Features. Description S 7 6 D 5 D 4 S GIPG ALS

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STL7N6M N-channel 6 V,.9 Ω typ., 5 A MDmesh M Power MOSFET in a PowerFLAT 5x5 package Datasheet - production data Features Order code V DS @ Tjmax R DS(on) max 7 6 5 STL7N6M 65 V.

1 STL7N6M N-channel 6 V,.9 Ω typ., 5 A MDmesh M Power MOSFET in a PowerFLAT 5x5 package Datasheet - production data Features Order code V Tjmax R DS(on) max STL7N6M 65 V.5 Ω 5 A Extremely low gate charge Excellent output capacitance (C OSS ) profile % avalanche tested Zener-protected G() Figure : Internal schematic diagram D(5, 6,, ) PowerFLAT 5x5 D D G S 9 S 8 S 7 6 D 5 D Applications Switching applications Description This device is an N-channel Power MOSFET developed using MDmesh M technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. S(, 3,, 7, 8, 9) NC Pin identification S 3 S S Top View GIPG6596ALS Table : Device summary Order code Marking Package Packaging STL7N6M 7N6M PowerFLAT 5x5 Tape and reel January 5 DocID77 Rev /3 This is information on a product in full production.

2 Contents STL7N6M Contents Electrical ratings... 3 Electrical characteristics.... Electrical characteristics (curves) Test circuits... 8 Package mechanical data Package mechanical data... 5 Revision history... /3 DocID77 Rev

3 STL7N6M Electrical ratings Electrical ratings Table : Absolute maximum ratings Symbol Parameter Value Unit V GS Gate-source voltage ± 5 V Drain current (continuous) at T C = 5 C 5 A Drain current (continuous) at T C = C 3. A M () () () M ()() Drain current (pulsed) A Drain current (continuous) at T pcb = 5 C. A Drain current (continuous) at T pcb = C.8 A Drain current (pulsed).8 A P TOT Total dissipation at T C = 5 C 67 W P TOT () Total dissipation at T pcb = 5 C W dv/dt (3) Peak diode recovery voltage slope 5 V/ns dv/dt () MOSFET dv/dt ruggedness 5 V/ns T stg Storage temperature - 55 to 5 C Max. operating junction temperature 5 C Notes: () Pulse width limited by safe operating area. () When mounted on FR- Board of inch², oz Cu (t < s) (3) ISD 5 A, di/dt A/µs; V DS peak < V (BR)DSS, V DD = V. () VDS 8 V Table 3: Thermal data Symbol Parameter Value Unit R thj-case Thermal resistance junction-case max.83 C/W R thj-pcb Thermal resistance junction-pcb max 3.3 C/W Table : Avalanche characteristics Symbol Parameter Value Unit I AR E AS Avalanche current, repetitive or not repetitive (pulse width limited by max) Single pulse avalanche energy (starting = 5 C, = I AR; V DD = 5 V) A 8 mj DocID77 Rev 3/3

4 Electrical characteristics STL7N6M Electrical characteristics T C = 5 C unless otherwise specified Table 5: On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS SS I GSS Drain-source breakdown voltage Zero gate voltage Drain current Gate-body leakage current V GS = V, = ma 6 V V GS = V, V DS = 6 V µa V GS = V, V DS = 6 V, T C = 5 C µa V DS = V, V GS = ±5 V ± µa V GS(th) Gate threshold voltage V DS = V GS, = 5 µa 3 V R DS(on) Static drain-source onresistance V GS = V, = A.9.5 Ω Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance pf C oss Output capacitance V DS= V, f = MHz, pf V GS = V Reverse transfer C rss pf capacitance C oss eq. () Equivalent output capacitance V DS = to 8 V, V GS = V pf R G Intrinsic gate resistance f = MHz, = A Ω Q g Total gate charge V DD = 8 V, = 5 A, V GS = V nc Q gs Gate-source charge (see Figure 5: "Gate charge nc Q gd Gate-drain charge test circuit") nc Notes: () Coss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when V DS increases from to 8% V DSS Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time V DD = 3 V, =.5 A ns t r Rise time R G =.7 Ω, V GS = V (see Figure : "Switching times ns t d(off) Turn-off-delay time test circuit for resistive load" and ns t f Fall time Figure 9: "Switching time waveform") ns /3 DocID77 Rev

5 STL7N6M Table 8: Source drain diode Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit I SD Source-drain current - 5 A I SDM () V SD () t rr Q rr I RRM t rr Q rr I RRM Source-drain current (pulsed) - A Forward on voltage V GS = V, I SD = 5 A -.6 V Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current Notes: () Pulse width is limited by safe operating area () Pulsed: pulse duration = 3 µs, duty cycle.5% I SD = 5 A, di/dt = A/µs, V DD = 6 V (see Figure 9: "Switching time waveform") I SD = 5 A, di/dt = A/µs, V DD = 6 V, = 5 C (see Figure 9: "Switching time waveform") - 75 ns -.55 µc - A ns -. µc - A DocID77 Rev 5/3

6 Electrical characteristics. Electrical characteristics (curves) (A) Figure : Safe operating area GIPG653ALS STL7N6M Figure 3: Thermal impedance GIPG75ALS K δ =.5 δ =. - δ =..... Operation in this area is limited by max R DS(on) µs µs ms ms =75 C T pcb =5 C Single pulse V DS δ =. SINGLE PULSE δ =.5 δ =. Z thj-pcb = KR thj-pcb δ = t p / Ƭ t p Ƭ T p (s) Figure : Output characteristics (A) V GS =7, 8, 9,, V AM585v Figure 5: Transfer characteristics (A) AM586v 8 6V 8 V DS = 9 V 6 6 5V 3V V 5 5 V DS 6 8 V GS Figure 6: Gate charge vs gate-source voltage V GS 8 6 VDS VDD=8V ID=5A 6 8 V DS AM58v 5 3 Qg(nC) Figure 7: Static drain-source on-resistance R DS(on) (Ω) V GS = V 3 GIPG656ALS 5 (A) 6/3 DocID77 Rev

7 STL7N6M Figure 8: Capacitance variations C AM588v (pf) Electrical characteristics Figure 9: Output capacitance stored energy E OSS (µj).5 AM589v Ciss. f = Mhz Coss.5. Crss.5.. V DS V DS Figure : Normalized gate threshold voltage vs temperature V GS(th) (norm).. = 5 µa AM578v Figure : Normalized on-resistance vs temperature R DS(on) (norm).5. AM58v.9.7 V GS = V ( C) ( C) Figure : Source-drain diode forward characteristics V SD AM58v = -5 C = 5 C = 5 C Figure 3: Normalized V(BR)DSS vs temperature V (BR)DSS (norm).9.5. = ma AM583v I SD (A) ( C) DocID77 Rev 7/3

8 Test circuits STL7N6M 3 Test circuits Figure : Switching times test circuit for resistive load Figure 5: Gate charge test circuit VDD V 7 k Ω kω nf Vi V GS I G = CONST Ω D.U.T. μ F.7 k Ω VG 7 k Ω PW kω AM69v Figure 6: Test circuit for inductive load switching and diode recovery times Figure 7: Unclamped inductive load test circuit Figure 8: Unclamped inductive waveform V (B R)DS S Figure 9: Switching time waveform t on toff t d(on) t r t d(off) t f V D 9% 9% M % % V DS V DD V DD V GS 9% AM7v % AM73v 8/3 DocID77 Rev

9 STL7N6M Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. DocID77 Rev 9/3

10 Package mechanical data. Package mechanical data Figure : PowerFLAT 5x5 drawings STL7N6M Pin identification 83653_A_type_S /3 DocID77 Rev

11 STL7N6M Dim. Package mechanical data Table 9: PowerFLAT 5x5 mechanical data mm Min. Typ. Max. A.8. A..5 A.5 b.3.5 D 5. D.5.5 E 5. E.6.79 E.5.5 e.7 L.5.75 Figure : PowerFLAT 5x5 recommended footprint (dimensions are in mm) 83653_A DocID77 Rev /3

12 Revision history STL7N6M 5 Revision history Table : Document revision history Date Revision Changes 6-Jan-5 First release. /3 DocID77 Rev

13 STL7N6M IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 5 STMicroelectronics All rights reserved DocID77 Rev 3/3

Features. Description. Table 1: Device summary Order code Marking Package Packaging STW40N65M2 40N65M2 TO-247 Tube

Features. Description. Table 1: Device summary Order code Marking Package Packaging STW40N65M2 40N65M2 TO-247 Tube N-channel 650 V, 0.087 Ω typ., 32 A MDmesh M2 Power MOSFET in a TO-247 package Datasheet - production data Features Order code V DS R DS(on) max. I D STW40N65M2 650 V 0.099 Ω 32 A TO-247 1 3 2 Extremely