N-channel 600 V, 1.06 Ω typ., 4.5 A MDmesh M2 Power MOSFETs in D 2 PAK and DPAK packages. Features. Description. AM15572v1. Table 1.

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1 STB6N60M2, STD6N60M2 N-channel 600 V, 1.06 Ω typ., 4.5 A MDmesh M2 Power MOSFETs in D 2 PAK and DPAK packages Features Datasheet - production data Order code V T Jmax R DS(on) max I D TAB D PAK TAB DPAK 1 3 STB6N60M2 STD6N60M2 650 V 1.2 Ω 4.5 A Extremely low gate charge Excellent output capacitance (C oss ) profile 100% avalanche tested Zener-protected Figure 1. Internal schematic diagram, TAB Applications Switching applications Description These devices are N-channel Power MOSFETs developed using MDmesh M2 technology. Thanks to their strip layout and improved vertical structure, the devices exhibit low on-resistance and optimized switching characteristics, rendering them suitable for the most demanding high efficiency converters. AM15572v1 Table 1. Device summary Order code Marking Package Packing STB6N60M2 STD6N60M2 6N60M2 D 2 PAK DPAK Tape and reel May 2016 DocID Rev 3 1/21 This is information on a product in full production.

2 Contents STB6N60M2, STD6N60M2 Contents 1 Electrical ratings Electrical characteristics Electrical characteristics (curves) Test circuits Package information D²PAK(TO-263) package information DPAK(TO-252) package information Packing information Revision history /21 DocID Rev 3

3 STB6N60M2, STD6N60M2 Electrical ratings 1 Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit V GS Gate-source voltage ±25 V I D Drain current (continuous) at T C = 25 C 4.5 A I D Drain current (continuous) at T C = 100 C 2.9 A I (1) DM Drain current (pulsed) 18 A P TOT Total dissipation at T C = 25 C 60 W dv/dt (2) Peak diode recovery voltage slope 15 dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns T stg Storage temperature range T j Operating junction temperature range -55 to 150 C 1. Pulse width limited by safe operating area 2. I SD 4.5 A, di/dt 400 A/µs; V DS peak < V (BR)DSS, V DD =400 V 3. V DS 480 V Table 3. Thermal data Symbol Parameter D 2 PAK Value DPAK Unit R thj-case Thermal resistance junction-case max 2.08 C/W R thj-pcb Thermal resistance junction-pcb max (1) C/W 1. When mounted on 1 inch² FR-4, 2 Oz copper board Table 4. Avalanche characteristics Symbol Parameter Value Unit I AR E AS Avalanche current, repetitive or not repetitive (pulse width limited by T jmax ) Single pulse avalanche energy (starting T j =25 C, I D = I AR ; V DD = 50 V) 1 A 86 mj DocID Rev 3 3/21 21

4 Electrical characteristics STB6N60M2, STD6N60M2 2 Electrical characteristics (T C = 25 C unless otherwise specified) Table 5. On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS I DSS Drain-source breakdown voltage Zero gate voltage drain current (V GS = 0) 1. Defined by design, not subject to production test I D = 1 ma, V GS = V V DS = 600 V 1 µa V DS = 600 V, T C =125 C (1) 100 µa Gate-body leakage I GSS V current (V DS = 0) GS = ± 25 V ±10 µa V GS(th) Gate threshold voltage V DS = V GS, I D = 250 µa V Static drain-source R DS(on) V on-resistance GS = 10 V, I D = 2.25 A Ω Table 6. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance pf C oss Output capacitance V DS = 100 V, f = 1 MHz, pf C rss V GS = 0 Reverse transfer capacitance pf Coss eq.(1) Equivalent output capacitance V DS = 0 to 480 V, V GS = pf R G Intrinsic gate resistance f = 1 MHz open drain Ω Q g Total gate charge V DD = 480 V, I D = 4.5 A, nc Q gs Gate-source charge V GS = 10 V nc Q gd Gate-drain charge (see Figure 16) nc 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 7. Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time ns t V DD = 300 V, I D = 1.65 A, r Rise time ns R G = 4.7 Ω, V GS = 10 V t d(off) Turn-off delay time ns (see Figure 15 and Figure 20) t f Fall time ns 4/21 DocID Rev 3

5 STB6N60M2, STD6N60M2 Electrical characteristics Table 8. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit I SD Source-drain current A I (1) SDM Source-drain current (pulsed) - 18 A V (2) SD Forward on voltage I SD = 4.5 A, V GS = V t rr Reverse recovery time ns Q rr Reverse recovery charge I SD = 4.5 A, di/dt = 100 A/µs V DD = 60 V (see Figure 17) µc I RRM Reverse recovery current A t rr Reverse recovery time I SD = 4.5 A, di/dt = 100 A/µs ns Q rr Reverse recovery charge V DD = 60 V, T j = 150 C µc I RRM Reverse recovery current (see Figure 17) A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID Rev 3 5/21 21

6 Electrical characteristics STB6N60M2, STD6N60M2 2.1 Electrical characteristics (curves) Figure 2. Safe operating area for D 2 PAK ID (A) AM15885v1 Figure 3. Thermal impedance for D 2 PAK Operation in this area is Limited by max RDS(on) Tj=150 C Tc=25 C Single pulse VDS(V) 10µs 100µs 1ms 10ms Figure 4. Safe operating area for DPAK ID (A) AM15875v1 Figure 5. Thermal impedance for DPAK Operation in this area is Limited by max RDS(on) Tj=150 C Tc=25 C Single pulse VDS(V) 10µs 100µs 1ms 10ms Figure 6. Output characteristics ID (A) 8 7 V GS = 8, 9, 10 V V GS = 7 V AM15876v1 Figure 7. Transfer characteristics ID (A) 8 7 AM15877v1 V DS = 20 V V GS = 6 V V GS = 5 V V GS = 4 V VDS(V) VGS(V) 6/21 DocID Rev 3

7 STB6N60M2, STD6N60M2 Electrical characteristics Figure 8. Gate charge vs gate-source voltage VGS (V) VDD = 480V 12 ID = 4.5 A VDS AM15878v1 VDS (V) 500 Figure 9. Static drain-source on-resistance RDS(on) (Ω) VGS=10V AM15879v Qg(nC) Figure 10. Capacitance variations C (pf) AM15880v1 Ciss Coss Crss VDS(V) Figure 12. Normalized gate threshold voltage vs temperature VGS(th) AM15882v1 (norm) 1.1 ID=250 µa TJ( C) ID(A) Figure 11. Normalized V DS vs temperature VDS (norm) 1.11 I =1 ma D TJ( C) Figure 13. Normalized on-resistance vs temperature RDS(on) (norm) VGS=10 V TJ( C) AM15881v1 AM15883v1 DocID Rev 3 7/21 21

8 Electrical characteristics STB6N60M2, STD6N60M2 Figure 14. Source-drain diode forward characteristics AM15884v1 VSD (V) TJ=-50 C TJ=150 C TJ=25 C ISD(A) 8/21 DocID Rev 3

9 STB6N60M2, STD6N60M2 Test circuits 3 Test circuits Figure 15. Switching times test circuit for resistive load Figure 16. Gate charge test circuit VDD 12V 47kΩ 100nF 1kΩ VGS VD RG RL D.U.T μf 3.3 μf VDD Vi=20V=VGMAX 2200 μf IG=CONST 2.7kΩ 100Ω D.U.T. VG PW 47kΩ PW 1kΩ AM01469v1 AM01468v1 Figure 17. est circuit for inductive load switching and diode recovery times Figure 18. Unclamped inductive load test circuit L G D A D.U.T. A FAST DIODE A L=100μH VD 2200 μf 3.3 μf VDD 25 Ω S B B B D μf μf VDD ID RG G S Vi D.U.T. AM01470v1 Pw AM01471v1 Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform ton toff tdon tr tdoff tf 0 90% 10% VDS 10% 90% VGS 90% 0 10% AM01473v1 DocID Rev 3 9/21 21

10 Package information STB6N60M2, STD6N60M2 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. 10/21 DocID Rev 3

11 STB6N60M2, STD6N60M2 Package information 4.1 D²PAK(TO-263) package information Figure 21. D²PAK (TO-263) type A package outline DocID Rev 3 11/21 21

12 Package information STB6N60M2, STD6N60M2 Table 9. D²PAK (TO-263) type A mechanical data Dim. mm Min. Typ. Max. A A b b c c D D D E E E e 2.54 e H J L L L R 0.4 V /21 DocID Rev 3

13 STB6N60M2, STD6N60M2 Package information Figure 22. D²PAK footprint (a) a. All dimension are in millimeters DocID Rev 3 13/21 21

14 Package information STB6N60M2, STD6N60M2 4.2 DPAK(TO-252) package information Figure 23. DPAK (TO-252) type C outline 14/21 DocID Rev 3

15 STB6N60M2, STD6N60M2 Package information Table 10. DPAK (TO-252) type C package mechanical data Dim. mm Min. Typ. Max. A A A b b c c D D E e E H L L REF L L BSC L L BSC Θ Θ V2 0 8 DocID Rev 3 15/21 21

16 Package information STB6N60M2, STD6N60M2 Figure 24. DPAK (TO-252) footprint (b) b. All dimensions are in millimeters 16/21 DocID Rev 3

17 STB6N60M2, STD6N60M2 Packing information 5 Packing information Table 11. D²PAK (TO-263) tape and reel mechanical data Tape Reel Dim. mm mm Dim. Min. Max. Min. Max. A A 330 B B 1.5 D C D D 20.2 E G F N 100 K T 30.4 P P Base qty 1000 P Bulk qty 1000 R 50 T W DocID Rev 3 17/21 21

18 Packing information STB6N60M2, STD6N60M2 Table 12. DPAK (TO-252) tape and reel mechanical data Tape Reel Dim. mm mm Dim. Min. Max. Min. Max. A A 330 B B 1.5 B C D D 20.2 D1 1.5 G E N 50 F T 22.4 K P Base qty P Bulk qty P R 40 T W /21 DocID Rev 3

19 STB6N60M2, STD6N60M2 Packing information Figure 25. Tape 10 pitches cumulative tolerance on tape +/- 0.2 mm T Top cover tape P0 D P2 E B1 K0 B0 F W For machine ref. only including draft and radii concentric around B0 A0 P1 D1 User direction of feed R User direction of feed Bending radius AM08852v1 REEL DIMENSIONS Figure 26. Reel 40mm min. T Access hole At sl ot location D B C A N Full radius Tape slot in core for tape start 25 mm min. width G measured at hub AM08851v2 DocID Rev 3 19/21 21

20 Revision history STB6N60M2, STD6N60M2 6 Revision history Table 13. Document revision history Date Revision Changes 11-Jun First release. 09-Jul May Minor text changes Modified: R thj-case value for D 2 PAK in table 3 Updated title, features and description. Updated Table 6: Dynamic and Table 8: Source drain diode. Updated Section 4: Package information and Section 5: Packing information. Minor text changes. 20/21 DocID Rev 3

21 STB6N60M2, STD6N60M2 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved DocID Rev 3 21/21 21