3D activities and plans in Italian HEP labs Valerio Re INFN Pavia and University of Bergamo

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Claribel Ellis
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1 3D activities and plans in Italian HEP labs Valerio Re INFN Pavia and University of Bergamo 1

2 Vertical integration technologies in Italian R&D programs In Italy, so far interest for 3D vertical integration of sensors and readout electronics mainly comes from people involved in MAPS developments and in tracking and vertexing systems in ILC and SuperB 3D could address needs to operate pixel detectors at high rate with low material budget to optimize position and momentum resolution; information from the tracking system could be used in a Level 1 trigger system Vertical integration would offer solutions for a higher functional density and a better signal-to-noise ratio and charge collection efficiency as compared to 2-D MAPS 2

3 CMOS MAPS R&D: the Italian way 130nm Deep NWell MAPS design for SuperB the APSEL series chips with sparsified readout and time stamping (see talk on SuperB Vertex Detector) Funding by INFN (SLIM5 collaboration) and Italian Ministry of University and Research (PRIN) 130nm DNW CMOS MAPS for the ILC Vertex Detector smaller pitch and power dissipation, different readout architecture funding by INFN (P-ILC collaboration) 180nm and 130nm bulk CMOS MAPS Various readout architectures, small pixels funding by INFN (Perugia and Roma3 groups) 3

Deep N-Well (DNW) sensor concept New approach in CMOS MAPS design compatible with data sparsification architecture to improve the readout speed potential PREAMPL SHAPER DISC LATCH Classical optimum

4 Deep N-Well (DNW) sensor concept New approach in CMOS MAPS design compatible with data sparsification architecture to improve the readout speed potential PREAMPL SHAPER DISC LATCH Classical optimum signal processing chain for capacitive detector can be implemented at pixel level: Charge-to-Voltage conversion done by the charge preamplifier The collecting electrode (Deep N-Well) can be extended to obtain higher single pixel collected charge (the gain does NOT depend on the sensor capacitance), reducing charge loss to competitive N-wells where PMOSFETs are located Fill factor = DNW/total n-well area ~90% in the prototype test structures 4

5 Why hybrid-pixel-like MAPS Modern VLSI CMOS processes (130 nm and below) could be exploited to increase the functionality in the elementary cell sparsified readout of the pixel matrix. Data sparsification could be an important asset at future particle physics experiments (ILC, Super B-Factory) where detectors will have to manage a large data flow A readout architecture with data sparsification will be a new feature which could give some advantages with respect to existing MAPS implementations flexibility in dealing with possible luminosity and background changes during the experiment lifespan, decouple modularity from readout speed An ambitious goal is to design a monolithic pixel sensor with similar readout functionalities as in hybrid pixels (sparsification, time stamping) 5

6 130 nm DNW MAPS: first generation of CMOS sensors with in-pixel sparsification and time stamping (to be tested in a beam quite soon) SLIM5 APSEL3D APSEL4D SDR0 8x32 matrix. Shielded pixel Data Driven sparsified readout 32x128 matrix. Data Driven, continuously operating sparsified readout Beam test Sep x16 matrix + smaller test structures. Intertrain sparsified readout 50x50 um pitch 25x25 um pitch 6

7 130nm CMOS DNW MAPS for the ILC vertex detector 7 INFN program started in 2006; design DNW MAPS according to ILC specifications (INFN Milano, Pavia, Roma III; University of Bergamo, University of Insubria, University of Pavia) Same concept as in the APSEL chips, but reduced pixel pitch and power dissipation Digital readout architecture with in-pixel sparsification logic and time stamping, taking into account the beam structure of ILC A pipeline with a depth of one in each cell should be sufficient to record > 99% of events without ambiguity Data can be readout in the intertrain interval system EMI insensitive 7

8 Sparsified readout architecture 8 In DNW MAPS sensors for ILC sparsification is based on a token passing readout scheme suggested by R. Yarema (FNAL) (R. Yarema, Fermilab Initiatives in 3D Integrated Circuits and SOI Design for HEP, ILC VTX Workshop at Ringberg, May 2006) This architecture was first implemented by Fermilab ASIC designers Jim Hoff, Tom Zimmerman and Gregory Deptuch in the VIP1 chip (3-D MIT LL technology, see Fermilab presentation on Wednesday) MAPS sensor operation is tailored on the structure of ILC beam Detection phase (corresponding to the bunch train interval) Readout phase (corresponding to the intertrain interval) 8

9 Pixel level processor 9 Preamplifier -G(s) 22T 14T C F obtained from the source-drain capacitance C F V t Discriminator High frequency noise contribution has been reduced limiting the PA bandwidth From simulations: i F ENC=25 e - rms@c D =100 ff Preamplifier output [V] Preamplifier response to an 800 e - pulse i =3 na F i F =5 na i =10 na F i F =15 na t [μs] Threshold dispersion 30 e - rms Power consumption 5 μw Features power-down capabilities for power saving: the analog section cell can be switched off during the intertrain interval in order to save power (1% duty-cycle seems feasible) 9

10 Cell digital section 10 Includes a 5 bit time stamp register and the data sparsification logic During the bunch train period, the hit latch is set in each hit pixel When the pixel is hit, the content of the time stamp register gets frozen Get X bus Get Y bus 4T Master Reset To the time stamp buffer From the discriminator 10T 13T 20T S hit D Q getb_en Q R hitb CP Qb Qb Lat_en tokin CPb tokout tokrst hit latch token passing core Cell CK Cell CK Get bus latch 76T time stamp register WE OE OEb t1 t2 t3 t4 t5 t1in t2in t3in t4in t5in From the time stamp counter 10

11 ILC DNW elementary cell 11 Preamplifier Discriminator analog front-end + digital section DNW sensor 25 μm 164 transistors 25 μm 11

Digital readout scheme 12 Cell CK gets caught by the first 4 5 4 5 4 5 Time Stamp Time Time hit pixel X=1 Buffer 1 X=2 Stamp X=16 Stamp the pixel points to the 1 1 Buffer 2 1 Buffer 16 X and Y

12 Digital readout scheme 12 Cell CK gets caught by the first Time Stamp Time Time hit pixel X=1 Buffer 1 X=2 Stamp X=16 Stamp the pixel points to the 1 1 Buffer 2 1 Buffer 16 X and Y registers at Cell (1,1) 5 Cell (1,2) 5 Cell (1,16) 5 the periphery and gxb gxb gxb gxb=get_x_bus First Hit sends off the time TS TS TS pixel gyb=get_y_bus token in stamp register content Tkin Tkout Tkin Tkout Tkin Tkout TS=Time_Stamp 4 data are serialized and 1 gyb gyb gyb Y=1 Tkin=token_in scans ahead Tkout=Token_out Cell (2,1) gxb Cell (2,2) gxb Cell (2,16) gxb 4 4 Y=2 Last token out Y= Tkout Readout CK X Y T MUX Serial data output TS TS TS Tkin Tkout Tkin Tkout Tkin gyb gyb Cell (16,1) gxb Cell (16,2) gxb Cell (16,16) gxb TS TS TS Tkout Tkin Tkout Tkin Tkout Tkin gyb gyb gyb gyb Readout phase: tokenissent token scans the matrix and The number of elements may be increased without changing the pixel logic (just larger X- and Y- registers and serializer will be required) 12

in the 3x3 matrix 2_2 2_1 2_3 3_1 1_3 1_2 3_2 ENC = 40 e rms @ C D =120 ff (preamplifier input device: I D = 1 μa, W/L

13 SDR0 experimental results 13 0,08 Matrix response to infrared laser Average charge sensitivity 0.7 V/fC preamplifier output [V] 0,07 0,06 0,05 0,04 0,03 0,02 central pixel response to injected charge other 8 pixels in the 3x3 matrix 2_2 2_1 2_3 3_1 1_3 1_2 3_2 ENC = 40 e C D =120 ff (preamplifier input device: I D = 1 μa, W/L = 22/0.25) Threshold dispersion 60 e (in 8x8 matrix) 0,01 1_1 3_ Time [μs] Digital readout is working fine Test with 55 Fe 13

14 CMOS APS: RAPS/SHARPS Perugia UMC 0.18μm m MM 1P6M bulk CMOS technology (twin-tub, tub, no-epi epi) RAPS02 APS 3T/ architecture (nmos& pmos); from 4x4μm 2 to 10x10μm 2 pixel size; sparse read-out; high-gain, in-pixel amplification; self-reset mode (event-triggered). WIPS SHARPS

15 Explore more advanced technological solutions: Vertical Integration R&D proposal submitted to MUR (Oct. 2007): Pixel systems for thin charged particle trackers based on high density microelectronic technologies (Universities of Pisa, Pavia, Bergamo, Bologna) The problem of thin pixel detectors is tackled from various sides: Develop a 128x128 DNW pixel matrix that can be used in an experiment (ILC or SuperB) Develop a readout architecture allowing operation in high rate environments Explore innovative cooling technologies where microchannels are integrated directly in the silicon substrate Explore Vertical Integration Technology Hopefully start R&D in summer 2008 (PRIN Project submitted, pending approval ) These technologies might not be ready when the SuperB construction starts but could be mature for an upgrade of Layer 0 (we need to design an interaction region with easier access & replacement). 15

16 Explore more advanced technological solutions: Vertical Integration R&D aiming at ASIC/pixel sensor interconnection for ILC (15-20 μm pitch) and Super B-Factory (50 μm pitch) vertex detectors with in-pixel data sparsification Overcome limitations typically associated to conventional and DNW CMOS MAPS: Fully depleted thick substrate, 100 % fill factor, better S/N vs power dissipation performance, pixel pitch, possible analog-to-digital interferences, 16

17 Ideas for Vertical Integration of Pixel Sensors Three possible implementations: Vertical integration of a 130nm CMOS readout chip with a high resistivity fully-depleted pixel sensor 100 μm total thickness Vertical integration between two layers of 130nm CMOS chips. The first layer may include a MAPS device with analog readout, and the second layer the digital readout circuits (from an idea of Ray Yarema) - Vertical integration of multiple, thinned and stacked CMOS MAPS improve the spatial/angular ionizing particle trajectory resolution (Perugia group) 17

18 3D vertical integration based on DNW MAPS (conceptual) 18 Use vertical integration technology to interconnect two 130nm CMOS layers (R. Yarema) Handle for CMOS Mostly digital CMOS tier Tier interconnection and vias with industrial technique Analog and sensor CMOS (mostly NMOS) tier NMOS Deep N-well structure NMOS PMOS P-well Buried N-type layer P-substrate Standard CMOS PMOS Standard N-well 18

spatial/angular ionizing particle trajectory resolution.

19 3D CMOS APS Perugia 3D approach to vertexing issues: adoption of multiple thinned, stacked, fully functional CMOS APS detectors. Aim: to reduce the multiple scattering / material problems (especially y in high magnetic field regions); to improve the spatial/angular ionizing particle trajectory resolution. Proof of concept: 2D device-level simulation; spatial/angular resolution enhancement. Requirements: Vertical alignment 1 micron; pitch 10 microns; tier depth 15/20 microns; Through-Silicon Vias technology OK.

20 To sum up In Italy R&D activity on 3D vertical integration technology is presently in a conceptual stage Italian groups are looking to different ideas and technologies using vertical integration to improve the performance of CMOS MAPS In the DevDet FP7 project, Italian groups are taking part in the Task on 3D interconnection of microelectronics and semiconductor detectors 20

Deep N-well CMOS MAPS with in-pixel signal processing and sparsification capabilities for the ILC vertex detector

Deep N-well CMOS MAPS with in-pixel signal processing and sparsification capabilities for the ILC vertex detector, Massimo Manghisoni, Valerio Re University of Bergamo Via Marconi, 20 Dalmine (BG), Italy.