3D devices for the ILC

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Horatio Pearson
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3D devices for the ILC Our work on 3D integrated circuits began when we considered challenges of an ILC vertex detector in 2006 High resolution small pixels Low mass thinned sensors and electronics

1 3D devices for the ILC Our work on 3D integrated circuits began when we considered challenges of an ILC vertex detector in 2006 High resolution small pixels Low mass thinned sensors and electronics Time stamping preferably to a single crossing Efficient power delivery low power electronics This led us to investigate an emerging technology which promised to solve many of the ILC problems and provide R. Lipton 1

3D Integrated Circuits A chip in three-dimensional integrated circuit (3D-IC) technology is

and vertical inter-tier connectivity routing Through Silicon Vias (TSV): small diameter

to readouts) Bonding: Oxide-, polymer-, metal-, or adhesive strengthened- (Wafer-Wafer,

metallization and patterning Back-Face Face-Face MIT-LL 3D-IC process FDSOI oxideoxide

2 3D Integrated Circuits A chip in three-dimensional integrated circuit (3D-IC) technology is composed of two or more layers of active electronic components using horizontal intra-tier and vertical inter-tier connectivity routing Through Silicon Vias (TSV): small diameter vertical connectivity (not only to build electronic chips but also for attaching detectors to readouts) Bonding: Oxide-, polymer-, metal-, or adhesive strengthened- (Wafer-Wafer, Chip-Wafer or Chip-Chip) Wafer thinning: aggressive and ultraprecise Back-side processing: metallization and patterning Back-Face Face-Face MIT-LL 3D-IC process FDSOI oxideoxide bonding Tezzaron 3D-IC bulk CMOS Cu-Cu thermocompression or DBI bonding TS Vias (f=1mm) Face-Face R. Lipton 2

3D Interconnect Technology based on: Bonding

fusion Copper/tin bonding Polymer/adhesive

and metalization Copper bonded two-tier IC

oxide bonded imager (Lincoln Labs) 8 micron

3 3D Interconnect Technology based on: Bonding between layers Copper/copper Oxide to oxide fusion Copper/tin bonding Polymer/adhesive bonding Cu stud Through wafer via formation and metalization Copper bonded two-tier IC (Tezzaron) 8 micron pitch, 50 micron thick oxide bonded imager (Lincoln Labs) 8 micron pitch DBI (oxide-metal) bonded PIN imager (Ziptronix) 3

4 3D For Particle Physics Why is 3D technology important for HEP? We care about bonding sensors to complex analog/digital electronics It enables intimate interconnection between sensors and readout circuits Subpixel readout and control of SiPMs It enables unique functionality Digital/analog/ and data communication tiers Two layer micro/macro pixel designs which can provide high resolution with minimal circuitry Can correlate information to help defeat noise Wafer thinning enables low mass, high resolution sensors Bonding technologies enable very fine pitch, high resolution pixelated devices Commercialization of 3D can reduce costs for large areas Unique circuit/sensor topologies (CMS track trigger) R. Lipton 4

5 Bonding Costs and Yields <$1/cm 2? Current and projected costs and yields for sensor/readout integration technologies

18 micron SOI CMOS Bonding, thinning and detector laser anneal technology We were invited to

6 History - MIT-LL 3D Technology MIT-LL had developed a 3D technology which seemed an excellent match to ILC needs. Demonstrated 50 micron thick bonded sensor/readout 3 Tiers of 0.18 micron SOI CMOS Bonding, thinning and detector laser anneal technology We were invited to participate in 2 DARPA-sponsored 3D runs. Submitted the VIP ILC Vertex chip. Made significant contributions to the submission debugging...

7 VIP Chip Chip designed for ILC Vertex Low power front end Digital and and analog time stamp Sparse scan readout 20(VIP1) 24(VIP2a) micron pitch Initial submission had low yield and marginal functionality due to MIT-LL process issues. Second submission with a more conservative design worked well. Converted to 0.13 micron CMOS for 3D Tezzaron run VIP2b. This gave us experience and confidence - next steps: Move to a commercial process (Tezzaron, Ziptronix) FNAL designs for x-ray (VIPIC), LHC (VICTR), ILC (VIP2b) applications

3D Sensor/ROIC Bonding A promising fine pitch bonding technology the direct bond interconnect (DBI) oxide bond process from Ziptronix now licensed to Novati No bump bonds planar resulting wafer Very

8 3D Sensor/ROIC Bonding A promising fine pitch bonding technology the direct bond interconnect (DBI) oxide bond process from Ziptronix now licensed to Novati No bump bonds planar resulting wafer Very fine pitch - 4 microns used for 3D Tezzaron wafers Mechanical strength enables aggressive post-bond thinning Uses standard IC processes - CMP and metalization Can withstand high temp. Wafer-wafer bond can be reworkable In principal can be low cost R. Lipton 8

Sensor chip to FPIX wafer bond Sensors ground to 100 microns - 8 V depletion 100%

9 Oxide Bond Demonstration Initial work was based on existing ROIC wafers from BTeV and sensor wafers from MIT-LL. Sensor chip to FPIX wafer bond Sensors ground to 100 microns - 8 V depletion 100% connectivity on sensors without obvious bond voids No degradation in s/n Radiation hard to >10 MRad This the process that was eventually used for 3D wafers Threshold Noise

Fermilab 3D-IC run Initial (small) efforts started with MIT-LL 3D process in 2006 (DARPA 3-tier 3D run): 3D-IC Consortium established in late 2008, now 17 members; 6 countries: USA, Italy, France,

Fermilab organized first 3D-IC MPW run for HEP Designs in: 05/2009; Chartered (GF) 130nm Fermilab had a role of silicon broker Many challenges in working with cutting edge technology: design

10 Fermilab 3D-IC run Initial (small) efforts started with MIT-LL 3D process in 2006 (DARPA 3-tier 3D run): 3D-IC Consortium established in late 2008, now 17 members; 6 countries: USA, Italy, France, Germany, Poland, Canada) + Tezzaron various goals among members. Fermilab organized first 3D-IC MPW run for HEP Designs in: 05/2009; Chartered (GF) 130nm Fermilab had a role of silicon broker Many challenges in working with cutting edge technology: design mistakes, incompatibility of software tools (Tezzaron not Cadence), lack of 3D oriented verification, handling of databases >10GB, shifting GF requirements (DRC), changing personnel at GF, slow progress through fab etc. MPW frame accepted for fab in 03/ nm GF/Tezzaron wafer - FNAL MPW before 3D bonding; single mask set used to fabricate top and bottom tier chips on the same wafer; Bonding by flipping wafers over symmetry line LEFT (bottom) chips Right (top) chips 10

fusing metal pads, forgiving on surface planarity Cu DBI reworkable shortly after bonding,

11 Fermilab 3D-IC run Tezzaron / Novati Ziptronix / licensed to Novati Difference between Cu-Cu thermocompression and Cu DBI wafer bonding methods: Cu-Cu not reworkable, bonding established by fusing metal pads, forgiving on surface planarity Cu DBI reworkable shortly after bonding, bonding established by chemically fusing oxide surfaces, must be ultra planar 11 CMS review, March 18-19, 2013

12 Ziptronix DBI bonding array Interconnect array Bump bond pad 6 micron thick top silicon 4 micron pitch DBI Copper pillars

13 3D Process Development The original cu-cu bonding technique developed by Tezzaron had several issues Aging of top copper Wafer misalignment Misaligned Bond Interface (Too) Aggressive design rules mm octagons on a 4 mm pitch alignment between wafers must be better than 1 um The DBI-oxide bonding process has solved these problems. L M R L M R Cu-Cu Alignment Keys R. Lipton 13 DBI

14 Two-Tier Devices Final two-tier (no sensors) wafers were delivered in 2013 VICTR and VIPIC wafers were tested, both bare and with bump bonded sensors. Top Bottom Wire Bond pads 12 um VIPIC with bumps VICTR with top sensor and interposer R. Lipton 14

15 Two-tier results -VIPIC Preamp X6 Disc. VIPIC is a chip design for X-ray photon correlation spectroscopy with deadtimeless readout Separate analog/ditial tiers 25 inter-tier connections/pixel (64x64 80 m pixels) 16 Serial Output Lines (LVDS) ts=250 ns Inject/ option Feedback Th X64 Program latches Two 5 bit counters Sparsification Serializer and LVDS Output 1 of 16 Serial Output Lines Image with bump bonded sensor R. Lipton 15

array 1 mm bottom tier short strip Modified FEI4 (Atlas) front end Long strip tier

16 Two-tier results - VICTR VICTR chip is designed for CMS track trigger applications correlating hits in long and short strip tiers 64 5 mm top tier long strip 64 x 5 array 1 mm bottom tier short strip Modified FEI4 (Atlas) front end Long strip tier Short strip tier Threshold Noise Noise Short strip tier Long strip tier R. Lipton 16

17 Two-tier Results VIP2b VIP Functional block diagram How it works: array of 24x24 mm 2 pixels 8 bit digital time stamp (Dt=3.9 ms) Readout between ILC bunch trains of sparsified data Sparsification - token passing scheme Single stage signal integrating frontend with 2 S/H circuits for analog signal output with CDS Analog information available for improved resolution Serial output bus Polarity switch for collection of e - or h + Analog tier (top) Digital tier (bottom) A 17 D Test inject Integrator Analog out Discriminator Vth Write data Read all Hit latch S Q R Pixel skip logic D FF Data clk Time stamp circuit Read data T.S. out To x, y address Analog front end Pixel sparsification circuitry Time stamp

18 Front-end tests R. Lipton! 18

Test Pulse Voltage VIP Testing Successfully read out all 192x192 = 36,864 pixels Token passes though at 189 ps/pixel Possible issues with pixel masking, odd row test pulse 0.16 0.14 0.12 0.1 0.08 0.

19 Test Pulse Voltage VIP Testing Successfully read out all 192x192 = 36,864 pixels Token passes though at 189 ps/pixel Possible issues with pixel masking, odd row test pulse Vth y = x Threshold value X Y Read all mode V(test)= R. Lipton

Final Fabrication We then chip-to wafer oxide bonded 3D chips to BNL sensors to form integrated sensor/electronics assemblies parts received in March This completes our

20 Final Fabrication We then chip-to wafer oxide bonded 3D chips to BNL sensors to form integrated sensor/electronics assemblies parts received in March This completes our initial 3D work with Tezzaron and Ziptronix VIP(ILC), VICTR(CMS), and VIPIC(X-Ray) assemblies VIP VICTR VIP TSV DBI bond TSV VIPIC VIPIC DBI bond sensor R. Lipton R. Lipton 20

21 Chip-to-Wafer bond DBI bonding of ROICs (VICTR, VIPIC, VIP) to BNL sensor wafer R. Lipton 21

22 VIP 2-tier VIP chip 24 micron pitch pixels 192x192 25m sensor R. Lipton 22

23 DBI Interconnect VIPIC pixel Interconnect structure Shield metal Alignment structures Pad redistribution R. Lipton 23

24 Mounted detectors.5 mm sensor R. Lipton 24

modes of operation (64 64 matrix / in 16 sub-matrices of 4 64 pixels): 1) timed readout of hits acquired at low occupancy (address

25 3D-IC: Fermilab designs VIPIC 1400 transistors / pixel 280 transistors / pixel Digital part of pixel Pixel 80x80 mm 2 Analog part of pixel array of 80 mm 2 ; shaping time t p =250 ns, power ~25 mw / analog pixel, noise <150 e - ENC Two dead-time-less modes of operation (64 64 matrix / in 16 sub-matrices of 4 64 pixels): 1) timed readout of hits acquired at low occupancy (address and hit count) s t =10ms 2) imaging counting of events Sparsified readout with priority encoder circuit (hit pixel address readout only) 25

26 VIPIC Sensor results R. Lipton 26

27 VIPIC Sensor results R. Lipton 27

28 Large Area Arrays We have demonstrated new technologies for chip and sensor interconnect. For wide applicability we need to address yield, cost and commercial access. The goal is cheap, large area, fine pitch pixelated systems. Seamless, pixelated detectors deployed in large areas are important (crucial) for many applications in HEP, x-ray imaging and Nuclear Physics There are two possible approaches 1. Use the fact that wafer-scale sensors can be fabricated with good yield and bond an array of smaller readout chips to a large sensor Interconnect geometry is a central issue 2. Fabricate tiles which can be butted on all four sides to fabricate arrays of arbitrary size. R. Lipton 28

an interposer to connect multiple chips Finer pitch,

29 2.5D Industry is moving first toward 2.5-D This technology utilizes through-silicon vias on an interposer to connect multiple chips Finer pitch, better thermal expansion match than PC board technologies R. Lipton 29

30 Why 2.5D for HEP? A 2.5D substrate allows us to match large area sensors to chips limited by CMOS reticules to 2-3 cm on a side Can be an enabling technology for large area sensors and focal plane arrays ROIC interposer Wafer Scale Sensor These can also be very important for very high bandwidth trigger and memory systems such as an AM-based track trigger. R. Lipton 30

31 2.5D Design for CMS R. Lipton 31

connections Sensors can be processed to have active edges using deep reactive ion etch so

32 Combining the two 3Ds Low cost, large area, thin, pixelated sensor planes with no dead regions. Decouple bond and array yields 3D provides backside interconnect to eliminate peripheral bond connections Sensors can be processed to have active edges using deep reactive ion etch so assemblies can be tiled. 166 mm 117 mm CMS FPIX Plaquette 76 mm 28 mm SiD (ILC) Outer pixel disk R. Lipton 32

cost Tiles can populate complex shapes with optimal tiling and low dead area Only bump bonds

33 How can we do it with 3D? Combine active edge technology with 3D electronics and oxide bonding with throughsilicon vias to produce fully active tiles. These tiles can be used to build large area pixelated arrays with good yield and reasonable cost Tiles can populate complex shapes with optimal tiling and low dead area Only bump bonds are large pitch backside interconnects High density and geometrical flexibility Buried oxide 200 micron trenches MIT-LL 4 side buttable imager VTT Active Edge sensor readout IC and pads sensor Handle wafer R. Lipton 33

Tiling sensors 700m 6m 10m Stack Before Thinning ROIC Wafer TSV DBI Stack After Thinning Top interconnect Needs a robust, planar wafer-wafer bond

34 Tiling sensors 700m 6m 10m Stack Before Thinning ROIC Wafer TSV DBI Stack After Thinning Top interconnect Needs a robust, planar wafer-wafer bond to allow thinning and topside processing 75m Sensor 700m SOI Handle Wafer ~150m Carbon fiber support disk Interconnect circuit ~10m ~75m Tile Tile

from Cornell The two will be wafer-wafer DBI bonded by Ziptronix.

35 Demonstration Project A project to demonstrate this technology is underway using: active edge sensors from VTT, based on early CMS long/short strip PS module designs Dummy ROIC wafers from Cornell The two will be wafer-wafer DBI bonded by Ziptronix. Simulation of charge density due to 3.5GeV muon hitting near the edge- study charge collection and edge effects. R. Lipton 35

36 Etched test wafer R. Lipton 36

37 Cheaper Alternative? Process active edge after 3D integration No complex SOI structure No TSVs necessary Standard plasma dicing LBNL moderate temperature pizza process implant and anneal Die 1 CMOS Wafer Sensor wafer 3D bond Die 2 CMOS Wafer Sensor wafer Etch CMOS Wafer Thin, Expose top contacts, singulate Implant and anneal CMOS Wafer R. Lipton 37

38 Summary We are now able to use 3D technology to combine optimal sensors and readout without many of the compromises inherent in MAPS Our next step is to apply this to large area devices in HEP, x-ray imaging and perhaps other applications Particle Physics may be small compared to the scale of the $300B semiconductor industry, but we have a role to play As first adopters of promising technologies As developers of new concepts which utilize emerging technologies As partners in innovation To do this we must have the ability and will to take risks It s never as easy as it first sounds But it s worth the effort R. Lipton 38

39 3D Geometry FE + discrimination + sampling time stamping sparsification Chip designers: Tom Zimmerman Gregory Deptuch Jim Hoff 39

Recent Results for 3D Pixel Integrated Circuits using Copper-Copper and Oxide-Oxide Bonding

Recent Results for 3D Pixel Integrated Circuits using Copper-Copper and Oxide-Oxide Bonding 1 Fermi National Accelerator Laboratory* P. O. Box 500 Batavia, IL 60510 USA E-mail: yarema@fnal.gov G. Deptuch