Towards Monolithic Pixel Detectors for ATLAS HL-LHC Upgrades

Size: px

Start display at page:

Download "Towards Monolithic Pixel Detectors for ATLAS HL-LHC Upgrades"

Beatrice Bell
5 years ago
Views:

1 Towards Monolithic Pixel Detectors for ATLAS HL-LHC Upgrades Hans Krüger Bonn University FEE 2016 Meeting, Krakow

2 Outline Comparison of Pixel Detector Technologies for HL-LHC upgrades (ATLAS) Design Challenges for fast and radiation tolerant CMOS Active Pixel Sensors Prototype of a Monolithic Pixel chip for ATLAS: LF-MonoPix H. Krüger, FEE 2016, Krakow 2

Pixel Detectors: Hybrid and Monolithic STAR ALICE-LHC

ALICE-LHC ILC ATLAS-LHC ATLAS-HL-LHC Timing [ns] 200

250 1000 10000 Fluence [n eq /cm 2 ] > 10 12 > 10 13

3 Pixel Detectors: Hybrid and Monolithic STAR ALICE-LHC ILC ATLAS Requirements for inner pixel layers STAR ALICE-LHC ILC ATLAS-LHC ATLAS-HL-LHC Timing [ns] Particle Rate [khz/mm 2 ] Fluence [n eq /cm 2 ] > > x x x10 15 Ion. Dose [Mrad] > > Fully Depleted Monolithic CMOS for Outer Layers? H. Krüger, FEE 2016, Krakow 3

Standard Hybrid Pixel Detector reference (65nm) good (planar) very good (3D) CMOS Active Pixel Hybrid Detector similar / worse (65nm R/O chip, ~150nm sensor) good (as

Detector worse (~150nm tech.) good (as planar, tbc) worse (increased input capacitance, non std.

4 Hybrid Pixels vs. (Monolithic) CMOS Active Pixels depleted substrate Planar Pixel Sensor CMOS Active Pixel Sensor TID radiation hardness (electronics) NIEL radiation hardness (sensor) Standard Hybrid Pixel Detector reference (65nm) good (planar) very good (3D) CMOS Active Pixel Hybrid Detector similar / worse (65nm R/O chip, ~150nm sensor) good (as planar, tbc) Power consumption reference worse (increased input capacitance) Material budget (silicon only) reference equal better Fully Depleted Monolithic Pixel Detector worse (~150nm tech.) good (as planar, tbc) worse (increased input capacitance, non std. digital logic) Assembly costs reference (bump bonding) equal (still needs bump bonding or glue + TSV) Silicon costs reference (high) better (active CMOS sensor cheaper than planar?) Integration density (min. pixel size) reference (50µm pixels) possibly better Features/challenges sub-pixel encoding isolation of analog FE and digital activity H. Krüger, FEE 2016, Krakow 4 best best worse

5 Implementation Concepts Read-out Node Charge signal Charge signal Electronics (full CMOS) Electronics (full CMOS) P+ p-well nw P+ n+ p-well nw n+ Deep n-well deep p-well - p-substrate - p-substrate Electronics inside charge collection well Electronics outside charge collection well Collection node with large fill factor no low field regions, radiation hard Large sensor capacitance (DNW/PW junction!) x-talk, noise & speed (power) penalties Full CMOS with isolation between NW and DNW Very small sensor capacitance low power Less radiation hard (longer drift lengths) Full CMOS with additional deep-p implant H. Krüger, FEE 2016, Krakow 5

factor no radiation CCE after 10 15 n eq /cm 2 5 10 15 n eq /cm 2 15% 99% 75% 25% 75% 100% 93% 67% 10 15 n eq /cm 2

6 read-out node Influence of the Fill Factor on the CCE Electron Velocity Electron after Velocity 1015 n eq /cm 2 NW PW NW PW Track between two pixels MIP MIP fill factor = 15% fill factor = 75% Charge collected within the first 10ns: Fill factor no radiation CCE after n eq /cm n eq /cm 2 15% 99% 75% 25% 75% 100% 93% 67% n eq /cm 2 Simulation parameters: Pixel pitch: 20µm NW - bias: +20V Substrate: 2k Ohm cm, 20µm thick H. Krüger, FEE 2016, Krakow 6

7 Detector Capacitance Small depletion zone large DNW/PW capacitance NW NW P+ PW P+ d C pw DNW C pw NW NW C n d p-sub C sub P+ C n Large Fill Factor collecting node has a double junction: DNW/SUB and DNW/PW Backplane capacitance C sub (DNW to substrate) Depends on depletion depth (substrate resistivity, bias voltage) Inter-pixel capacitance C n Depends on fill factor and p-implant ( p-stop ) geometry DNW to P-well capacitance C pw Depends on electronics circuit area and DNW/PW junction width same as for std. Hybrid Pixels additional capacitance for Active Pixels H. Krüger, FEE 2016, Krakow 7

8 Example of a Doping profile 130nm CMOS technology with DNW, high resistivity substrate junction width U DNW_PW = 20V P+ PW PW PW pw ~ 0.05 Ω cm DNW dnw ~ 0.1 Ω cm P + - PW - DNW P-SUB psub ~ 3k Ω cm ~150µm U bias = 100V Doping profile H. Krüger, FEE 2016, Krakow 8

9 Typical Pixel Capacitance Sensor type Pixel size Pixel capacitance Diamond sensor 250 µm x 50 µm ~22 ff (meas.) Planar pn-sensor 3D-sensor Active CMOS sensor 250 µm x 50 µm ~110 ff (meas.) 125 µm x 33 µm ~70 ff (sim.) 50 µm x 50 µm ~50 ff (sim.) 250 µm x 50 µm ~170 ff (meas.) 50 µm x 50 µm ~100 ff (sim.) 250 µm x 50 µm (w/o fast r/o) ~300 ff (sim.) 250 µm x 50 µm (w/ fast r/o) ~400 ff (sim) 125 µm x 33 µm ~100 ff (sim.) x3 x4 Measurement data from: M. Havránek et al., Measurement of pixel sensor capacitances with sub-femtofarad precision, NIM A 714 (2013) H. Krüger, FEE 2016, Krakow 9

10 Effects of Pixel Capacitance Total input capacitance = planar + PW/DNW-capacitance C f C d = C d + C pw dig. logic Noise C C pw d p-well Time walk ENC thermal τ CSA C d 1 g m 1 C f 1 g m (C d +C f ) Need to increase bias current (g m I d ) to compensate excess capacitance more power Cross-talk: The PW/DNW capacitance C pw couples direct to the CSA input Despite of careful layout and low noise digital circuits, the minimum operational threshold may get affected. Example: dv PW = 1mV, C PW DNW = 100fF crosstalk = 624e H. Krüger, FEE 2016, Krakow 10

11 Going to lower thresholds: Time Walk vs. Threshold will decrease the time walk only if signal charge has a lower bound (i.e. no charge sharing). V thr1 V thr2 has almost no effect on the time walk if signal amplitudes are not limited to a lower end. charge sharing time walk peaking time Note: Increasing depletion width enhances charge sharing (larger aspect ratio of thickness to pitch) V thr1 V thr2 Low energy tail due to charge sharing H. Krüger, FEE 2016, Krakow 11

12 The Competition is on Standard Hybrid Pixels vs Active CMOS Sensor Hybrid Pixels Possibly no reduction of assembly cost: capacitive coupled CMOS sensors (glued instead of bump bonded) still need electrical connections CMOS sensors have higher analog power consumption Physics case for inner layers: improved spatial resolution with sub pixel encoding (still needs to be proven) No strong use case for Active CMOS Sensor Hybrid Pixels for HL-LHC Standard Hybrid Pixels vs Monolithic Pixels Competition only for outer layers (rad. tolerance, pixel size) Challenging task to integrate digital R/O (x-talk, logic density) Huge savings in silicon and assembly costs Challenge accepted H. Krüger, FEE 2016, Krakow 12

5mm Towards a Monolithic Pixel Sensor for ATLAS LF 150 nm CMOS technology, 2kOhm cm p-type bulk CPPM (Marseille), IRFU (Saclay) and UBonn Design based on CMOS demonstrator pixel chip LF-CPIX 5mm

13 5mm Towards a Monolithic Pixel Sensor for ATLAS LF 150 nm CMOS technology, 2kOhm cm p-type bulk CPPM (Marseille), IRFU (Saclay) and UBonn Design based on CMOS demonstrator pixel chip LF-CPIX 5mm CCPD_LF (A/B) Sub. Sep 2014 Fast R/O coupled to FE-I4 33 x 125µm 2 pixels LF-CPIX Demonstrator Sub. March 2016 Fast R/O coupled to FE-I4 50 x 250µm 2 pixels LF-Monopix 01 To be submitted July 2106 CPIX_LF + stand-alone fast R/O H. Krüger, FEE 2016, Krakow 13

14 CCPD_LF bump bonded to FE-I H. Krüger, FEE 2016, Krakow 14

Time walk Some Results from CCPD_LF Fraction of in-time (25ns) hits Low threshold : 79% High threshold : 91% Collected charge [ke ] T. Hirono Signal spectra (3.

15 Time walk Some Results from CCPD_LF Fraction of in-time (25ns) hits Low threshold : 79% High threshold : 91% Collected charge [ke ] T. Hirono Signal spectra (3.2 GeV e - beam) 160µm depletion 110V bias Noise ~150 (100)e - for version A (B, low cap.) Ampout [V] Collected charge [ke ] 25 ns 13.3 ke (Depletion width 160μm) Base line ENC=136e 55 Fe k ENC=149e Ampout [V] H. Krüger, FEE 2016, Krakow 15

16 H. Krüger, FEE 2016, Krakow 16

LF-Monopix Chip floorplan Floor plan is based on LF-CPIX Demonstrator Bottom part stays almost the same: shift registers, bias circuit, analog buffers,

17 LF-Monopix Chip floorplan Floor plan is based on LF-CPIX Demonstrator Bottom part stays almost the same: shift registers, bias circuit, analog buffers, regulator EoC circuit, serializer and LVDS driver located on the top of the chip LF-CPIX (Demonstrator) LF-Monopix H. Krüger, FEE 2016, Krakow 17

18 Injection HV BL TH Inj_EN PreAmp_EN Discr_EN Monitor_EN vddabias LF-CPIX Demonstrator Pixel Electronics LF-CPIX Pixel 4 bit CSA_Monitor Vbias CSA DAC_LSB SF DAC Thres. Tuning HIT buf HIT_Monitor to FE-I4 SR_EN SR_DATA_IN (from previous pixel) CLK D R Shift Reg. D D Inj_EN Monitor_EN PreAmp/Discr_EN 4-bit thres. tuning SR_DATA_OUT (to next pixel) Charge Sensitive Amplifier AC coupled to sensing diode Two variants: NMOS & CMOS input Discriminator 4-bit thres. trimming Hit pulse width charge signal EN 7 bit 7-bit in-pixel latch PreAmp/Discri enable Output monitor enable Injection enable 4 bits threshold trimming Shift register Write config. Data / Read hit data H. Krüger, FEE 2016, Krakow 18

Monopix R/O Logic Token in (from previous pixel) LF-CPIX Pixel Pixel R/O Logic + R/O logic Monopix Pixel HIT EN TE HIT LE S R S R HIT flag D EN LE TE ReadInt LE RAM TE RAM Addr.

19 Monopix R/O Logic Token in (from previous pixel) LF-CPIX Pixel Pixel R/O Logic + R/O logic Monopix Pixel HIT EN TE HIT LE S R S R HIT flag D EN LE TE ReadInt LE RAM TE RAM Addr. ROM ReadInt Column-drain R/O logic (FE-I3 like) 8-bit gray coded ToT (40 MHz) LE RAM: leading edge stamp TE RAM: trailing edge stamp Distribution of column signals (low noise) Token current steering logic Time stamps (LE, TE) differential mode Freeze Token out (to next pixel) HIT LE TE Token out Freeze Read ReadInt Read Time Stamp (8 bit) Column bus (24 bit) H. Krüger, FEE 2016, Krakow 19

20 Low Noise In-pixel R/O Logic: Token Propagation Pixel R/O Logic Token in (from previous pixel) HIT EN TE HIT LE S R S R HIT flag D EN LE TE ReadInt LE RAM TE RAM Addr. ROM ~ 3 μa ~ 200 ff ReadInt Token out (to next pixel) Freeze Time Stamp (8 bit) Token will propagate while pixels are sensitive OR implemented with Current Steering Logic: constant current less noise Token delay along the column depends on bias settings (< 35 ns for ~ 3 μa, filter cap. 200 ff) Read Column bus (24 bit) CMOS CS-CMOS Token in Output of CSA 1000 e injection H. Krüger, FEE 2016, Krakow 20

ROM ReadInt ReadInt Pixel RAM Column End Freeze ReadInt Token out (to next pixel) Read Time Stamp (8 bit) RAM with source follower output Avoids current

21 Low Noise In-pixel R/O Logic: Timestamp R/O Token in (from previous pixel) Pixel R/O Logic LE/TE LE/TE in in HIT EN TE HIT LE S R S R HIT flag D EN LE TE ReadInt LE RAM TE RAM Addr. ROM ReadInt ReadInt Pixel RAM Column End Freeze ReadInt Token out (to next pixel) Read Time Stamp (8 bit) RAM with source follower output Avoids current injection into the PW during high to low transitions SF bias per column data line ~20µA Column data line is pre-charged Sense amplifier at end of column Column bus (24 bit) Vpc Read out Sense amplifier ~ 20 μa 1000e r/w 0 r/w 1 injection out Read Vpc H. Krüger, FEE 2016, Krakow 21

22 Pixel layouts LF-CPIX Demonstrator Full custom R/O logic to minimize digital p-well area Shielding of lines with logic signals LF-Monopix 01 Separated digital & analog substrate R/O Separated digital ground and bulk connection H. Krüger, FEE 2016, Krakow 22

220 μm End of Column R/O Scheme End-of-Column circuit

address 48 current source (20 μa for each) One gray

priority scan at the column level Left-most column has

LVDS driver Output data rate = 160 MHz Off-chip R/O

driver Sense Amplifiers X 24 Serializer Digital FLow

23 220 μm End of Column R/O Scheme End-of-Column circuit 24 sense amplifiers: 16-bit time stamp + 8-bit pixel address 48 current source (20 μa for each) One gray counter at each column end EoC R/O logic => R/O priority scan at the column level Left-most column has the highest priority Digital buffers Serializer and LVDS driver Output data rate = 160 MHz Off-chip R/O controller Layout of one EoC circuit 250 μm LVDS driver Sense Amplifiers X 24 Serializer Digital FLow Gray Counter EoC Logic Digital Buffer H. Krüger, FEE 2016, Krakow 23

24 Other Monolithic Pixel Developments aimed at LHC Upgrades ALPIDE Chip for ALICE ITS upgrade (CERN) COOL (SLAC) H35Demo (KIT, Liverpool, Geneva ) H. Krüger, FEE 2016, Krakow 24

25 ALPIDE Chip for ALICE ITS upgrade In total ~24000 CMOS Pixel Sensors (10 m 2 sensitive area, 12.5 Gpixels) TowerJazz 180 nm Imaging CMOS Process 3nm thin gate oxide, 6 metal layers > 1kWcm p-type epitaxial layer (18 to 30 mm thick) on p-type substrate Not to scale Deep PWELL shielding NWELL allowing PMOS transistors (full CMOS within active area) 2 mm n-well diode, ~100 times smaller than pixel => low capacitance => large S/N Reverse substrate bias to increase the depletion volume around the NWELL collection diode => further reduce capacitance and increase radiation tolerance 3 x 1.5 cm 2 system-ready chip (1024 x 512 pixels) just submitted: PWELL PWELL NWELL Epitaxial Layer P- Substrate P++ Sensitive area 4.12 cm 2, granularity ~28x28 μm 2, spatial resolution 5 μm With 40 nw front-end and /C 80 mv, hit-driven matrix readout and clock gating in the digital periphery, power consumption (mw/cm 2 ): matrix: analog 5.4 digital 0.78, overall inner: 36.9 and outer barrel: 20.2 NWELL DIODE NMOS TRANSISTOR h e e h h e e h PMOS TRANSISTOR DEEP PWELL H. Krüger, FEE 2016, Krakow 25

26 15 mm palpide-3 chip (last prototype) 30 mm Soldering pads Die picture 55 Fe Radioactive source For further results and details: Presentation by T. Kugathasan at this workshop H. Krüger, FEE 2016, Krakow High occupancy event: 200 MeV p at PSI 26

27 H. Krüger, FEE 2016, Krakow 27

28 Digital matrix with on-chip r/o: All digital signal processing done at the end of column I.Peric et al H. Krüger, FEE 2016, Krakow 28

29 Conclusion Since a few years there is a lot of activity (and enthusiasm) in the field of fully depleted CMOS pixel sensors for ATLAS. Active CMOS pixels have a conceptual pitfal: they are less power efficient compared to hybrid pixels. A realistic approach demands now to evaluate were CMOS pixels actually improve things (i.e. which problem do we want to solve?) Hybrid pixels with passive CMOS sensors? cheaper sensor Hybrid pixels with active CMOS sensor? no performance gain unless used for going to higher integration densities (~3D) Monolithic CMOS sensors huge gain in silicon and assembly costs, feasible for outer layers, still very challenging A first prototype of a fully monolithic CMOS Sensor (LF-Monopix 01) currently being developed, to be submitted in July H. Krüger, FEE 2016, Krakow 29

Thank you for your attention Centre de Physique des Particules de Marseille: M. Barbero, P. Breugnon, S. Godiot, J. Liu, P. Pangaud, A. Rozanov, A. Wang IRFU CEA-Saclay Y. Degerli, F. Guilloux, F.

30 Thank you for your attention Centre de Physique des Particules de Marseille: M. Barbero, P. Breugnon, S. Godiot, J. Liu, P. Pangaud, A. Rozanov, A. Wang IRFU CEA-Saclay Y. Degerli, F. Guilloux, F. Orsini, P. Schwemling Karlsruhe Institute of Technology: I. Peric University of Bonn: T. Hemperek, T. Hirono, F. Hügging, H. Krüger, P. Rymaszewski, T. Wang and N. Wermes H. Krüger, FEE 2016, Krakow 30

arxiv: v2 [physics.ins-det] 15 Nov 2017

arxiv: v2 [physics.ins-det] 15 Nov 2017 Development of depleted monolithic pixel sensors in 150 nm CMOS technology for the ATLAS Inner Tracker upgrade arxiv:1711.01233v2 [physics.ins-det] 15 Nov 2017 P. Rymaszewski a, M. Barbero b, S. Bhat b,