Radiation Tolerance of HV-CMOS Sensors
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1 Radiation Tolerance of HV-CMOS Sensors Ivan Perić, Ann-Kathrin Perrevoort, Heiko Augustin, Niklaus Berger, Dirk Wiedner, Michael Deveaux, Alexander Dierlamm, Franz Wagner, Frederic Bompard, Patrick Breugnon, Jean-Claude Clemens, Denis Fougeron, Patrick Pangaud, Alexandre Rozanov, Fuwei Wu, Jian Liu, Malte Backhaus, Fabian Hügging, Hans Krüger, Lingxin Meng, Daniel Münstermann, Maurice Garcia-Sciveres, Christan Kreidl Supported by: Baden Württemberg Stiftung, Helmholtz Alliance, Institute ZITI, University of Heidelberg RESMDD 2012, Firenze, Ivan Peric 1
2 Overview High-voltage CMOS pixel sensors introduction Results of irradiations with neutrons, protons and x-rays RESMDD 2012, Firenze, Ivan Peric
3 High-voltage CMOS pixel detectors or smart diode arrays or HV-MAPS RESMDD 2012, Firenze, Ivan Peric 3
4 The structure RESMDD 2012, Firenze, Ivan Peric 4
5 HV CMOS detectors Monolithic active pixel sensor. Pixel electronics based on CMOS. Implemented in commercial technologies. PMOS and NMOS transistors are placed inside the shallow n- and p-wells. Pixel 1 Pixel 2 Pixel 3 PMOS NMOS Shallow n-well Shallow p-well RESMDD 2012, Firenze, Ivan Peric
6 HV CMOS detectors A deep n-well surrounds the electronics of every pixel. Pixel 1 Pixel 2 Pixel 3 PMOS NMOS deep n-well RESMDD 2012, Firenze, Ivan Peric
7 HV CMOS detectors The deep n-wells isolate the pixel electronics from the p-type substrate. Pixel 1 Pixel 2 Pixel 3 PMOS NMOS deep n-well p-substrate RESMDD 2012, Firenze, Ivan Peric
8 HV CMOS detectors The substrate can be biased low without damaging the transistors. In this way the depletion zones in the volume around the n-wells are formed. => Potential minima for electrons PMOS NMOS deep n-well Potential energy (e-) Depletion zone p-substrate RESMDD 2012, Firenze, Ivan Peric
9 HV CMOS detectors Charge collection occurs by drift. (main part of the signal) PMOS NMOS deep n-well Drift Potential energy (e-) Depletion zone p-substrate RESMDD 2012, Firenze, Ivan Peric
10 HV CMOS detectors Charge collection occurs by drift. (main part of the signal) Additional charge collection by diffusion. PMOS NMOS deep n-well Drift Potential energy (e-) Depletion zone p-substrate Diffusion RESMDD 2012, Firenze, Ivan Peric
11 HV CMOS detectors HVCMOS sensors can be implemented in any CMOS technology that has a deep-n-well surrounding low voltage p-wells. (We have successfully used TSMC 65nm: 2.5 μm pixels.) We expect the best results in high-voltage technologies: These technologies have deeper n-wells and the substrates of higher resistances than the LV CMOS. Smart diode PMOS NMOS deep n-well Potential energy (e-) Depletion zone p-substrate RESMDD 2012, Firenze, Ivan Peric
12 HV CMOS detectors Example AMS 350nm HVCMOS: Typical reverse bias voltage is V and the depleted region depth ~15 m. 20 cm substrate resistance -> acceptor density ~ cm -3. E-field: 100V/15 m or 67 kv/cm or 6.7 V/ m. PMOS NMOS deep n-well Depletion zone 100V ~15µm RESMDD 2012, Firenze, Ivan Peric
13 Radiation tolerance RESMDD 2012, Firenze, Ivan Peric 13
14 Radiation tolerance High-voltage monolithic detectors 0V drift <-60V 15 μm diffusion Tcoll~200ps RESMDD 2012, Firenze, Ivan Peric 14
15 Radiation tolerance High-voltage monolithic detectors drift Rad. damage RESMDD 2012, Firenze, Ivan Peric 15
16 Project results RESMDD 2012, Firenze, Ivan Peric 16
17 Project history 2006 Proof of principle phase 350nm AMS HV technology 1) Simple charge integrating pixels with pulsed reset and rolling shutter RO. (Possible applications: ILC, transmission electron microscopy, etc.) 2) Pixels with complex CMOS-based pixel electronics that detect particle signals. (Possible applications: CLIC, LHC, CBM, etc.) 3) Capacitively coupled pixel detectors (CCPDs) based on a pixel sensor implemented as a smart diode array. First publication: I. Peric, A novel pixelated monolithic particle detector implemented in high-voltage CMOS technology Nucl. Instr. Meth. A 582, (2007) RESMDD 2012, Firenze, Ivan Peric
18 Charge integrating pixel detector 3.3 V Reset V. Out Res Res Sel Sensor diode HVPixelM: 21x21 µm pixel size 128 x 128 pixel matrix RESMDD 2012, Firenze, Ivan Peric
19 Test-beam results: HVPixelM Seed pixel SNR 27, seed signal 1200e, cluster 2000e Efficiency at TB: ~98% (probably due to rolling shutter effects one row out of 64 is in reset state. Spatial resolution 3-3.8µm RESMDD 2012, Firenze, Ivan Peric
20 A pixel with CMOS-based electronics 40 µm RESMDD 2012, Firenze, Ivan Peric
21 A Pixel with CMOS-based electronics Left: Response probability of the entire pixel matrix for 660e test pulse and the noise occupancy. Right: MIP spectrum measured at SPS (CERN). RESMDD 2012, Firenze, Ivan Peric
22 CCPD Pixel Readout chip HVMAPS Signal charge RESMDD 2012, Firenze, Ivan Peric 22
23 Efficiency Edgeless CCPD2 signal and noise Pixel matrix efficiency: Detection of signals > 350e possible MIP signal ~ 1800 e 1.0 Efficiency - window 800ns Signal [e] CAPPIX/CAPSENSE edgeless CCPD 50x50 µm pixel size Noise 30-40e Time resolution 300ns MIP SNR RESMDD 2012, Firenze, Ivan Peric
24 New projects 65nm UMCLV technology 2006 Proof of principle phase 350nm AMS HV technology A 180nm HV technology Applications: 1) ATLAS and CLIC Smart sensors readout by pixel- and strip readout chips. 2) Mu3e experiment at PSI Monolithic pixel detector 3) Transmission electron microscopy integrating pixels with pulsed reset and rolling shutter RO in-pixel CDS RESMDD 2012, Firenze, Ivan Peric
25 Irradiations RESMDD 2012, Firenze, Ivan Peric 25
26 Neutron irradiation at the research-reactor in Munich n eq /cm 2 RESMDD 2012, Firenze, Ivan Peric 26
27 Irradiated device: HVPixelM 3.3 V Reset V. Out Res Res Sel Sensor diode HVPixelM: 21x21 µm pixel size RESMDD 2012, Firenze, Ivan Peric
28 Signal [e] Number of hits Irradiation with neutrons Increase of the detector leakage current from 350fA (room T) to 130pA (0C) per pixel => 30 μa / cm 2 at 0C Seed pixel signal decrease from 1300e to 1000e. The measurement has been performed at 0C. Not irradiated Irradiated Co Irradiated chip (10 14 n eq ) Not irradiated MSP 2 MSP 3 MSP 4 MSP 5 MSP 6 MSP Number of pixels in cluster Signal [e] RESMDD 2012, Firenze, Ivan Peric 28
29 Proton irradiation at KIT (Karlsruhe) n eq /cm 2 RESMDD 2012, Firenze, Ivan Peric 29
30 Irradiated device: CCPD2 Readout chip Digital part A A Sensor CAPPIX/CAPSENSE edgeless CCPD 50x50 µm pixel size RESMDD 2012, Firenze, Ivan Peric
31 ~number of signals ~number of signals ~ number of signals ~number of signals Irradiation with protons at KIT (10 15 n eq /cm 2 ) 55 Fe spectrum and RMS noise Not irradiated Room temperature 1.0 RMS Noise 12 e 0.8 RMS Noise 0.5mv (12e) 55 Fe 70mV (1660e) Room temperature 55 Fe 55 Fe spectrum and RMS noise Irradiated 20C 1.0 RMS Noise 270 e 0.8 RMS Noise, 13mv (270e) 55 Fe, 80mV (1660e) Temperature 20C Irradiated with protons to n eq 55 Fe peak Base line noise (RMS) Noise peak Fe spectrum, RMS noise Irradiated 10C RMS Noise 77 e signal amplitude [V] RMS Noise, 2.8mv (77e) 55 Fe, 60mV (1660e) Temperature 10C Irradiated with protons to n eq 0.0 Base line noise (RMS) signal amplitude [V] RMS Noise, 2.4mv (40e) 55 Fe, 100mV (1660e) Temperature -10C Irradiated with protons to n eq 55 Fe spectrum, RMS noise Irradiated -10C RMS Noise 40 e signal amplitude [V] signal amplitude [V] RESMDD 2012, Firenze, Ivan Peric 31
32 ~number of signals ~number of signals ~number of signals Irradiation with protons at KIT (10 15 n eq /cm 2 ) 55 Fe RMS Noise, 13mv (270e) 55 Fe, 80mV (1660e) 55 Na, 200mV (4150e) Temperature 20C Irradiated with protons to n eq RMS Noise, 2.8mv (77e) 55 Fe, 60mV (1660e) 55 Na, 180mV (4980e) Temperature 10C Irradiated with protons to n eq Na Fe and 22 Na spectrum, RMS noise Irradiated Temperature 10C RMS Noise 77 e SNR = signal amplitude [V] signal amplitude [V] 55 Fe and 22 Na spectrum, RMS noise Irradiated Temperature 20C RMS Noise 270 e SNR = RMS Noise, 2.4mv (40e) 55 Fe, 100mV (1660e) 55 Na, 220mV (3750e) Temperature -10C Irradiated with protons to n eq Fe and 22 Na spectrum, RMS noise Irradiated Temperature -10C RMS Noise 40 e SNR = signal amplitude [V] RESMDD 2012, Firenze, Ivan Peric 32
33 ~number of signals Irradiation with protons at KIT (10 15 n eq /cm 2 ) Na - 0V bias (0.075V or 1250e) 22 Na - 30V bias (0.18V or 3125e) 22 Na - 60V bias (0.22V or 3750e) 55 Fe - 60V bias (100mV or 1660e) RMS Noise (2.4mV or 40e) Temperature: - 10C Irradiated with protons to n eq V -30V -60V Na Fe signal amplitude [V] RESMDD 2012, Firenze, Ivan Peric 33
34 X-Ray irradiation at KIT 50 MRad RESMDD 2012, Firenze, Ivan Peric 34
35 Irradiated device: CCPD1 Monolithic matrix CCPD matrix (sensor) Electrodes CCPD matrix (readout) RESMDD 2012, Firenze, Ivan Peric 35
36 noise [e] response probability response probablility Irradiation with x-rays (50 MRad) Noise Before irradiation Room Temperature Noise 72e Response probability fit: sgma = 72e, mean = 750e Not irradiated Room temperature Noise After irradiation Temperature 5C Noise 83e Response probability fit: sgma = 83e, mean = 610e Irradiated with x-rays to 60MRad Temperature 5C signal amplitude [e] signal amplitude [e] Noise Room temperature annealiing day 0: irradiation with x-rays to 60MRad day 5: 24 hours at 80C Noise at room Temperature Vs. annealing time annealing time [days] RESMDD 2012, Firenze, Ivan Peric 36
37 Irradiation at PS (CERN) RESMDD 2012, Firenze, Ivan Peric 37
38 4.4mm Irradiated device: HV2FEI4 Pixel matrix: 60x24 pixels (readout by 20 x 12 FEI4 pixels) Pixel size 33 m x 125 m. IO pads for strip operation Pixel matrix Strip pads IO pads for CCPD operation RESMDD 2012, Firenze, Ivan Peric 38
39 HV2FEI4: CCPD readout FEI4 Pixels Signal transmitted capacitively CCPD Pixels 2 2 Bias A 3 3 Bias B 1 1 Bias C + RESMDD 2012, Firenze, Ivan Peric 39
40 HV2FEI4: strip-like readout Pad Pad RESMDD 2012, Firenze, Ivan Peric 40
41 Pixel electronics - layout NMOS NMOS PMOS B B FB FB FB Ld FB FB Ld N Ld C P-well BLR ThR P+ ring N-well P+ ring N-well RESMDD 2012, Firenze, Ivan Peric
42 Pixel electronics FB <1nA Amplifier Output 500nA Monitor Output High pass Sensor bias 100fF Amplifier <5 μa <1 μa Low pass Comparator ~ μa ~ μa RESMDD 2012, Firenze, Ivan Peric 42
43 6 pixels layout Tune DAC Comparator Amplifier 33 µm RESMDD 2012, Firenze, Ivan Peric
44 Irradiation at PS (CERN) Transparency: Patrick Breugnon RS232 The system allows the configuration of HVCMOS chip and the readout when the chip is in the beam using the Amplifier Output and Monitor signal. LVDS 20m long cable 4 signals io 3,3V Lvds 1,8V 5m 4 signals The Monitor and AmpOut signals are read-back and amplified through an analog amplifier DE2 board Output signal 20m long cable 0,4V max HV2FEI4 VDDA VSSA Threshold Gate HV RESMDD 2012, Firenze, Ivan Peric
45 Irradiation at PS (CERN) RESMDD 2012, Firenze, Ivan Peric 45
![Output voltage [V] Results after 380 MRad and ~ 8 x 10 15 n eq /cm 2 The chip works, particles are measured when the chip is in the beam: Output of the](/docs-images/84/91041479/images/46-0.jpg "amplifier 1,8 1,6 1,4 1,2 1,0 0,8 Comparator characteristics.")
46 Output voltage [V] Results after 380 MRad and ~ 8 x n eq /cm 2 The chip works, particles are measured when the chip is in the beam: Output of the amplifier 1,8 1,6 1,4 1,2 1,0 0,8 Comparator characteristics. 0,39 0,40 0,41 0,42 0,43 0,44 0,45 0,46 0,47 0,48 Input voltage [V] RESMDD 2012, Firenze, Ivan Peric
47 Current HV [ua] AmpOut rate [part/spill] Results after 144 MRad Rate vs. HV HV [Volts] The rate of detected particles depends on the high voltage bias. T: Superposition of two effects: Positive effect: The increase of HV bias leads to an increase of the depleted region depth => better detection efficiency. Negative effect: The increase of the leakage current leads to a signal loss Leakage current vs. HV HV [Volts] Measured HV (leakage) current dependence on the high voltage bias. T: Leakage current depends on the volume of the depleted region. Linear size of the depleted layer depends as square root of the bias voltage but The cylindrical depleted layer volume depends linearly on bias voltage. RESMDD 2012, Firenze, Ivan Peric 47
48 RESMDD 2012, Firenze, Ivan Peric Decrease of counting rate
49 Charge multiplication effect RESMDD 2012, Firenze, Ivan Peric 49
50 Test device: Mu3e test-chip 39 m 1.8mm 42x36 pixels 30 m Analog pixels Digital channels Analog pixel layout 0.7 m 2 metal layers Pixel size 39x30 micrometers. Separated digital and analog block. Signal amplitude can be measured as ToT. RESMDD 2012, Firenze, Ivan Peric 50
51 LED measurement LED light pulses have been detected. Signal amplitude has been measured as the time over threshold. From 60V reverse bias, the time over threshold increases exponentially. (about 2x increase) 11 Time over threshold [μs] 10 9 Charge multiplication! Reverse bias [V] RESMDD 2012, Firenze, Ivan Peric 51
52 Conclusions HVCMOS is an active pixel technology with the charge collection based on drift. Thanks to the use of commercial processes, the production of relatively low-cost (1.5 k /12 wafer), large area detectors is possible. We have irradiated test HVCMOS sensors wit neutrons (10 14 n eq ) (Munich), protons (10 15 n eq and 8 x n eq MRad) (KIT and PS), and x-rays (50MRad) (KIT). Two main effects are observed: 1) Reduction of the secondary signal part that is collected by diffusion. 2) Increase of leakage current. Good SNR can be achieved after irradiation if the sensors are cooled to ~ 0C. Charge multiplication factor can further increase SNR. Although we still do not understand all effects, the HVCMOS sensors seem to have a high radiation tolerance. RESMDD 2012, Firenze, Ivan Peric 52
53 Thank you RESMDD 2012, Firenze, Ivan Peric 53
54 Backup Slides RESMDD 2012, Firenze, Ivan Peric 54
55 RESMDD 2012, Firenze, Ivan Peric Decrease of counting rate
56 ~Number of hits ~signal probability ~number of signals Irradiation with x-rays (50 MRad) 1.0 Not irradiated (room T) Irradiated with x-rays to 60MRad (5C) Fe irradiated with x-rays to 60MRad Temeperature 5C Na spectrum signal duraion [clock periodes] signal duration [clock periodes] 22 Fe spectrum Na beta signal Irradiated with x-rays to 60MRad Temperature 5C Na spectrum Singnal/e RESMDD 2012, Firenze, Ivan Peric 56
57 Signal-generation and amplification RESMDD 2012, Firenze, Ivan Peric 57
58 HV CMOS detectors Particle hit N-well e-h RESMDD 2012, Firenze, Ivan Peric
59 HV CMOS detectors Charge collection Assume: V sat = 8 x 10 4 m/s T col = 188 ps e- 188 ps RESMDD 2012, Firenze, Ivan Peric
60 HV CMOS detectors Voltage drop in the n-well Q/Cdet Cdet Q 188 ps RESMDD 2012, Firenze, Ivan Peric
61 HV CMOS detectors Amplification Q/Cdet Cdet Q 188 ps 50ns RESMDD 2012, Firenze, Ivan Peric
62 HV CMOS detectors Feedback action through Cf N-well potential temporary restored Meta-stabile state Q/Cf Q Q Cf Cdet 188 ps 50ns RESMDD 2012, Firenze, Ivan Peric
63 HV CMOS detectors Reset of the charge sensitive amplifier Q/Cf Q Q Cf Cdet 188 ps 50ns RESMDD 2012, Firenze, Ivan Peric
64 HV CMOS detectors Reset of the charge sensitive amplifier accomplished: N-well again negative! Assumption: Cc= Cdet Q Cc ~Q/Cdet Cdet Q 188 ps 50ns 500ns RESMDD 2012, Firenze, Ivan Peric
65 HV CMOS detectors Initial voltage across the n-well and the coupling capacitance restored by R bias Rbias 188 ps 50ns 500ns >>500ns RESMDD 2012, Firenze, Ivan Peric
66 Temperature [C] Current HV [ua] Results after 144 MRad Leakage current vs. power (HV=30V) Power [mw] 60% increase from 22 to 72 mw Measured HV current dependence on the analog power. T: Increase of the analog power leads to a temperature increase. The temperature increase leads to the diode leakage increase Temperature vs. power 2.8 degrees difference from 22 to 72 mw Power [mw] Measured temperature dependence on the analog power. Check: About 2.8 degrees temperature increase leads to 60% leakage increase, RESMDD 2012, Firenze, Ivan Peric 66
67 HV CMOS detectors Collected charge causes a voltage change in the n-well. This signal is sensed by the amplifier placed in the n-well. P-substrate PMOS NMOS G S D electrons holes N-well P-well RESMDD 2012, Firenze, Ivan Peric
68 HV CMOS detectors Collected charge causes a voltage change in the n-well. This signal is sensed by the amplifier placed in the n-well. P-substrate RESMDD 2012, Firenze, Ivan Peric
69 HV CMOS detectors Collected charge causes a voltage change in the n-well. This signal is sensed by the amplifier placed in the n-well. P-substrate RESMDD 2012, Firenze, Ivan Peric
70 Experimental results - overview Capacitive coupled hybrid detector CCPD2 -capacitive coupled pixel detector Pixel size 50x50μm Noise 30-40e Time resolution 300ns MIP SNR Irradiations of test pixels 60MRad MIP SNR 22 at 10C (CCPD1) n eq MIP SNR 50 at 10C (CCPD2) HV2FEI4 chip CCPD for ATLAS pixel detector Readout with FEI4 chip Reduced pixel size: 33x125μm RO type: capacitive and strip like Noise: ~80e (stand alone test, preliminary) HVPixel1 CMOS in-pixel electronics with hit detection Binary RO Pixel size 55x55μm Noise 60e MIP seed pixel signal 1800 e Time resolution 200ns Monolithic detector continuous readout with time measurement MuPixel Monolithic pixel sensor for Mu3e experiment at PSI Charge sensitive amplifier in pixels Hit detection, zero suppression and time measurement at chip periphery Pixel size: 39x30 μm (test chip) (80 x 80 μm required later) MIP seed signal 1500e (expected) Noise: ~40 e (measured) Time resolution < 40ns Power consumption 7.5µW/pixel Monolithic detector - frame readout PM2 chip - frame mode readout Pixel size 21x21μm 4 PMOS pixel electronics 128 on-chip ADCs Noise: 21e (lab) - 44e (test beam) MIP signal - cluster: 2000e/seed: 1200e Test beam: Detection efficiency >98% Seed Pixel SNR ~ 27 Cluster signal/seed pixel noise ~ 47 Spatial resolution ~ 3 m HPixel - frame mode readout In-pixel CMOS electronics with CDS 128 on-chip ADCs Pixel size 25x25 μm Noise:60-100e (preliminary) MIP signal - cluster: 2100e/seed: 1000e (expected) SDS - frame mode readout 1. Technology 350nm HV substrate 20 cm uniform Pixel size 2.5x2.5 μm 4 PMOS electronics 2. Technology 180nm HV substrate 10 cm uniform Noise: 20e (preliminary) MIP signal (~1000e - estimation) 3. Technology 65nm LV substrate 10 cm/10 m epi RESMDD 2012, Firenze, Ivan Peric 70
71 Mu3e detector Proposed: four layers of pixels ~ 80x80 m 2 size HV CMOS monolithic detectors Time stamping with < 100ns resolution required to reduce the number of tracks in an image. Sensors should be thinned to ~50 m Triggerless readout Power ~ 200mW/cm 2 cooling with helium Total area: 1.9 m M pixels 100 wafers (if 100% yield) B=1T Recurl pixel layers Outer pixel layers 3744cm cm 2 Scintillator tiles µ+ Inner pixel layers Scintillating fibres 360cm 2 Al target RESMDD 2012, Firenze, Ivan Peric
72 RESMDD 2012, Firenze, Ivan Peric HV CMOS detectors
73 Integrating pixels with CDS Correlated double-sampling (CDS) is implemented in the pixels using CMOS electronics. The pixel output signals are digitized by 128 on-chip ADCs. The readout electronic has been optimized for a fast readout and a low power consumption. 25 µm VP VP Res Res Sel Sample Sel Sel Out RESMDD 2012, Firenze, Ivan Peric 73
74 A pixel with CMOS-based electronics 40 µm RESMDD 2012, Firenze, Ivan Peric
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