ISIS2 as a Pixel Sensor for ILC

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1 ISIS2 as a Pixel Sensor for ILC Yiming Li (University of Oxford) on behalf of UK ISIS Collaboration (U. Oxford, RAL, Open University) LCWS 10 Beijing, 28th March / 24

2 Content Introduction to ISIS Motivation & Application History ISIS2 Design ISIS2 Test Results Test Structure Main Array Future Conclusion 2 / 24

3 ILC Vertexing Requirements: 3 µm resolution 0.1 X 0 % per layer! Huge background Occupancy < 1% Time slicing Two solutions offered by LCFI Fast readout: CPCCD Charge Storage: ISIS ISIS advantage No need for power cycle, reduced peak power Storage of raw charge Figure: Simulation of e + e pair production at ILC Figure: ILC bunch train 3 / 24

4 CCD and Charge-Coupled CMOS Charge Coupled Device (CCD) Charge is stored inside the pixels Small pixel size high resolution ISIS is produced with CMOS process while uses CCD structures to store signals for multiple time-slices 4 / 24

5 In-situ Storage Image Sensor Charge is collected under photogate Charge is transferred into 20 in-situ storage pixels During the quiet time between bunch trains the charge is converted to voltage and read out 5 / 24

Possible Application Beyond ILC Vertexing Buried Channel in CMOS process is of interest in general Decouples charge storage and charge-to-voltage conversion low noise & CDS Efficient charge

closed cylinders (incl endcaps), 50µm square pixels 0.6%X 0 per layer, 3.

6 Possible Application Beyond ILC Vertexing Buried Channel in CMOS process is of interest in general Decouples charge storage and charge-to-voltage conversion low noise & CDS Efficient charge collection from large area LC Tracking Silicon Pixel Tracker (SPT) Barrel: SiC foam ladders, linked mechanically to one another along their length (Low-Mass Collaboration UK) Tracking layers: 5 closed cylinders (incl endcaps), 50µm square pixels 0.6%X 0 per layer, 3.0%X 0 total, over full polar angle range, plus < 1%X 0 from VXD Timing layers: one (double) as an envelope for general track finding, and one between VXD and tracker, to tag large angle loopers, 150µm square pixels Amenable to the fast-growing charge-coupled CMOS pixel technology C architecture offering large area coverage at minimal thickness and cost, due to simplicity of the monolithic process Figure: SPT at ILC/CLIC suggested layout (Chris Damerell) 6 / 24

7 ISIS History Fast framing CCD cameras based on ISIS principle has been developed (G. Etoh et al) - Max frame rate 100 Megaframes/s! ISIS for ILC development started in LCFI end 2003 ISIS1 was produced and successfully tested to prove the feasibility of local charge storage ISIS2 was received after the termination of LCFI but the testing has been going on nonetheless. 7 / 24

Proof-of-principle Device: ISIS1 e2v CCD 2µm process 160 40µm 2 pixel, 5 storage cells successfully tested with 55 Fe and testbeam Z.

8 Proof-of-principle Device: ISIS1 e2v CCD 2µm process µm 2 pixel, 5 storage cells successfully tested with 55 Fe and testbeam Z. Zhang et al. NIM A 607(2009)538 D. Cussans et al. NIM A 604(2009)393 J. J. Velthius et al. NIM A 599(2009)161 Figure: Three pixels on ISIS1 8 / 24

2008 CCD buried channel in a CMOS process!

9 ISIS2 Design ISIS2 received from Jazz Semiconductor in Oct CCD buried channel in a CMOS process! µm CMOS process µm 2 storage pixel (ISIS1: µm 2 ) 9 / 24

10 Introduction to ISIS ISIS2 Design ISIS2 Test Result Future Summary ISIS2 Pixels Layout Figure: ISIS2 pixels under microscope Figure: ISIS2 pixel layout. (K. Stefanov, P. Murray) 10 / 24

11 ISIS2 Variations Reset transistor - Surface Channel - Buried Channel Deep p + well - With/w.o. aperture under PG - Size of aperture Pixel variations - CCD gate width - CCD intergate gap Process options: doping concentration Figure: Upper: Surface Channel reset transistor; Lower: Buried Channel reset transistor. (K. Stefanov) 11 / 24

Test Structure Same as full array but without CCD transfer gates Allows to establish operating conditions Small feature size - Small capacitance of

12 Test Structure Same as full array but without CCD transfer gates Allows to establish operating conditions Small feature size - Small capacitance of output node excellent noise performance - Edge effects and 3D fringe fields are important Figure: ISIS2 test structure. (K. Stefanov, P. Murray) 12 / 24

13 Fringe Effects C. Damerell, Z. Zhang Potential under the output gate is pulled up by output node at 5 V Charge leaking to output node directly from photo gate 13 / 24

14 Slow Readout Rate Processing/design flaw: Large resistance of polysilicon gates It takes a few ms per transfer (between gates) Large dark current accumulated Low temperature: dark current, gate resistance Bright side: charge lives in CCD for seconds can be manipulated 14 / 24

X-ray Calibration Calibration with 55 Fe (1620 e K α and 1780 e K β lines) - direct hits on output node - hits from photo gate CTE and Noise Measured - Sensitivity 24 µv e

15 X-ray Calibration Calibration with 55 Fe (1620 e K α and 1780 e K β lines) - direct hits on output node - hits from photo gate CTE and Noise Measured - Sensitivity 24 µv e - Best noise 6 e - 5% loss of CTE due to tapered geometry -10 C 31 C CTE 94.2% 94.5% OD Noise 20 e 14 e PG Noise 27 e 66 e Figure: 55 Fe hits on output node at 31 C 15 / 24

16 Charge Transfer Charge transferred from: dark current, LED or charge injection Well capacity is limited by Summing Gate e depending on SG bias 16 / 24

17 Full Array First successful charge transfer in main array in July 2009! 17 / 24

18 Deep p + Splits No deep p + shield (YELLOW) Deep p + with aperture (GREEN) Deep p + with wider aperture (PURPLE) Deep p + without aperture (PINK) 18 / 24

19 Readout Time Minimization Efforts to minimizing the readout time: (left)sequence of the transfers ( excluding SG) is squashed, eg. The time between transfer gates are decreased (right)trying to run at highest frequency 19 / 24

20 Charge Transfer Efficiency (1) 3 phase CCD charge can be transferred in both directions CTE is measured by comparing Case 1 and Case 2 CTE 99% limited by temperature instability 20 / 24

21 Charge Transfer Efficiency (2) CTE is also measured by comparing the charge from each individual storage cell. Final charge S N = S 0 (1 CTI ) N S 0(1 N CTI ) Two different method to achieve hits on individual cell: by moving the source (Z. Zhang) CTE 99.3% with an optical shutter (H. Wilding, Y. Li) CTE 98.4% Two numbers are measured using different sensor splits from different wafers, yet still very similar 21 / 24

22 Full Array Readout 128 rows 32 columns 32 columns serialized into 4 outputs Rolling shutter readout Logic bug - cannot single out one row for pixel-level correlated double sampling 22 / 24

23 Future Design bugs of ISIS2 to be fixed buried channel reset transistor resistive polysilicon gate logic of rolling shutter ISIS3: larger sensor with more compact pixel geometry and data serialization. 23 / 24

24 Summary ISIS Approach has its advantage for ILC vertexing and beyond ISIS2 successfully demonstrated feasibility of multiple charge storage and transfer in CMOS process A few defects in ISIS2 design/manufacture, but well understood and easy to fix in future iteration 24 / 24

Low Power Sensor Concepts

Low Power Sensor Concepts Konstantin Stefanov 11 February 2015 Introduction The Silicon Pixel Tracker (SPT): The main driver is low detector mass Low mass is enabled by low detector power Benefits the