Perspectives of 65nm CMOS technologies for high performance front-end electronics in future applications

Transcription

1 Perspectives of 65nm CMOS technologies for high performance front-end electronics in future applications G. Traversia, L. Gaionia, M. Manghisonia, L. Rattib, V. Rea auniversità degli Studi di Bergamo and INFN Pavia buniversità degli Studi di Pavia and INFN Pavia 21th International Workshop on Vertex Detectors, September, 2012, Jeju, Korea

2 Motivations Pixelated detectors in cutting-edge scientific experiments at high luminosity particle accelerators and advanced X-ray sources will need to fulfill very stringent requirements on pixel pitch, material budget, readout speed and radiation tolerance Designers are currently considering two different approaches: moving to higher density 2D technology nodes moving to technologies with vertical integration techniques (3D-IC) The 65nm is starting to be considered as a new attractive solution in view of the development of high-density, high-performance, mixed-signal readout circuits In the nanometer range, the impact of new dielectric materials and processing techniques (e.g.: silicon strain, gate oxide nitridation) on the analog behavior of MOSFETs has to be carefully evaluated 2

3 65 nm process options Several variants of the 65nm process technology are available High Speed: highest possible speed at the price o f v e r y h i g h l e a k a g e c u r r e n t ( f o r microprocessors, fast DSP, ). Lower operation voltage (Vdd=1V), low threshold voltage devices General Purpose: speed is not critical -> leakage current one order of magnitude lower than HS Low Power (or Low Leakage): thicker gate oxide thickness, Vdd=1.2V, higher threshold voltage devices (for low power applications) Low (-50%) Moderate (0%) Fast (+50%) The characterization results of the 65nm technology shown in this talk are referred to a Low Power option (compared with 90nm LP, 90nm GP and 130nm GP from different foundries) SEE and TID. Radiation Test Results on ST Circuits in 65nm CMOS Technologies, Final Presentation of ESTEC Contract No /04/NL/AG, COO-3. January

4 Outline Analog performance of MOS transistors in 65nm technology Intrinsic gain Gate leakage current Noise performance Radiation hardness Prototype chip with mixed-signal readout circuits in 65nm CMOS Features of the designed structures Experimental results Collaborative activities under the AIDA WP3.3 Proposed IP blocks 4

5 Intrinsic gain in different CMOS nodes The intrinsic gain is the maximum gain obtainable from a single transistor Intrinsic Gain nm Foundry B 90 nm Foundry B 65 nm Foundry A As-drawn Gate Length [µm] NMOS V DS =1.0 V IC 0 =10 Gain = g m Intrinsic αl g ds g m channel transconductance g ds output conductance α scaling factor (for constant field scaling) devices are biased at the same inversion level expressed by the inversion coefficient I C 0 = I D I Z * W L where I Z * is the characteristic normalized drain current Keeping the intrinsic gain constant with scaling is considered one of the major challenges in the design of analog circuits in scaled down technologies The intrinsic gain: is proportional to the channel length is maintained across technology nodes (L min scales by the same factor α) 5

6 Intrinsic gain in 65nm node 1000 Weak Moderate Strong L=700 nm L=500 nm As a function of the inversion coefficient: Intrinsic Gain 100 L=350 nm L=200 nm L=130 nm L=100 nm The intrinsic gain is maximum in weak inversion where it is independent of the drain current It decreases with the drain current in strong inversion (increases with L but with different slopes for short and long L) L=65 nm Inversion Coefficient DIBL effects dominate on g ds 65 nm node IC0=0.1 As a function of the gate length: The intrinsic gain is proportional to the channel length for L close to Lmin (DIBL dominates on g ds ) Intrinsic Gain Weak Moderate Strong IC0=1 IC0=10 It shows a reduced slope for L>5L min (CLM effects dominates on g ds ) 50 CLM effects dominate on g ds As-drawn Gate Length [µm] The intrinsic gain is larger in weak inversion for long channel devices and is lower in strong inversion for short channel devices 6

7 Gate leakage current The gate current density is used to evaluate the impact of the gate oxide thickness reduction on the static power consumption J G is the I G /WL measured at V DS =0 I G is due to discrete charge randomly crossing a potential barrier Gate Current Density [A/cm 2 ] A/cm 2 Foundry B GP devices NMOS A PMOS A NMOS B V GS =1.0 PMOS V B V DS =V BS =0 Foundry A LP devices Technology Node [nm] Oxynitride gate allows to reduce tunneling effects The gate current changes between 90nm processes from two different foundries 65nm MOSFETs are in the same region of current density values of 90nm Foundry A and 130nm Foundry B devices This region is well below the commonly used limit of 1 A/cm 2 CMOS scaling beyond 100nm does not necessarily lead to very leaky devices 7

8 Noise in MOS transistors Noise in the drain current of a MOSFET can be represented through an equivalent noise voltage source in series with the device gate S W - white noise channel thermal noise (main contribution in the considered operating conditions) G D S k B Boltzmann s constant T absolute temperature Γ channel thermal noise coefficient contributions from parasitic resistances S 1/f - 1/f noise technology dependent contribution k f 1/f noise parameter α f 1/f noise slope-related coefficient White and 1/f noise have been measured on test devices with different geometries and biased at different drain currents 8

9 White noise Evaluated in terms of the equivalent channel thermal noise resistance: α w excess noise coefficient n proportional to the reciprocal of the slope of I D (V GS ) in subthreshold γ channel thermal noise coeff. a w close to unity for NMOS and PMOS with L > 65 nm no sizeable short channel effects in the considered operating regions (except for 65 nm devices with a w 1.3 ) Negligible contributions from parasitic resistances 9

10 Noise in different CMOS nodes NMOSFETs belonging to different CMOS nodes, with the minimum L allowed by each process The oxide thickness t OX and the minimum L scale with the same coefficient, the NMOSFETs feature approximately the same value of the gate capacitance C G =WLC OX Devices exhibit a similar 1/f noise => the values of the k f parameter changes little across different CMOS generations White noise: devices are biased close to weak inversion => white noise is not sizably affected by L and CMOS node variations even at minimum gate length, as it appears in the high frequency portion of the spectra 10

11 Ionizing radiation effects in sub-100 nm CMOS The oxide thickness reduction and the substrate doping increase, due to the device scaling in CMOS technologies, improve the radiation hardness of deep submicron MOS transistors. The main degradation effects of devices exposed to ionizing radiation, are associated to the thick lateral isolation oxides (STI = Shallow Trench Isolation) Radiation induced positive charge is removed from the gate oxide by tunneling (which also prevents the formation of interface states) Isolation oxides remain thick (order of 100nm) also in nanoscale CMOS, and they are radiation soft Radiation-induced positive charge trapped in isolation oxides may invert a P-type region in the well/substrate of NMOSFETs creating a leakage path between source and drain In an interdigitated device this can be modeled considering that two lateral transistors for each finger are turned on The effect of these parasitic devices on the noise and static characteristic must be carefully evaluated 11

12 Ionizing radiation effects Drain Current[A] NMOS W/L = 1000/0.13 V DS =0.6V 130 nm 65 nm total ID after irradiation ID before irradiation ID,lat total ID after irradiation ID before irradiation ID,lat 10 Mrad Gate-to-Source Voltage [V] Noise Voltage Spectrum [nv/hz 1/2 ] nm NMOS W/L=1000/0.13 and 130 nm NMOS W/L=1000/0.35 Id=100 Vds=0.6 V 65 nm, before irradiation 65 nm, 10 Mrad 130 nm, before irradiation nm, 10 Mrad Frequency [Hz] A large amount of lateral leakage takes places in 130nm devices The smaller ID,lat of 65nm devices suggests that the sensitivity to positive charge buildup in STI oxides is mitigated by the higher doping of the P- type body with respect to less scaled technology Noise voltage spectra in the low frequency region are very similar before irradiation (similar gate capacitance) 1/f noise increase in the 130 nm device is significantly larger than in the 65 nm one 12

13 Noise in NMOSFETs Noise Voltage Spectrum [nv/hz 1/2 ] NMOS 65 nm Id=50 µa, Vds=0.6 V Frequency [Hz] before irradiation 5 Mrad Noise Voltage Spectrum [nv/hz 1/2 ] NMOS 65 nm Id=500 µa, Vds=0.6 V before irradiation 5 Mrad Frequency [Hz] No increase in the white noise region is detected At higher currents the degradation is barely detectable because the impact of the parasitic lateral devices on the overall drain current is negligible PMOSFETs (not shown) do not feature any significant change in their static and noise properties after irradiation, following the trend of the most recent CMOS nodes 13

14 Some remarks on the 65nm node According to the study of key analog parameters, low-noise analog design in the 65nm CMOS node is viable Intrinsic gain is not degraded by scaling Gate leakage current is well below the limit of 1 A/cm 2 Channel thermal noise behavior is consistent with equations valid in weak and moderate inversion Flicker noise comparison with previous CMOS nodes shows that scaling to the 65nm process does not affect 1/f noise performance significantly The comparison with data from previous generations confirms the high degree of radiation tolerance to ionizing radiation that appears to be typical of sub-100 nm technologies Data analysis does not point out any novel damage mechanisms which could be related to the technological advances associated to an aggressively scaled process We designed a prototype chip with mixed-signal readout circuits in the 65nm IBM CMOS process 14

15 Apsel65: deep n-well monolithic active pixel sensor Classical signal processing chain for capacitive detectors The analog processor includes a charge sensitive amplifier, a shaping stage and a threshold discriminator binary readout 15

16 Chip description Chi Standalone channels C inj = 30fF Detector simulating cap. C D =250fF (CH1) C D =350fF (CH2) C D =450fF (CH3) DNW sensor not connected M1 3x3 matrix 40 µm pixel pitch all analog outputs accessible C inj = 30fF for central pixel 360 µm 2 DNW electrode area M2 8x8 matrix 40 µm pixel pitch Row by row, 8-parallel digital readout 360 µm 2 DNW electrode area FCi FFE channels C inj = 10fF Detector simulating cap. C D =50fF (FC1) C D =100fF (FC2) C D =150fF (FC3) 16

17 Apsel65: measurements Measured ENC in good agreement with the simulated values Recovery time increases linearly with the signal amplitude (C2 discharged by a constant current source) Charge sensitivity has an average value of 760 mv/fc (725 mv/fc simulated) Signal amplitude distribution for X- rays from an 55 Fe source (courtesy of S.Bettarini - INFN PI) Charge collected by the central pixel as a function of the laser position Signal magnitude (normalized with respect to V pk ) is plotted in the z (colour) axis for each position of the laser spot 5 µm step in X and Y (1064nm wavelength) The layout of the DNW and n-well layers has been superimposed (exact position unknown) σ xy of the laser 3 µm The main purpose of this measurement is to show the relative charge collection versus position (the amount of charge that is deposited has not been calibrated) L. Gaioni, M. Manghisoni, L. Ratti, V. Re, G. Traversi, A 65 nm CMOS prototype chip with monolithic pixel sensors and fast front-end electronics, accepted for publication on IEEE Trans. on Nucl. Sci.. 17

18 Fast front-end for high resistivity pixels W/L PA input device: 27/0.25 Power consumption: 6 µw ENC = 204 e C D = 100 ff (measured: 214 e - ) Simulated charge sensitivity: 42 mv/fc (measured: 37 mv/fc) Peaking time: ~ 25 ns (measured about 25 ns) Integral non linearity: ~ 3.5 % (32 ke - input dynamic range) 18

19 AIDA (Advanced european Infrastructures for Detectors at Accelerators) The AIDA project addresses infrastructures required for detector development for future particle physics experiments The infrastructures covered by the AIDA project are key facilities required for an efficient development of the future experiments, such as: test beam infrastructures (at CERN and DESY), specialised irradiation facilities (in several European countries), common software tools, common microelectronic tools and engineering coordination offices 4 year project More than 80 institutions and laboratories from 23 countries 3 main activities: Networking WP2: Development of software common tools WP3: Microelectronics and detector/electronics integration WP3.1: Coordination and communication WP3.2: 3D Interconnection WP3.3: Shareable IP blocks for HEP (65nm CMOS and SiGe) WP4: Relations with industry Joint research WP8: Improvement and equipment of irradiation and test beam lines WP9: Advanced infrastructure for detector R&D Transnational access: supports small teams to carry out dedicated activities at one of the 5 European test facilities (DESY, CERN, JSI, KIT, UCL) 19

20 AIDA WP3.3: collaborative activities on 65nm WP3.3 task defines the plans for the creation of microelectronic libraries and IP blocks in advanced technologies to be made available to the community of users in HEP The choice of the 65nm technology was prompted by the needs of future vertex detectors The complexity of advanced microelectronic technologies demands for a critical mass of designers which shares knowledge and designs. This activity allows to exploit synergy in the HEP community AIDA WP3.3 members set a common choice of technology option (65nm Low Power) and blocks of general interest to be developed CERN is working to provide by Q a new frame contract with a foundry A common set of radiation characterization steps for the IP blocks has to be defined in order to have a uniform performance of the blocks in the applications Some web-pages for documenting activities and results are being prepared allowing collaborative editing 20

21 Proposed IP Blocks Block Standard Cell Library CMOS IO Standard Library PADs LVDS IO PADs SLVDS IO PADs DAC SRAM Radiation Hardened Standard Cells ADC Monitoring Temperature Sensor Bandgap References PLL ADC fast Group CERN CERN Bonn, INFN Pavia, AGH Krakow Bonn, INFN Pavia, AGH Krakow LAL, CPPM, INFN Pavia INFN Milano INFN Milano, LAPP, CPPM, LPNHE LAL, LAPP, CERN CPPM, INFN Pavia LAPP, CPPM, INFN Pavia AGH Krakow AGH Krakow 21

22 Conclusion and future plans Static, signal and noise measurements and radiation tests have been performed on devices belonging to a 65nm CMOS process A test chip including deep N-well MAPS has been submitted in a 65nm CMOS process Measurement results from this prototype circuit are encouraging and provide useful information for future submissions of larger chips The 65nm CMOS technology is considered by designers a new attractive solution for the development of high performance front-end electronics in future applications Shareable IP blocks for HEP Organization of regular Microelectronics User Group meeting to exchange information, plan and coordinate actions related to the creation of a shared library of IP blocks First submission of IP blocks in 65nm CMOS foreseen in