Low-noise Design Issues for Analog Front-end Electronics in 130 nm and 90 nm CMOS Technologies

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1 Low-noise Design Issues for Analog Front-end Electronics in 3 n and 9 n CMOS Technologies M. Manghisoni a, c, L. Ratti b, c, V. Re a, c, V. Speziali b, c, G. Traversi a, c a Università di Bergao, Dipartiento di Ingegneria Industriale, Viale Marconi, 5, 2444 Daline, Italy b Università di Pavia, Dipartiento di Elettronica, Via Ferrata,, 27 Pavia, Italy c INFN, Sezione di Pavia, Via Bassi, 6, 27 Pavia, Italy assio.anghisoni@unibg.it Abstract Deep sub-icron CMOS technologies provide wellestablished solutions to the ipleentation of low-noise front-end electronics in various detector applications. The IC designers effort is presently shifting to 3 n CMOS technologies, or even to the next technology node, to ipleent readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of noise easureents carried out on CMOS devices in 3 n and 9 n coercial processes are presented. The behavior of the /f and white noise ters is studied as a function of the device polarity and of the gate length and width. The study is focused on low current density applications where devices are biased in weak or oderate inversion. Data obtained fro the easureents provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends in LHC upgrades. I. INTRODUCTION Deep sub-icron CMOS technology has et the challenging design requireents for front-end electronics in various High Energy Physics (HEP) detector applications. For instance, CMOS coercial technologies of the quarter icron node have been extensively used for the ipleentation of radiation tolerant, low noise, low power readout circuits with very high channel density for analog and digital processing in pixel and icrostrip detectors at the Large Hadron Collider (LHC) experients under construction at CERN [-4]. The increased luinosity and track densities expected in the experients at the next generation colliders (LHC upgrades, International Linear Collider, Super B- Factory) set the deand for oving to ore scaled CMOS technologies [5-7]. Nowadays, CMOS processes with 3 n iniu feature size are widely available for Application Specific Integrated Circuits (ASICs) design, and 9 n processes are coing on-line as the next industrial generation; therefore, the IC designers effort is presently shifting to these technology nodes to ipleent readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. At nanoscale geoetries, below n feature sizes, odeling the behavior of the analog paraeters of these devices is a tricky proble, since soe effects which can deeply affect short channel MOSFET perforance, becoe ore difficult to foresee. This work presents the results relevant to the noise characterization of single CMOS devices 483 belonging to two coercial CMOS processes with iniu feature size of 3 n and 9 n anufactured by STMicroelectronics. The devices were characterized at drain currents fro several tens of µa to A, that is, the usual operating currents of input devices in integrated chargesensitive aplifiers. In these conditions, deep sub-icron devices are biased in weak or oderate inversion. The behavior of the ain noise paraeters odelling the /f and white noise ters is studied as a function of the device polarity and of the gate length and width to account for different detector requireents. The wide set of easureents provides a powerful tool to establish design criteria in 3 n and 9 n CMOS processes. The analysis of the experiental results also includes the coparison of noise paraeters obtained fro the two technology generations. This is expected to provide useful hints for the choice of the proper CMOS node to be used for detector frontend electronics in view of future applications in the field of HEP electronic instruentation such as LHC upgrades. II. EXPERIMENTAL DETAILS A. Investigated Devices The MOSFETs studied in this paper belong to two coercial CMOS processes with 3 n and 9 n iniu feature size anufactured by STMicroelectronics. The axiu allowed supply voltage V DD is +.2 V for devices in the 3 n process and +. V for devices in the. The physical thickness of the gate oxide t OX is 2. n, and.6 n respectively; for devices in inversion the electrical gate oxide thickness can be estiated to be 2.4 n and 2. n [8], therefore, the corresponding effective gate capacitance per unit area C OX, is about 5 ff/µ 2 and 8 ff/µ 2. In the 3 n process and NMOS devices with gate length L of.3,.2,.35,.5,.7 and µ, and gate width W of 2, 6 and µ were investigated. In the we studied devices of both polarities with gate length of.,.3,.2,.35,.5 and.7 µ, and gate width of 2 and 6 µ. Devices with such a large W are coonly used as front-end eleents in readout systes for particle detectors, in order to achieve the best noise perforances [9]. In both processes all NMOS devices were laid out using a standard open structure, interdigitated configuration.

2 Noise Voltage Spectru [nv/hz /2 ] NMOS W/L=6/.2 I D =5 µa, V DS =.6 V /f Slope (α f =) Noise Voltage Spectru [nv/hz /2 ] NMOS W=6 µ Id=25 µa, V DS =.6 V L=.3 µ L=.35 µ L=.7 µ Figure : Gate referred noise voltage spectra for NMOS and devices with W/L=6/.2 belonging to the (I D =5 µa, V DS =.6 V). B. Measureent setup Measureents of static and signal paraeters were carried out with an Agilent E527B Precision Measureent Mainfrae with E528B SMU Modules. The spectral density of the noise in the channel current of the exained devices was easured using instruentation purposely developed at the Electronic Instruentation Laboratory, University of Pavia. The noise of the DUT is aplified by a wideband interface circuit and detected by a Network/Spectru Analyzer HP495A []. This syste allows for noise easureents in the Hz MHz range. III. NOISE MODEL AND PARAMETERS In a MOSFET, the noise in the channel current can be expressed by an equivalent noise voltage generator referred to the gate of the device. A rather general expression for the power spectral density of the voltage noise is expressed by eans of equation () where the first ter is deterined by channel theral noise and noise contributions fro parasitic source/drain, gate and bulk resistors while the second ter is given by /f noise in the channel current [] S (f) = S S (f) () e W + In the low current density operating region, the white noise voltage spectru S w 2 is doinated by channel theral noise and can be expressed by eans of its equivalent noise resistance: R eq B /f 2 SW nγ = = α W (2) 4k T g were k B is the Boltzann s constant, T is the absolute teperature, g is the device transconductance, n is a coefficient proportional to the inverse of the subthreshold slope of I D as a function of V GS, γ is a coefficient ranging fro /2 in weak inversion to 2/3 in strong inversion and α W is an excess noise factor [2]. The /f noise in the channel Figure 2: Noise voltage spectra of NMOS with gate width W=6 µ and different gate length L belonging to the 9 n process (I D =25 µa, V DS =.6 V). current can be odeled by the relationship: K 2 f S /f (f) =. (3) α C f f K f is an intrinsic process paraeter for /f noise and C i =C OX WL is the gate oxide capacitance, whose value depends on the size of the MOSFET. The exponent α f deterines the slope of this low frequency noise ter and its value is usually between.8 and.2. According to equations (2) and (3) the noise paraeters α W, γ, K f and α f, together with static and signal paraeters n and g, fully characterize the noise perforance of MOS transistors. IV. NOISE MEASUREMENT RESULTS Noise voltage spectra were easured for and NMOS with different gate widths and lengths belonging to both the investigated technologies. Fig. to Fig. 5 are a typical set of experiental results concerning devices in the. For the devices in the 3 n process, noise easureent results can be found in [3], while the effects of ionizing radiation on the noise properties are studied in [4]. The device paraeters were characterized at drain currents I D below A, as dictated by power dissipation constraints in high density onolithic front-end systes. In these conditions nanoscale devices are biased in weak or oderate inversion. Fig. copares the noise voltage spectra of a and an NMOS with the sae gate diensions. The devices are biased at I D = A, that is in the oderate inversion region, where the NMOS has a larger transconductance with respect to the. This results in a saller channel theral noise for the NMOS, as it appears in the high frequency part of the spectra. The retains an advantage on the NMOS in ters of /f noise, which doinates the low frequency portion of the spectra. Figs. 2 and 3 show noise voltage spectra relevant to NMOS and devices with W=6 µ and different gate lengths L, biased at the sae drain current. The devices are close to weak inversion, therefore, white noise should not be sizably affected by L variations. At low frequencies, /f noise i 484

3 Noise Voltage Spectru [nv/hz /2 ] W=6 µ Id=25 µa, V DS =.6 V L=. µ L=.2 µ L=.7 µ Noise Voltage Spectru [nv/hz /2 ] W/L=6/.2 V DS =.6 V Id=. A Id=.25 A Id=. A Figure 3: Noise voltage spectra of with gate width W=6 µ and different gate length L belonging to the 9 n process (I D =25 µa, V DS =.6 V) Figure 5: Noise voltage spectra of a with W/L=6/.2 belonging to the at different values of drain current I D ( V DS =.6 V)..4 Noise Voltage Spectru [nv/hz /2 ] NMOS W/L=6/.5 V DS =.6 V Id=. A Id=.25 A Id=. A α f L=. µ L=.3 µ L=.2 µ L=.35 µ L=.5 µ L=.7 µ NMOS Figure 4: Noise voltage spectra of an NMOS with W/L=6/.5 belonging to the at different values of drain current I D (V DS =.6 V). increases with decreasing L. According to (3), this is due to the reduction in the input capacitance C i. Figs. 4 and 5 show the effect of the drain current I D on the noise voltage of an NMOS and a. Channel theral noise is reduced by increasing I D in agreeent with (2), since the transconductance correspondingly increases. As far as the /f noise coponent is concerned, it is not affected by I D variations for NMOS devices while a slight increase with the drain current is detected for devices. In the following the behavior of the /f and white noise paraeters is studied as a function of the device polarity and of the gate length and width to account for different detector requireents at different drain currents. A coparison of paraeters concerning the two investigated technologies is also shown. A. /f noise paraeters K f and α f In Fig. it can be observed that the slope of the /f noise coponent of the spectru α f is not equal to. The analysis of the experiental results shows that α f is consistently Drain Current [A] Figure 6: Slope of the /f noise ter as a function of the drain current I D for NMOS and devices with W=6 µ belonging to the ( V DS =.6 V). saller than in NMOSFETs and larger than in FETs. This behavior was detected in other deep subicron processes [5,6] and could be related to a different profile of oxide traps interacting with carriers of different polarity. Typical values of α f obtained for devices of both polarities in the two investigated processes are reported in table together with the spread across saples with different gate diensions and tested in different bias conditions. Fro the easured noise voltage spectra it has been found that /f noise paraeter α f does not exhibit any clear dependence on the channel length L nor on the drain current I D as shown in Fig. 6. Fig. 7 shows the behavior of the Table : Slope coefficient of the low frequency noise ter. α f Process 3 n 9 n NMOS.85±.5.85±.5.9±.5.9±.5 485

4 4 3 Kf [J -25 Hz (alpha-) ] I fro. to A, V =.6 V D DS 3 n process n process offset =.82 +/- 2.2 slope =.97 +/-.2,2,4,6,8,2 As-drawn Gate Length [µ] Figure 7: /f noise coefficient K f as a function of the gate length L for NMOS belonging to the 3 n and es (V DS =.6 V). Figure : Equivalent channel theral noise resistance R eq for devices belonging to the 3 n process ( V DS =.6 V). Kf [J -25 Hz (alpha-) ] n process Gate Overdrive Voltage [V] offset =.68 +/-.45 slope =.96 +/-.2 NMOS L>.3 µ Figure 8: /f noise coefficient K f as a function of the overdrive voltage for belonging to the 3 n and es ( V DS =.6 V). Figure : Equivalent channel theral noise resistance R eq for NMOS devices belonging to the (V DS =.6 V) n process NMOS L >.3 µ offset = /-.9 slope =. +/ offset =.4 +/- 5. slope =.83 +/ Figure 9: Equivalent channel theral noise resistance R eq for NMOS devices belonging to the 3 n process (V DS =.6 V). 486 Figure 2: Equivalent channel theral noise resistance R eq for devices belonging to the ( V DS =.6 V).

5 /f noise coefficient K f for NMOS devices as a function of the channel length. In both processes the /f noise coefficient K f is larger for devices with channel length close to the iniu allowed by the technology and is lower in the with respect to 3 n process. Moreover it is independent of the drain current in the NMOS. Measureents on devices show an increase of K f both with the channel length L and the drain current I D. According to [6,7] this behavior is due to the origin of flicker noise that, in p-channel devices, is often attributed to obility fluctuations, and shows an increase of K f with the overdrive voltage. In Fig. 8 values of K f obtained for devices with different gate geoetry and bias condition are reported as a function of (V GS -V T ). According to this plot K f is larger for devices in the 3 n process and its bias dependence is weaker in 9 n technology. B. White noise paraeters α W and γ White noise is evaluated in ters of the equivalent channel theral noise resistance R eq. Figs. 9 and show values of R eq as a function of nγ /g obtained for NMOS and devices belonging to the 3 n process. According to equation (2) the slope of the linear fit is deterined by the coefficient α W while the offset is due to contributions fro parasitic resistance. Values of α W close to unity were found for all devices except for NMOS with the iniu feature size allowed by the technology. This eans that there are no sizeable short channel effects in the considered operating regions. Negligible contributions were found fro parasitic resistance. Sae results were obtained for devices as shown in Figs. and 2. In this case no data are available for channel theral noise in NMOS devices with L.3 µ. V. CONCLUSIONS The paper presents noise easureent results concerning devices belonging to two different CMOS technology nodes, naely the 3 n and the 9 n STM processes. The analysis of the experiental results show that channel theral noise equations developed to describe the device behavior in the considered operating regions provide a reliable odel, with short channel effect playing a inor role in both the considered processes. /f noise results confir the behavior detected in previous subicron processes as far as the dependence on device polarity and bias and gate geoetry is concerned. Extracted noise paraeters show that using the ay ensure an iproveent in the noise perforances in applications where large signal dynaic range is not needed while iniaturization can be an asset. VI. REFERENCES [] W. Snoeys, F. Faccio, M. Burns, M. Capbell, and E. Cantatore, et al., Layout techniques to enhance the radiation tolerance of standard CMOS technologies deonstrated on a pixel detector readout chip, Nucl. Instru. Methods Phys. Res. A, vol. A439, p. 349, 2. [2] P.F. Manfredi, and M. Manghisoni, Front-end electronics for pixel sensors, Nucl. Instru. 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