IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 56, NO. 3, JUNE

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1 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 56, NO. 3, JUNE Noise Minimization of MOSFET Input Charge Amplifiers Based on 1 and 1N 1=f Models Giuseppe Bertuccio and Stefano Caccia Abstract The optimization of the noise performance of integrated complementary metal oxide semiconductor (CMOS) charge amplifiers is studied in detail considering accurate 1 noise modeling for the input metal oxide semiconductor field-effect transistor (MOSFET) biased in a strong inversion-saturation region. This paper aims to generalize and correct previously published analyses which have been based on two limiting and sometimes not applicable assumptions: a fixed MOSFETs bias current and the general validity of the McWhorter 1 noise model. This study considers the two main 1 noise models: 1) the mobility fluctuation, known as 1 or Hooge model, which is followed by p-channel MOSFETs and 2) the carriers number fluctuation, also known as 1N or McWhorter model, which is applicable only for n-channel MOSFETs. The front-end noise optimization is made with the 1 component alone, thus determining the ultimate performance, and also considering the presence of series and parallel white noise sources. It is shown that different design criteria are valid of p- or n-channel MOSFETs: the 1 model results in an optimum bias current and a different optimum gate width with respect to 1N model. Two-dimensions suboptimum noise minimization criteria are derived when power or area constraints are imposed to the circuit design. Starting from experimental data on CMOS 1/f noise, examples of application of the presented analysis are shown to predict the lower limits of the 1 noise contribution for the currently available CMOS technologies. Index Terms Charge amplifier, complementary metal oxide semiconductor (CMOS) integrated circuit (IC), integrated circuits (ICs), low-noise circuit, 1/f noise. I. INTRODUCTION CHARGE-SENSITIVE amplifiers (CSAs) are widely employed in several applications which use sensors delivering information by means of electrical charge signals. CSAs are generally employed in the front-end of application-specific integrated circuits (ASICs) to read out photon and particle detectors or micromechanical capacitive sensors [1], [2]. Since 1955, when Emilio Gatti and co-workers proposed the charge Manuscript received July 16, 2008; revised November 15, Current version published June 17, This work was supported by the Italian Institute of Nuclear Physics (INFN) and the Italian Ministry of University and Scientific Research (MIUR). G. Bertuccio is with the Department of Electronics Engineering and Information Science, Politecnico di Milano and INFN-sez. Milano, Polo Regionale di Como, Como 22100, Italy ( Giuseppe.Bertuccio@polimi.it; stefano. caccia@polimi.it). S. Caccia was with the Politecnico di Milano, Polo Regionale di Como. He is now with ST Microelectronics, Milano, Italy. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TNS amplifier concept for radiation detector readout [3], a large variety of implementations have been studied and developed involving all types of front-end devices and technologies (junction field-effect transistor (JFET), metal semiconducor fieldeffect transistor (MESFET), high-electron mobility transistor (HEMT), bipolar junction transistor (BJT), metal-oxide semiconductor field-effect transistor (MOSFET)) in order to maximize performance in terms of speed, noise, power consumption, or chip area. In the last five years, intense attention has been given to the design of charge amplifiers implemented in CMOS technologies because of their advantages in terms of high integration density, low power consumption, wide bandwidth and digital logic integration, as required in many applications. The most common objective in CSA design is the minimization of the equivalent noise charge (ENC), which requires a careful design of the input stage. In particular, the noise associated with the drain current of the input device plays a major role in ultra low-noise design, as recently demonstrated with CSA with noise levels of a few electrons root mean square (rms) [4]. Previous works have studied the noise optimization of CMOS CSA but with two restrictive and sometimes not applicable assumptions: 1) a fixed bias current of the input MOSFET, mainly determined by power consumption or bandwidth constraints and 2) the general validity of the McWhorter model (see next section) [5] [10]. In our analysis, we remove both of these assumptions and consider the two main models for the noise: Hooge and McWhorter models; in this way, we derive the general and correct criteria for minimizing ENC in case of a p- or n-channel front-end input device. In Sections II and III, the MOSFETs noise models are introduced and the related ENC are derived for, and subsequently compared. In Sections IV VI, the noise minimization and design criteria based on and models are presented, taking into account also power or area constraints. In Section VII, examples of application of the theory on currently available technologies are shown. II. NOISE MODELS FOR MOSFETS A. Introduction The MOSFET drain current depends on the number and on the mobility of charge carriers in the channel, so that the fluctuation of can be attributed to random variations of and/or. Presently, three main models have been proposed to describe the noise in MOSFETs: 1) the or McWhorter Model, which considers the fluctuation of due to the channel conductivity modulation /$ IEEE

2 1512 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 56, NO. 3, JUNE 2009 caused by trapping/detrapping of carriers tunneling into the gate oxide [11], [15]; 2) the or Hooge Model, which assumes that carrier mobility fluctuations originate the noise [12], [13], [15]; 3) the unified model, which explains the experimental data by assuming that the charge trapping/detrapping process produces correlated and fluctuations [14]. Each model predicts a different dependence of the noise spectral density on the drain current and on the MOSFETs gate width and length. The experimental data show that the noise can be well explained by the or model depending on carrier type and bias condition [15] [18]. In strong inversion, p-mosfets follow (Hooge) and n-mosfets follow (McWhorter) model; this different behavior can be explained by the fact that the channel in n-mosfets are closer to the gate oxide so that charge trapping/detrapping is much more significant than in p-mosfets, in which the channel is farther from the oxide interface [23]. Both NMOS as PMOS have been found to follow the model when biased in weak inversion. The equation of the unified model can describe both the n- and p-type MOSFETs noise by adjusting a scattering parameter which accounts for the correlated variations of and due to charge carrier trapping/detrapping [14]. The unified model is commonly implemented in circuit simulators for its generality [19]. However, for a given MOSFET (p or n-type) biased in a specific region (weak or strong inversion, linear or saturation region), the analytical description of the 1/f noise in or models is much simpler, but strongly agrees with the experimental data. For these reasons, we will refer to these two models in our analysis. We will consider the case of MOSFETs biased in strong inversion/saturated region, as usually occurs in input devices of charge amplifiers. B. and Models in Strong Inversion Saturation Region In a strong inversion-saturation region, the drain noise current spectral density predicted by the and models are, respectively, [15] (1) (2) Fig. 1. Measured gate voltage noise spectral density-frequency product S 2f as a function of the drain current I for two p- and two n-type MOSFETs. The gate width W and the length L are indicated. The transistors are biased in p the strong inversion saturation region. For the p-mosfets, a dependence on I is observed in agreement with the 1 model (4), while for the n-mosfets, independence of I, as predicted by the 1N model (5), is observed. in which is the subthreshold slope coefficient. Dividing (1) and (2) by, the gate voltage spectral densities are obtained Significant differences between the and models are evident: while the model predicts the increase of with the root square of the bias current, the model predicts as being independent of. Moreover, the dependences of and on the gate width and length are completely different. Fig. 1 shows the measured versus for two n-mos- FETs and two p-mosfets ( m; m and m). The spectral densities have been measured in a 10 Hz 1 MHz bandwidth and the component has been extracted. It can be seen that is independent from for n-mosfets, but depends on for P-MOSFET, as predicted by (4) and (5). Also, its dependence on and has been found in accordance with the two models [20]. (4) (5) in which is the elementary charge, is the carrier mobility, is the Boltzman constant, is the absolute temperature, is the gate oxide capacitance per unit area, is the Hooge constant, is the oxide/interface trap density per unit volume and energy at the quasi Fermi level, is the tunneling parameter of the traps, and are the gate width and length, respectively, and is the drain current. When the effects of the carrier velocity saturation in the channel are not relevant, the MOSFET s transconductance can be written as (see the Appendix) (3) III. EQUIVALENT NOISE CHARGE FROM SERIES NOISE A. Introduction The input transistor of a charge amplifier contributes to a high percentage to the ENC and always determines the ultimate noise performance of the circuit; therefore, the prediction of its noise contribution is fundamental. In order to determine the contribution of the noise, let us consider a general expression for the voltage noise spectral density of the input MOSFET as (6)

3 BERTUCCIO AND CACCIA: NOISE MINIMIZATION OF MOSFET INPUT CHARGE AMPLIFIERS 1513 in which can be derived from (4) and (5) for the and models. The due to the noise can be written as [21] in which is a constant related to the type of pulse shaping; is the load capacitance at the preamplifier input, given by the sum of the detector, feedback, test, and stray capacitances [21]; is the part of the MOSFET gate capacitance which depends on the gate geometry, while the size-independent capacitance component must be included in. Due to the generality of (6), (7) is valid for all noise models and MOSFET bias condition. B. for and -type MOSFETs By combining (4) (7), the for a and -type MOSFETs operating in a strong inversion saturation can be written as (10) Equation (10) is the condition of validity for (8) and (9), which states that the MOSFET is biased in strong inversion or, more generally, at a current for which (1) and (2) are verified to be valid. is a reference current given by (7) (8) (9) (11) in which is the subthreshold slope and is the minimum value of the so-called inversion coefficient (see the Appendix). We have experimentally verified the validity of (1) and (2) down to [20]. It can be observed that the differences between (8) and (9) are quite relevant for the front-end design criteria. The (Hooge) model predicts that increases as, while for the (McWhorter) model, is independent from the transistor current. Moreover, the transistor geometry, implicit in, differently affects in (8) and (9). These diversities will determine different design criteria for the minimization, as will be shown in the following sections. IV. ENC MINIMIZATION A. Introduction Let us first consider the case in which the is the dominant noise component and let us find the conditions to minimize the ENC in case of type. The designer can practically control two variables, the gate capacitance and the bias current of the input MOSFET. The search for a minimum of given by (8) has to be done considering the constraint on the current given by (10), which makes the two variables and not completely independent. If (10) is not considered properly, an apparent contradiction is found. In fact, when searching for the minimum of (8), it can be intuitive to set the current at its minimum value ; in this case, the ENC minimum is found for. On the other hand, if the current is set at an arbitrary constant value, the minimum of (8) is found for. The general problem of minima will be solved in the following two subsections. B. Absolute Minimum The absolute minimum of can be searched by setting the minimum bias current allowable for a generic MOSFET size (i.e., and ) according to (10) and (11), and finding which MOSFET size minimizes (8). By setting, (8) becomes whose minimum is reached for given by (12) and it is (13a-b) in which is the minimum current in strong inversion, according to (10) and (11), for a capacitive-matched MOSFET at which the absolute minimum (13a) is reached. It can be observed that (13a) does not depend on the gate length, although shorter gate MOSFETs imply higher and. C. Locus of Relative Minima In some cases, the optimum gate width and current could not be compatible with the constraints on chip area, power consumption, bandwidth, or loop gain requirements; therefore, smaller MOSFETs or lower or higher bias currents must be chosen. In order to determine the design criteria in these cases, it is useful to refer to Fig. 2, which shows an example of a 3-D graph versus of (8). has been set to zero outside the field of validity established by (10). It can be determined that for an arbitrarily chosen current, (8) has a minimum at, but this is a valid solution only for, as stated by (10), (11), and (13b). This case corresponds to the line B-C, locus of relative minima of for any current. For, the minimum of is located on the border curve D-A-B corresponding to the minimum-allowable current for a given MOSFETs size. The equation of the D-A-B curve is given by (10) which can be rewritten as (14) which sets the relationship between and to achieve minimum in case. To sum up, the design criteria to achieve minimum for any value of the bias current are for for (15a-b)

4 1514 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 56, NO. 3, JUNE 2009 Fig type MOSFETs: ENC given by (8) as a function of the bias current and the ratio C =C between the gate capacitance and the load capacitance at the amplifier input. The ENC has been set to zero outside the field of validity of (8) given by (10). The absolute minimum at C =C =1(point A) and the locus of the relative minima given by the line D-A-B-C are shown. In conclusion, the relative minimums of belong to the line D-A-B-C, which sets a specific relationship between the MOSFET size (i.e., ) and its bias current (15a-b). The absolute minimum is located in A, corresponding to and. D. Worsening for Arbitrary Conditions It is useful to calculate the worsening of with reference to the absolute minimum for any choice of MOSFET size and bias current by combining (8) and (13a-b), the worsening factor (WF) can be derived Fig. 3. Worsening factor WF (16) as a function of the ratio between the MOSFET current I and the optimum bias current I given by (13b). The WF is calculated along the path D-A-B-C of relative minimums shown in Fig. 2. and the noises are present. The total is therefore given by in which the series white noise contribution is [21] (17) (18) where and are the time-parameter (usually referred to shaping or peaking time) and the shape factor of the filter, respectively [21]; is the MOSFETs white voltage noise spectral density which, in strong inversion and saturation, is given by (19) (16) In particular, WF can be calculated along the path D-A-B-C of relative minima shown in Fig. 2; the result is drawn in Fig. 3 as a function of. Due to the dependence of on the (8) and due to the fact that the locus of minima are considered, an worsening below 10% can be achieved if. This feature allows quite large flexibility in choosing the MOSFETs current out of its optimum without a significant increase of the noise contribution. V. MINIMIZATION FOR AND WHITE NOISES A. Absolute Minimum In general, the contribution of the white noise sources (series and parallel) are not negligible with respect to the component, so it is interesting to consider the case in which the white in which depends on the MOSFET type (P or N), gate length, and overdrive voltage [22]. Assuming a first approximation model of constant, the contribution can be derived from (18) and (19) as (20) The white parallel noise contribution is due to the detector current, to the MOSFET gate current, and to the feedback network. It can be written as [21] where the noise current spectral density noise of three currents (21) is the sum of the shot (22) in which is the detector leakage current, is the MOSFET gate leakage current, and is the noisy current that can be associated with the feedback network. Excluding very particular

5 BERTUCCIO AND CACCIA: NOISE MINIMIZATION OF MOSFET INPUT CHARGE AMPLIFIERS 1515 cases (MOSFETs with a gate oxide thickness of a few nanometers and ultra-low leakage detectors), is in the subpicoampere range and its noise contribution is generally negligible. Considering (20) and (21), (17) can be rewritten as (23) in which,, and are derived from (20), (8), and (21) (24) We will find the conditions to minimize, which depends on the three variables,, and. As far as the bias current is concerned, it can be observed that decreases with while increases with, so that an optimum bias current exists. As far as the gate capacitance is concerned, at a given bias current, it can be easily derived that has a minimum for while is minimized for at and for for, as derived in Section IV. The optimum capacitance that minimizes is therefore expected to be in the range of and. Last, the optimum shaping time depends on the weight of the series and parallel white noise components. The minimum of (23) can be found by nulling its partial derivatives with respect to,, and. In the case of a constraint on the shaping time, the optimum and bias current are Fig. 4. Example of a plot of ENC given by (23) as a function of the bias current and the ratio C =C between the gate capacitance and the load capacitance at the amplifier input. The ENC has been set to zero outside the field of validity of (23). The absolute minimum (point M) is C =C =1and I = I = 14 ma (25). The line on the surface is the locus of the relative minima since the bias current is varied, given by (28). If the optimum current is lower than the minimum current, then it must be set as, and defining as the ratio the suboptimum capacitance and shaping time become (27a) (27b) (25a) so the optimum condition is always achieved at capacitive matching. The optimum shaping time is given by (25b) If can be chosen, the corresponding optimum current is obtained by setting in (25a). The optimum current, if higher than the minimum-allowable value, is the one at which and, as expected, decreases as the becomes dominant with respect to the white series noise component and vice-versa. At, and result in and the minimum of is reached, given by (26) B. Locus of Relative Minima Similar to what has been done in Section IV for, it is useful to find the locus of the relative minima of in the space in order to also reach the best noise performance when the conditions (25a) for the absolute minimum are not compatible with area, power, or bandwidth design constraints. With the help of Fig. 4, it can be seen that for a given current, the relative minima of is obtained for a value which is the solution of ; this, on the surface, represents the curve (28a) Equation (28a), under the constraint, gives the locus of the relative minima as shown in Fig. 4 (line drawn on the surface). For a given, if, the relative minima stay on the border ; for, it results in as expected (see (25a)). It can also be observed that as the current is increased, the suboptimum capacitive ratio tends toward as expected because the noise becomes the dominant component.

6 1516 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 56, NO. 3, JUNE 2009 of (30) is not negligible. The bias current can be so chosen at the highest value compatible with the power consumption constraint and considering the weight of the white series noise with respect to the other components. For a given bias current, can be minimized for a gate capacitance which is the solution of the cubic equation with the condition (32a) Fig. 5. Plot of (28b) from which the best C for every bias current can be obtained to minimize ENC. The curve is valid for I R I. Introducing the capacitive factor written as, (28a) can be (28b) Equation (28b) can be used to find the best for any bias current. Equation (28b) is plotted in Fig. 5. For, then. When, the best tends toward as expected because. When, and tend to,so minimizing. However, the condition (see Fig. 5) must be always verified in order for the MOSFET to be biased in the saturation region. VI. ENC MINIMIZATION FOR AND WHITE SERIES NOISES In contrast to, the ((9)) does not depend on the MOSFETs current; rather, it is a function of with a minimum at given by (29) in which. If also the white noise contributions (20), (21) are significant, the total can be written as In (30), and are given by (24), and is (30) (31) It can be observed that in contrast to, a finite optimum current does not exist for. For a given, decreases continuously as the current is increased, as long as the white series noise component first term (32b) Equation (32b) is derived from the constraint of (30). Equation (32a) has two limit solutions: for (no component) and for (no white series component). For realistic intermediate cases, (32) can be numerically solved by finding, which depends on the MOSFETs bias current and on the signal filtering through,, and. Fig. 6(a) and (b) shows an example of as a function of the bias current and. For any current, the locus of relative minima given by (32a) and (b) is represented by the continuous line on the surface. It can be observed that the relative minimum moves from toward as the current increases, because the component becomes dominant with respect to the white series one as the current is increased. By continuously increasing the MOSFETs current, the minimum is asymptotically approached at ; this minimum is due to the (29) plus the white parallel noise components. VII. NOISE PERFORMANCE PREDICTIONS A. Introduction It is worth applying the previous theoretical analysis to evaluate for some of the currently available CMOS technologies in order to predict the lowest limits achievable with CMOS charge amplifiers. To this aim, Fig. 7 shows the Hooge parameter for p-channel MOSFETs and the McWhorter parameter (see Section VII-C) for n-channel MOSFETs measured for different CMOS technologies. B. Noise The minimum value of can be calculated by (13a) and it is obtained by choosing a MOSFET with the gate capacitance biased at the minimum current given by (13b). As can be seen in Fig. 7, ranges from up to [15], [20], [23]. Assuming the data of Table I referred to m CMOS technology with at 293 K [20], the results can be written as

7 BERTUCCIO AND CACCIA: NOISE MINIMIZATION OF MOSFET INPUT CHARGE AMPLIFIERS 1517 Fig. 7. Experimental Hooge parameter for different p-channel MOSFETs (white symbols) and K parameter (34) for n-channel MOSFETs (black symbols) taken from different references. TABLE I CMOS TECHNOLOGY PARAMETERS Fig. 6. 1N -type MOSFETs: example of the plot of ENC given by (30) as a function of the bias current I and the ratio C =C. ENC has been set to zero outside the field of validity of (30). The red line on the surface represents the locus of the relative minima as the bias current or C =C is varied, as given by (32a) and (b). By continuously increasing the MOSFETs current, the minimum of ENC is asymptotically approached at C = C ; this minimum is due to the 1=f (29), plus the white parallel noise components. (33) and are represented in Fig. 8 as a function of. It can be observed that below seven electrons rms are obtained for 10 pf at room temperature. Moreover, electrons rms are obtained for 0.2 pf. C. Noise In order to show the parameters related to the technology or to the device explicitly, circuit designers usually write (5) for the voltage noise spectral density in two simplified forms as Fig type MOSFETs: minimum ENC calculated as a function of the load capacitance C at the preamplifier input (13a). Also, the MOSFETs bias current I (13b) and its optimum gate width obtained by setting C = C are shown. (33). The parameters for the evaluation are shown in Table I. (34)

8 1518 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 56, NO. 3, JUNE 2009 Fig. 9. 1N-type MOSFETs: minimum ENC calculated as a function of the load capacitance C at the preamplifier input (29) for two typical values of the constant K. Fig. 10. Comparison between the minimums ENC achievable at different C with N and P-MOSFETs. The considered noise parameter values K and are among the lowest experimentally measured ones (see Fig. 7). in which the constants and [J] can be derived from (5) as (35) Experimental values of or have been determined for N-channel MOSFETs of different foundries and technological nodes from 0.09 m to 0.7 m [20], [24] [27]. values have been found ranging from to Joule. Then, from (29) (36) which are represented in Fig. 9 for input load capacitance ranging from 10 ff to 10 pf. It can be observed that shows a quite large range of values depending on and. The best technologies allow reaching 30 electrons rms for 10 pf. D. P-MOSFETs versus N-MOSFETs Fig. 10 shows a direct comparison of the versus achievable with N- and P-type MOSFETs as calculated in the previous sections. The considered values of the noise parameters and are among the lowest experimentally measured ones. As observed, the best P-MOS- FETs gives an of about four times lower than that of one of the best N-MOSFETs. It must be considered that the lower P-MOSFET noise can be advantageous only when this component is at least comparable with respect to the white series and parallel noise contributions. VIII. CONCLUSION The noise of the MOSFETs drain current can be well described by two different models: the Hooge model for the p-channel and the McWhorter model n-channel MOSFETs. Since the two models show different dependence of the noise intensity on the drain current and transistor geometry (8), (9), distinct design criteria have been derived for minimizing the noise of charge amplifiers with a capacitive input load. The bias current and the geometrical dimensions of the input transistor (gate width, length, or capacitance ) have been assumed as free parameters in the optimization procedure. It has been shown that the minimum noise contribution is obtained at capacitive matching for both the models (13a), (29). The model requires a minimum bias current (13b) within the strong-inversion region, different from the model, which is current independent (29). In case of p-mosfets, a simple equation (15a-b) has been derived to minimize the noise also in case the transistor had to be biased at a nonoptimum current because of the bandwidth or power consumption constraints. It has been shown that the best gate capacitance is never higher than (15b). In the presence of white noises, the optimum condition for the model remains as the capacitive matching but an optimum bias current exists (25), while for, the optimum gate capacitance depends on the chosen bias current but ranges from to (32). In case of n-mosfets, a simple equation (32) has been derived to find the optimum transistor s gate width which minimizes at a given drain current. Finally, the application of the theory with some of the existing technologies (Section VIII) allows to predict the ultimate contribution for p- and n-channel transistors. The n-mosfets give higher than p-mosfets by a factor 4. The best p-mosfets are allowed to reach noise levels as low as a few electrons rms for a detector capacitance below 10 pf. APPENDIX EKV MOSFET MODEL The drain current of a MOSFET biased at can be written by using a single equation valid from weak to strong inversion, as given by the EKV model [28] (A1)

9 BERTUCCIO AND CACCIA: NOISE MINIMIZATION OF MOSFET INPUT CHARGE AMPLIFIERS 1519 Fig. 11. Fit of the experimental normalized I versus V characteristic of two n-mosfets to the EKV model, showing very good agreement. The y axis represents the inversion coefficient R = I =I.ForR<0:01, the characteristic is well approximated by (A3), for R > 5 by (A4), which are drawn as well. in which the specific current the drain current at, which is almost equal to half of, is given by (A2) In (A2), is the subthreshold slope, and is the thermal voltage. If is much smaller or bigger than th, (A1) can be simplified to derive the expressions for the weak (subthreshold) and inversion regions, respectively, as follows: (A3) (A4) From (A1), it is possible to define a dimensionless parameter, called inversion coefficient, which is useful to identify the transistor s region of operation. When, (A1) can be approximated by (A3) with errors less than 10%: the MOSFET is operating in weak inversion. If, (A1) is well approximated by (A4) with an error of less than 10%: the MOSFET operates in strong inversion. When, the transistor operates in moderate inversion. Fig. 11 shows an example of the very good agreement between the EKV model and the experimental data of two MOSFETs with a W/L of 30/2 and 10/0.4. In strong inversion, the transconductance can be derived by differentiating (A4) (A5) Equation (A5) predicts a linear dependence of from the drain current, which is actually verified when the effects of the carrier velocity saturation are not significant. Fig. 12 shows an example of linear fit on experimental for p-mosfets with m and different gate lengths from 2 mdownto0.4 m. It can be observed that the linear Fig. 12. Squared transconductance g versus drain current for p-mosfets with W =30m and gate lengths from 2 m down to 0.4 m. The dependence of g on I (A5) can be assumed as linear within a current density (I =W ) range of interest in low-power integrated charge amplifiers design. approximation for can be acceptable within a current density range generally of interest in low-power integrated charge amplifiers design. ACKNOWLEDGMENT The authors would like to thank M. Spicci and M. Troiani for carefully reading and reviewing the manuscript, T. Rossi and A. Pozzi for the noise measurements, and the reviewers for their advice. REFERENCES [1] B. Philips, Ed., in Proc. IEEE Nuclear Science Symp., Medical Imaging Conf. Room Temperature Semiconductor Detector, San Diego, CA, Oct. 29 Nov. 4, [2] G. Bertuccio, 1=f noise in p- and n-channel MOSFETs, in Proc. IEEE Int. Symp. Circuits and Systems, May 23 26, 2005, vol. 6, pp [3] C. Cottini, E. Gatti, G. Giannelli, and G. Rozzi, Minimum noise preamplifier for fast ionization chambers, Il Nuovo Cimento, vol. 3, p. 481, [4] G. Bertuccio and S. Caccia, Progress in ultra-low-noise ASICs for radiation detectors, Nucl. Instrum. Methods Phys. Res. A, vol. 579, no. 1, pp , [5] Z. Y. Chang and W. Sansen, Noise optimization of CMOS wideband amplifiers with capacitive sources, in Proc. ISCAS, 1989, pp [6] W. M. Sansen and Z. Y. Chang, Limits of low noise performance of detector readout front ends in CMOS technology, IEEE Trans. Circuits Syst., vol. 37, no. 11, pp , Nov [7] L. Fasoli and M. Sampietro, Criteria for setting the width of CCD front-end transistor to reach minimum pixel noise, IEEE Trans. Electron Devices, vol. 43, no. 7, pp , Jul [8] P. O Connor and G. De Geronimo, Prospects for charge sensitive amplifiers in scaled CMOS, Nucl. Instrum. Methods Phys. Res. A, vol. 480, pp , [9] L. Fabris and P. F. Manfredi, Optimization of front-end design in imaging and spectrometry applications with room temperature semiconductor detectors, IEEE Trans. Nucl. Sci., vol. 49, no. 4, pp , Aug [10] M. Manghisoni, L. Ratti, V. Re, and V. Speziali, Low-noise design criteria for detector readout systems in deep submicron CMOS technology, Nucl. Instrum. Methods Phys. Res. A, vol. 478, pp , [11] A. L. McWhorter, Semiconductor Surface Physics, R. H. Kingston, Ed. Philadelphia, PA: Univ. Pennsylvania Press, [12] F. N. Hooge, 1/f noise is no surface effect, Phys. Lett. A, no. 29, p. 139, [13] F. N. Hooge et al., Experimental studies on 1/f noise, Rep. Prog. Phys., vol. 44, no. 5, pp , 1981.

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