Buffered LABRADOR (BLAB3) Design Review. Gary S. Varner 4 NOV 09

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1 Buffered LABRADOR (BLAB3) Design Review Gary S. Varner 4 NOV 09

2 Baseline confirmation Goals for today Ice Radio Sampler (IRS) as sampling/storage array basis High rate/long latency architecture Review simulations Basic functionality Additional monitor/control features Flag action items (prior to submission) Anything missing? Target submission (26 OCT 09 delayed) [23 NOV 09]

3 BLAB3 Specifications samples/chan (>5us trig latency) 8 channels/blab3 ASIC 8 Trigger channels ~9 bits resolution (12[10]-bits logging) 64 samples convert window (~16ns) 4GSa/s 1 word (RAM) chan, sample readout 1+n*0.02 us to read n samples (of same 64) 30 khz sustained readout (multibuffer) Time alignment critical Synchronize sampling to accelerator RF clock >5us a must for trigger, since single photon rates high Needs Gain!

4 Gain Needed Amplifiers dominate board space Readout ASIC pair What gain needed? At 10 6 gain, each p.e. = 160 fc At 2x10 5 gain (better for aging), each p.e. = 32 fc In typical ~5ns pulse, Vpeak = dq/dt * R = 32uA * R = 32mV * R [kω] (6.4mV) Gain Estimate Rterm 1 p.e. peak 50 1mV 1k 20mV 20k 400mV

5 Starting place: IRS design 8 HS inputs 64 x 2 samples/ch 32k deep storage 64 sample select 8x64 Wilk ADC 12 output bits Random Access 10-bits Write Sel 10-bits Read Sel 3-bits channel 7-bits ADC ch 129 bonding pads 180um min pitch

6 BLAB3 Single Channel Sampling: 128 (2x 64) separate transfer lanes Recording in one set 64, transferring other ( ping-pong ) Storage: 64 x 512 (512 = 8 * 64) Wilkinson (32x2): 64 conv/channel

7 IRS Input Coupling Input Coupling versus total input Capacitance Input coupling versus frequency Analog Bandwidth [-3dB frequency] C=15fF,Ron=1k R_S = 50Ohm -1 C=15fF,Ron=5k -2 C=25fF,Ron=1k -3 C=25fF,Ron=5k Total input Capacitance [ff] Frequency [GHz] Input bandwidth depends on 2x terms f3db[input] = [2*π*Z*C tot ] -1 Relative amplitude [db] f3db[storage] = [2*π*R on *C store ] -1

8 IRS Input Coupling Input inductance impedance versus frequency Input coupling versus frequency Impedance [Ohms] Bond-wire Bump-bond Relative amplitude [db] Bond-wire Bump-bond Frequency [GHz] Frequency [GHz] Role of inductance

9 Input coupling sim (35fF sample) Onto chip ~1 GHz analog bandwidth Into storage cell

10 Trans-Impedance Amp Basic building block have used before

11 3kΩ TIA Sim ~380MHz analog bandwidth

12 TIA timing simulation results Some overshoot a realistic current pulse?

13 Summary Plot ABW TIA Analog Bandwidth vs. Gain Analog Bandwidth [MHz] x gain 100uA TIA Gain [k-ohm]

14 Summary Plot ABW vs. Bias TIA Analog Bandwidth vs. Gain Analog Bandwidth [MHz] Saturates ~500uA 3k TIA Bias Current [ua]

Simulated Noise Input noise Saturates ~500uA Output noise Noise integral from 100.00000K Hz to 1.

15 Simulated Noise Input noise Saturates ~500uA Output noise Noise integral from K Hz to G Hz Total integrated output noise voltage = u V Total equivalent input noise voltage = u V

16 Phase Response ~300MHz

17 Sample Cell Main element is buffer amp (OTA) Relatively low current (10 s ua) operation possible

18 Effect of too small a storage Cap Desire small C for better Input Coupling Cstore = 35fF

19 Storage Cell Diff. Pair as comparator Only power on selected block

20 Another Constraint: Leakage Current Need small C for Input Coupling Can Improve? (readout faster) Sample channel-channel variation ~ fa leakage typically

21 Sample transfer realistic capacitance <= 16ns settling 200Ω isolation resistor to reduce ringing

22 IRS Sampling Method Base delay

23 Simulated sampling speed Sampling Simulation with full parasitic Extraction Extracted Sampling Rate [GSa/s] RCObias [V] RCObias VadjP1,2 = RCObias; VadjN1,2 = VDD-RCObias

24 Triggering Need 9 th channel for monitoring

25 Temperature Dependence Sample 6GSa/s aperature (172ps = 5.8GSa/s) 0.2%/degree C (can correct) Matches SPICE simulation

26 Triggering same as previous results Trigger 1-shot Width Adjust T_1_TRG Power (T_1_TRG) 100 Output Width [ns] Discharge Current [ua] Monitor 9 th channel (uses Ch.1 threshold) to compensate for temperature dependence

27 Wilkinson ADC No missing codes Linearity as good as can make ramp Can bracket range of interest BLAB3 Digitization 12-bit ADC Run count during ramp Modified! (self-counter) [~0.7 GHz] Excellent linearity Basically as good as can make current source/comparator

28 Wilkinson Clock Generation Strictly only 5 channels necessary 4x antenna, 1x reference channels Could interleave for twice depth, or multiple reference channels

Wilkinson Recording Start = start 0.5-1.

29 Wilkinson Recording Start = start GHz Clock Ripple counter (run as fast as can)

30 Wilkinson Clock Simulation Wilkinson Counter Rate Dependence Wilkinson Clock [GHz] Extracted Vdly Control Voltage [Volts] Better than 500MHz of FPGA (and at lower power) 1GHz would be nice, but only 30% faster

31 Simulated transfer encoding Works as expected

32 Output Bus Settling Time ~8.5ns (10-90%) ~100MHz bus operation should be possible

Project# 80350 (BLAB3) Wirebonding diagram MOSIS ID NOTE: pads 33, 63, 64, 97, 98, 128 are NOT bonded Design_number: 80350 Customer name: Univ.

33 Project# (BLAB3) Wirebonding diagram MOSIS ID NOTE: pads 33, 63, 64, 97, 98, 128 are NOT bonded Design_number: Customer name: Univ. of Hawaii Customer acct: 2105 Phone number: (808) Fax number: (808) Qty packaged: 0 Package name: LQFP128A Cavity size: 9.5mm x 9.5mm 9.5mm 7.62mm 5.82mm 9.5mm

34 Summary Leveraging IRS design effort ~0.4 GHz analog bandwidth All basic functionality simulates OK (with parasitics) Up to 100MHz bus readout rate (50MHz conservative) Am concerned about schedule Things will be much worse if doesn t work Could put in 128pin package Matters if will stud bond? Remaining concerns Optimal Write Address selection time Noise level on input Cost of stud bonding Others from today?

35 Upgraded detector -PID(π/Κ) detectors - Inside current calorimeter - Use less material and allow more tracking volume Available geometry defines form factor - Barrel PID Aerogel RICH 1.2m e - 8.0GeV 2.6m e + 3.5GeV

imaging TOP (itop) Concept: Use best of both TOP (timing) and DIRC and fit in Belle PID envelope Drawing by Marc Rosen(UH) BaBar DIRC Bars compatible (though thinner) with proposed TOP

36 imaging TOP (itop) Concept: Use best of both TOP (timing) and DIRC and fit in Belle PID envelope Drawing by Marc Rosen(UH) BaBar DIRC Bars compatible (though thinner) with proposed TOP counter Use new, compact solid-state photon detectors, new high-density electronics Use simultaneous T, θc [measuredpredicted] for maximum K/π separation Keep pixel size comparable to DIRC

37 Proposed Common Approach for Belle2

38 Baseline image block Top View 2x 64-channel PMTs per fiber link 7x BLAB3 daughtercards (112x BLAB3) 896 PMT channels/module (16 itop staves) 7 data, 7 trigger fiber pairs + HV power, LVDS RF clock, Revolution marker pairs

39 Baseline System Components Giga-bit Fiber Photo- Sensor Photo- Sensor BLAB3 BLAB3 BLAB3 BLAB3 MCP MAIN x4 FINESSE CARD x4 COPPER FIFO BLAB3 is 8 channels, each 32k samples deep <~1us to read out 32-samples hit/blab3 Total channel numbers presented previously unchanged, partitioned slightly differently

40 Hit Processing reminder 8 BLAB3 ASIC Trans-Imp Amps 512 x 64 samples Per channel BLAB3 sampling Assume: 100kHz charged track hits on each bar ~32 p.e./track (1% of 100ns windows) 30kHz trigger rate Each PMT pair sees <8> hits 240k hits/s Each BLAB3 has an average occupancy <1 hit (assume 1) 400ns to convert 256 samples 16ns/sample to transfer At least 16 deep buffering (Markov overflow probability est. < ) Fast conversion Matrix (x256) Improvements based upon Lessons learned from BLAB2 Each hit = 64samples * 8bits = 512bits ~125Mbits/s (link is 3.0 Gb/s ~ x30 margin) Plan to model in standard queuing simulator, but looks like no problem (CF have done same exercise with Jerry Va vra for 150kHz L1 of SuperB and can handle rate)

41 Context: BLAB2 & PD scale readout Initial Target: New f-dirc Readout System Really reached on specs Gen. 0 Prototype (LAB3)

42 BLAB2 Lessons RGC (Regulated Cascode) Fussy doesn t look like 50Ω for large voltage signals Not enough phase margin (oscillates) Sampling nmos/pmos does NOT work Alignment between sampling rows Overall timing alignment troublesome Better with fewer distinct samples, yet having more buffer depth

43 Experiment 2: 13-Mar-09 (~9 mo.) 448 channels readout at SLAC + few hundred UH [HI-TIDE] Learning about big system timing issues Experiment 3: winter (~6+ mo.) BLAB3 ASIC upgrade (lessons learned) At speed fast feature extraction

44 1kΩ TIA Sim ~405MHz analog bandwidth

45 2kΩ TIA Sim ~400MHz analog bandwidth

46 5kΩ TIA Sim ~350MHz analog bandwidth

47 10kΩ TIA Sim ~300MHz analog bandwidth

48 20kΩ TIA Sim ~245MHz analog bandwidth

49 50kΩ TIA Sim ~170MHz analog bandwidth

50 100kΩ TIA Sim ~130MHz analog bandwidth

51 3kΩ TIA, bias current sims ~130MHz analog bandwidth

52 3kΩ TIA, bias current sims ~200MHz analog bandwidth

53 3kΩ TIA, bias current sims ~300MHz analog bandwidth

54 3kΩ TIA, bias current sims ~370MHz analog bandwidth

55 3kΩ TIA, bias current sims ~420MHz analog bandwidth

56 3kΩ TIA, bias current sims ~450MHz analog bandwidth

57 3kΩ TIA, bias current sims ~450MHz analog bandwidth

58 3kΩ TIA, bias current sims ~450MHz analog bandwidth

Ice Radio Sampler (IRS) & Buffered LABRADOR #3 (BLAB3) Preliminary Specification Review. Gary S. Varner Internal ID Lab Review, 10 AUG 09

Ice Radio Sampler (IRS) & Buffered LABRADOR #3 (BLAB3) Preliminary Specification Review Gary S. Varner Internal ID Lab Review, 10 AUG 09 Goals for both ASICs Confirm Design Specifications Table Listing