Large Analog Bandwidth Recorder and Digitizer with Ordered Readout (Perf, Results)

Transcription

1 Large Analog Bandwidth Recorder and Digitizer with Ordered Readout (Perf, Results) Gary S. Varner University of Hawai i U Chicago Precision Timing Mtg Dec.07

2 Topics Background to WFS Development Antarctic Impulsive Transient Antenna (ANITA) LABRADOR ASIC 6GSa/s ~11ps Improved Performance Super Flavor Factory PID Buffered LABRADOR (BLAB) Technique Limits Streak Camera/Precision Timing Next Gen ASIC

3 Ice RF clarity: 1.2 km(!) attenuation length The ANITA Concept Typical balloon field of regard ~4km deep ice! Effective telescope aperture: ~250 km ev ~10 km 3 sr ev (Area of Antarctica ~ area of Moon)

4 ~7m Antarctic Impulsive Transient Antenna (ANITA) A demanding Application ~320ps Measured RF Transient (impulsive) Events ( MHz) GSa/s Completely solar powered (tight demands on power, few hundred W total) Sounds almost like a joke

5 Major Hurdles these ν are elusive No commercial waveform recorder solution (power/resolution) 3σ thermal noise fluctuations occur at MHz rates (need ~2.3σ) Without being able to record or trigger efficiently, there is no experiment

6 STRAW2 Chip 16 Channels of 256 deep SCA buckets Optimized for RF input Microstrip 50Ω Target input Bandwidth: >700MHz Record length: ns DACs Self-Triggered Recorder Analog Waveform (STRAW) 8192 analog storage cells 32x256 SCA bank Trigger ADC Self-Triggering: -LL and HL (adj.) for each channel -Multiplicity trigger for LL hits On-chip ADC: 12-bit, >2MSPS Sampling Rate: 1-3GSa/s (adj.) Sampling Rates >~4GSa/s possible w/ 0.25μm process External option: MUXed Analog out Die:~2.5mm 2 scalers

7 STRAW1 STRAW2 Trig Comb. Sampling LABRADOR2 STRAW3 GLUE LABRADOR Intelligent Design? SHORT2 SATURN LABRADOR3

8 9 x 260 samples = 2340 storage cells LABRADOR(3) architecture 4 RF inputs timing control 5 RF inputs SCA bank: 4 rows x 260 columns 12 Wilkinson ADC Convert all 2340 samples in parallel, transfer out on common 12-bit data bus SCA bank: 5 rows x 260 columns tail samples

9 Large Analog Bandwidth Recorder and Digitizer with Ordered Readout [LABRADOR] Straight Shot RF inputs Switched Capacitor Array (SCA) Massively parallel ADC array Similar to other WFS ASICs analog bandwidth 8+1 chan. * samples Common STOP acquisition 3.2 x 2.9 mm Conversion in 31μs (all 2340 samples) Data transfer takes 80μs Ready for next event in <150μs Random access:

10 XOR Look-ahead logic (sample on rising/falling edge) Sampling rates up to 4 GSa/s with voltage overdrive LABRADOR Sampling Speed 2.6GSa/s

11 SURF #5 Pedestal and Pedestal Stability AC coupled input ΔT = 17C (δt ~ 24hours) ~0.052mV/C

12 Wilkinson ADC No missing codes Linearity as good as can make ramp Can bracket range of interest Run count during ramp LABRADOR Digitization 12-bit ADC Excellent linearity Basically as good as can make current source/comparator Comparator ~ V; 133MHz GCC max (~31us)

13 Sampling Rate Temperature Dependence Qualitative agreement obtained in SPICE

14 LABRADOR (SURF board) Noise 1.3mV 10 real bits (1.3V/1.3mV noise) (2.5V VDD, rails smaller) Ch.9 Vped noise

15 Bandwidth Limitations (LAB1 example) f 3dB = 1/2πZC LAB3 move R term to front For 1.2GHz, C <~ 2pF (NB input protection diode ~10pF) Minimize C, (C drain not negligible x260)

16 Transient Impulse FFT Difference Bandwidth Evaluation f 3dB ~> 1.2GHz Frequency [GHz]

17 Response for RF Signals 2.6 GSa/s, peak fit boardlevel noise interference)

18 Cross-talk Amplitude 4 RF inputs timing control 5 RF inputs SCA bank: 4 rows x 260 columns SCA bank: 5 rows x 260 columns Qualitative agreement obtained in SPICE

19 Cross-talk Phase 4 RF inputs timing control 5 RF inputs SCA bank: 4 rows x 260 columns SCA bank: 5 rows x 260 columns Qualitative agreement obtained in SPICE

20 Timing Calibration Constants T 0!= T 1!= ½ T Separate wrap time constants Need to determine Phase 0, 1 interleaving In general every Δt0, Δt1 different

21 Timing Calibrations (1) High-low!= Low-high Wrap-around time difference

22 600MHz Clock Timing Calibrations (2) 384.6ps nom. Bin-by-bin

23 MC study of Calibration Technique Estimated Limit

24 Jiwoo Nam UC Irvine

25 Ground pulser Calibration with Realistic Signals Bore hole pulser Ice 80m thick and messy Dipole

26 Validation data: borehole pulser RF Impulses from borehole antenna at Williams field Detected at payload out to km, consistent with expected sensitivity Allows trigger & pointing calibration

27 SURFv3 Board Flies in space all components heat sunk Programming/ Monitor Header J4 to TURF LAB3 (SURF = Sampling Unit for RF) (TURF = Trigger Unit for RF) J1 to CPU RF Inputs Trigger Inputs Timing Calibrations!

28 ~47ps due to Time Ref. Passing (33MHz clock) Jiwoo Nam Natl Taiwan U.

29 After full calibration 100 s km downrange

30 If simply scale: 35cm 350nm (10 6 ) 40ps 40as! Why doesn t this work? BW 1GHz 1PHz N γ ~ Infty. Anyway, only talking about factor 40 Photonics in its infancy direct O-O

31 oscilloscope on a chip High Speed sampling 2 GSa/s, 1GHz ABW Tektronics Scope 2.56 GSa/s LAB Sampling speed Bits/ENOBs Power/Chan. LABRADOR GSa/s 12/9-10 <= 0.05W Commercial 2 GSa/s 8/ W Cost/Ch. $10 (vol) > 1k$

32 Deeper sampling Desired for Extensive radio array for UHE neutrino PID Upgrade precision timing ev νμ ~2 km

33 Buffered LABRADOR (BLAB1) ASIC Single channel 64k samples deep, same SCA technique as LAB, no ripple pointer Multi-MSa/s to Multi- GSa/s 12-64us to form Global trigger 3mm x 2.8mm, TSMC 0.25um Arranged as 128 x 512 samples Simultaneous Write/Read

34 Buffered LABRADOR (BLAB1) ASIC 10 real bits of dynamic range, single-shot Measured Noise 1.45mV 1.6V dynamic range

35 BLAB1 Sampling Speed Can store 13us at 5GSa/s (before wrapping around) 200ps/sample Single sample: 200/SQRT(12) ~ 58ps But, have Complete Waveform Information

36 BLAB1 Analog Bandwidth -3dB ~300MHz A few fixes (lower power, higher BW) Multi-channel: BLAB2 (16), TARGET (16 w/ gain), LARC (32) and PrX

37 voltage (mv) Typical single p.e. signal [Burle] Overshoot/ringing Using RF Amplifier System (~43dB gain) time (ns)

38 Temperature Dependence Sample 6GSa/s aperature (172ps = 5.8GSa/s) 0.2%/degree C (can correct) Matches SPICE simulation Even better, can delay lock

39 400MHz sine wave Calibration (1) Linear variation across chip Due to IR drop in feed voltage (can be improved) Storage Cell Number 6GSa/s Extracted Period [ns]

40 400MHz sine wave Calibration (2) 6GSa/s After basic linearity and bin-by-bin correction ~11ps intrinsic (~8ps possible) 15ps Linearity only Extracted Period [ns]

41 ~30ns pulse pair 6GSa/s 30ns Bench Test timing ~27ps for two edges ~20ps for each edge

42 Temperature Dependence Sample 6GSa/s aperature (172ps = 5.8GSa/s) 0.2%/degree C (can correct) Matches SPICE simulation

43 Courtesy: J. Buckley (Wash U. St. Louis) BLAB2 Initial Target: New f-dirc Readout System Gen. 0 Prototype (LAB3) Target Submission: Feb. 11, 2008

44 Interleaved Operation Single shot uncalibrated room for improvement push BW higher LARC ASIC: 64 5 GSa/s = 384GSa/s Streak camera type applications ps timing If jitter due to random noise, more samples better

45 Courtesy: J. Va vra (SLAC) Limitations 1: Analog Bandwidth Difficult to couple in Large BW (C is deadly) At what point stop getting useful information? f 3dB = 1/2πZC

46 voltage (mv) Limitations 2: Interpolation Error Tied to Bandwidth Issue Is 10 samples/ns along leading edge enough? Need 100:1 interpolation for 1ps And aperature jitter at < 1ps time (ns)

47 T0 [ns] Limitations 3: Systematic Errors Experience with running Belle TOF System for ~ a decade Any jitter/shift/jump in reference time is fatal? (differential measurements) Experiment ps jump! T0 [ns] T0 [ns] Experiment 19 Run number Run-by-run T 0 Run number

48 Limitations 4: Leakage Current Need small C for Input Coupling Can Improve? (readout faster)

49 Limitations 5: ktc Noise Need small C for Input Coupling

50 Summary Exciting Stuff! 30ps (PET) seems quite feasible without TDC (fast discriminator) Timing Systematics! 1ps resolution, need to pull out all of the stops

51 Back-up slides

52 600MHz sine and 2.6GSa/s well matched Difference from Exact zero-crossing time [ns] 10ps difference typ. (ideal) Sine amplitude Sine amplitude Zero crossing comparison Time [ps] Zero crossing comparison Time [ps] 600MHz sine LAB3 600MHz sine LAB3

53 600MHz sine and 2.6GSa/s well matched Positive ½ cycle ~11ps difference typ. (ideal) Difference from Exact Period time [ns]

54 Using Ideal Extraction Use both ½ cycles ~5ps difference typ. (ideal bins) Extracted Bin Width [ns]

55 Running Average converges very quickly Use both ½ cycles ~5ps difference typ. (ideal bins) Bin Sample Number Estimated Bin Width [ns]

56 Running Average converges very quickly Due to input function, Convergence not 1/sqrt(n) Error on Bin Width [%] Bin Sample Number

57 However, when input +/- 10% bin scatter Fast convergence, but with offsets Error in Bin Width [ns] Number of Samples in Bin

58 Impact on estimation (+/- 10% true difference) Difference from Actual Bin Width [ns] About <bin> ~19ps Difference from true Width, referenced to mean [ns]

59 Data: Bin-by-bin Calibration Constants ~34 ps RMS Bin width in Calibration File [ps]

60 General trend larger intrinsic spread [+/- 10% flat] Determined bin width including error [ns]

61 Consider Slightly larger input spread [+/- 15% flat] 36ps [MC] vs. 34ps [data] Data Determined bin width including error [ns]

62 However, the errors are non-negligible Sqrt(36^2-28^2) ~ 24.8 ps Difference from True Bin Width [ns]

63 Cross-check: BLAB1 ASIC Brute Force occupancy method 100k Events 6.0 GSa/s

64 Cross-check: BLAB1 ASIC Brute Force occupancy method 100k Events 6.0 GSa/s Same TSMC Process as LAB3 General slope Across ASIC (expected) SCA Sample number (512 per row)

65 6GSa/s 125MHz sine wave Pre-calibration

66 ANITA Payload

67 ROBUST TRACR DOM-MB Metal Plate Sealing the DRM Antennas DRM electronics Surface Test Metal can /w electronics