ANITA-Lite Trigger Object (ALTO Rev. B) User s Manual

Transcription

1 ANITA-Lite Trigger Object (ALTO Rev. B) User s Manual Gary S. Varner, David Ridley, James Kennedy and Mary Felix Contact: varner@phys.hawaii.edu Instrumentation Development Laboratory Department of Physics and Astronomy, University of Hawaii at Manoa 16 June 2003 ABSTRACT This document serves as an introduction and handbook to use of the dedicated trigger for the ANITA-Lite test flight. The major changes in Revision B of the trigger board were the addition of RF VETO functionality and a settable delay of the RF trigger signals to allow time for forming a VETO signal. In addition, provision was made for the injection of a TTL one pulse per second (1PPS) signal from the on-payload GPS. Output plots are provided of the trigger levels and RF power sensitivity. Keywords: ANITA-lite, RF triggering, VETO 1. Theory of Operation The ANITA-lite experiment is intended as a Radio Frequency background survey in advance of the ANtarctic Impulsive Transient Array [1]. Triggering on band-limited impulsive transients, such as those from the desired Askaryan effect [2] events, requires a dedicated triggering system. In order to meet the goals of the background flight sampling, an object with the attributes listed below is required. Based upon these design requirements, a conceptual prototype for the ANITA-Lite Trigger Object (ALTO) was fabricated in January of During the process of testing this first version (Rev. A) of the ALTO board, additional features and constraints from concurrent operation with the TIGER [3] payload mandated additional design features, culminating in a 2 nd board revision, Rev. B. Required design features for the ALTO Rev. B board: Operation of 4 RF antenna inputs at the thermal noise limit over the GHz BandWidth (BW) Ability to trigger on band-limited transients Provision for a VETO antenna input Computer controlled RF trigger and VETO thresholds Continuous monitoring of the RF input power Low power, fast triggering Synchronization with GPS once-per-second (1PPS) timing marker Muli-level analog output to allow Multiplicity selection in the Acqiris [4] digitizer module Instantaneous and averaged Livetime monitoring

2 Figure 1 outlines the functional blocks of the ALTO Rev. B board. RF antenna inputs with approximately 70dB of upstream gain are presented to the ALTO from the left. The key trigger output to the Acqiris digitizer cards is at the center on the right. An Acromag [5] cpci module provides Digital-to-Analog Converter (DAC) outputs to control the comparators for the four RF and single VETO inputs. Because band-limited RF pulses from the quad-ridge horn antennas can have very fast transient characteristics, diode detector modules are used to convert the input signal into a pulse upon which the discriminators can operate effectively. In order to efficiently set the threshold at an optimal setting above noise, monitoring of the RF input power is performed using a so-called bias-tee circuit. The output from the bias-tee is amplified and sent to an ADC module in the Acromag carrier card. This ADC also monitors the 1 second averaged Livetime signal. Digital control/disabling of the VETO and 1PPS inputs are implemented through the VETOMASK and 1PPSDIS TTL inputs, respectively. These inputs are controlled via the Acromag Digital I/O IP module. To prevent re-triggering or to disable the trigger during initialization and prolonged bursts, a digital HOLDOFF input is provided to allow for such functionality via the same Acromag digital I/O interface. While the analog Livetime is a convenient averaged sum of the livetime (or inversely the VETO deadtime), a TTL copy of the VETO signal is provided to allow polling to determine whether the VETO is active at any specific instance in time. Finally, as a functionality check, the 1PPS signal is echoed from the ALTO as 1PPSMON for inspection of proper GPS operation. Figure 1: A block diagram of the ALTO Rev B circuit. While individual channel noise rates may be quite high, requiring a muli-fold coincidence should significantly reduce the accidentals trigger rate. Requiring such a coincidence is unlikely to significantly impact true signals or coherent impulsive backgrounds.

3 Table 1 is a summary of all the input and output signals for the ALTO Rev. B board. The DAC outputs to the ALTO are routed through the DAC INTerface breakout board (DINT), which is connected via a Centronics-to-SCSI-2 cable to an Acromag TRANS-C200 transition module which interfaces through the cpci backplane J4 and J5 connectors to the Acromag 8625 IP carrier module. Four horn antennae and one VETO discriminator thresholds are set from these DACs. The trigger signal itself is a 4-level analog signal and is fed to the external trigger input of the Acqiris module. A trigger level multiplicity select is set by choosing a threshold as per the series of curves shown in Figure 2, which also illustrates the output width currently established. This width can be adjusted by changing a resistor on each RF channel. Monitoring of the received RF power and Trigger Livetime is done by digitizing analog values routed through the ADC INTerface breakout board (AINT), which is connected via a Centronics-to-SCSI-2 cable to another port on the Acromag TRANS-C200. This port corresponds to another IP module location on the Acromag ADC measurements of the bias-tee amplified outputs may be correlated to an RF received power as per the transfer curves displayed in Figures 3 and 4. Monitoring of the ALTO livetime (or correspondingly the VETO deadtime) is done by sampling the 1 second average integral of the VETO duty cycle. This Livetime transfer curve is shown in Figure 5. Digital control and monitoring of the ALTO VETO and 1PPS signals is implemented by means of an Acromag IP470, which has a Logical INTerface breakout module (LINT) of the same interface as per others above. Table 1 details the no connect (n.c.) behavior of these signals and their active states. Table 1: Signal definitions for the ALTO Rev. B board. Input Output Name Type Source/Desination Comments RF1 analog horn 1 RCP 90 degree hybrid RF2 analog horn 1 LCP combinations RF3 analog horn 2 RCP 90 degree hybrid RF4 analog horn 2 LCP combinations VETOANT analog VETO Antenna mix sum of external VETO antennae THR1 analog Acromag IP220 (DINT) RF1 threshold THR2 analog Acromag IP220 (DINT) RF2 threshold THR3 analog Acromag IP220 (DINT) RF3 threshold THR4 analog Acromag IP220 (DINT) RF4 threshold VETOTHR analog Acromag IP220 (DINT) VETO threshold VETOMASK digital Acromag IP470 (LINT) Disable VETO, active LOW (n.c. = VETO active) HOLDOFF digital Acromag IP470 (LINT) Trigger Holdoff, active HIGH (n.c. = no Holdoff) GPS1PPS digital GPS unit (TTL out) 1-2ms width, active high, leading edge timing TTL 1PPSDIS digital Acromag IP470 (LINT) Disable 1PPS, active LOW (n.c. = 1PPS enabled) DC1 analog Acromag IP320 (AINT) RF1 power, see Figs. 3 & 4 for transfer curves DC2 analog Acromag IP320 (AINT) RF2 power, see Figs. 3 & 4 for transfer curves DC3 analog Acromag IP320 (AINT) RF3 power, see Figs. 3 & 4 for transfer curves DC4 analog Acromag IP320 (AINT) RF4 power, see Figs. 3 & 4 for transfer curves TRIG analog Acqiris digitizer card TRIGGER output signal, see Fig. 2 for levels LIVE analog Acromag IP320 (AINT) LIVEtime monitor, see Fig. 5 for transfer curve 1PPSMON digital Acromag IP470 (LINT) GPS 1PPS monitor VETO digital Acromag IP470 (LINT) Instantaneous VETO signal monitor

4 Preliminary testing of all of the functionality for the ALTO Rev. B board has been performed and demonstrated to work in representative plots below. Figure 2 illustrates the output response of the ALTO Rev. B to the four possible trigger input conditions. The trigger multiplicity may be set in 100mV steps below ground. Receipt of the 1PPS signal outputs a level 4 trigger value. Figure 2: Multi-level trigger output response to the Acqiris. Multiplicity selection of the four trigger levels may be done with approximately 100mV offset steps. 2. RF Sensitivity Optimum tuning of the performance of the trigger requires understanding of the corresponding received power upon which to feed back the trigger thresholds and thereby the rate. Using a noise diode as an RF power source and a Minicircuits amplifier, a series of RF power input points were measured, as may be seen in Figures 3 and 4. On the left side of Figure 3 is seen the power value as measured with a spectrum analyzer utilizing 1MHz frequency bins. On the right of the same Figure is seen the same curve when multiplied by an effective 1GHz bandwidth. Figure 4 helps illustrate that the received power follows an exponential function nicely over almost 30dB of dynamic range. Note that at the low received power end, the corresponding quantization of the 12-bit ADC becomes noticeable. Introducing a VETO circuit is always a matter of careful consideration. Given the expected large and potentially rapid period of nearby noise sources, it is necessary to include such functionality. However to prevent becoming continually blind, a Livetime monitor has been added. The monitor voltage as a function of Livetime is illustrated in Figure 5.

5 Figure 3: Output response vs. Input power. On the left, the 1MHz BW power as measured at 600MHz with an HP8560E Spectrum Analyzer; on the right, the corresponding curve into an estimated 1GHz total BW. Figure 4: Logarithmic response of the ALTO Rev. B DC power output, indicating at least some sensitivity over almost 30dB of RF power input.

6 Figure 5: Livetime response curve with 1 second averaging. All other digital functionality has been measured and determined to function as per design. There are two values of note in the current configuration of the board. First there is the choice of width of the VETO tail. This is currently set so that the VETO remains active for 200ns after the termination of VETO input stimulus. The other parameter is the delay applied to the RF signals to allow for generation and application of the VETO in advance of the arrival of the RF signals. This delay is currently set to 50ns. Both of these widths may be rather trivially changed by swapping the resistors used in simple R-C circuits as may be found in the Appendix. Power dissipation during initial operation is 132mA of +12V and 88mA of 12V or about 2.64W. 3.Board Layout and Packaging The conserve space, provide an RF-shielded environment and make the machining as simple as possible, the form-factor as seen in Figure 6 was adopted. One advantage of making the board compact was to limit the length of impedance controlled traces or, rather, minimize their detrimental impact in the event of any impedance mis-match.

7 Figure 6: Photograph of the ALTO Rev. B board, with silkscreen indicating the location of the signals mentioned above. SMA connectors mount on the bottom side of the board, allowing access to test points when the cover is removed. The ALTO Rev. B board is packaged inside an RF-shielded housing as shown in Figure 7. The choice of vertical SMA was made to facilitate ready access to signals when opened as well as greatly simplify machining and assembly.

8 Figure 7: Photograph of the ALTO Rev. B board in its ALTOREVB housing, with the various signals and power connections implemented in SMA connectors and labeled accordingly.

9 4.References 1. ANtarctic Impulsive Transient Array proposal P.W. Gorham, D.P. Saltzberg, P. Schoessow, et al., Radio-frequency measurements of coherent transition and Cherenkov radiation: Implications for high-energy neutrino detection, Phys. Rev. E 62, 8590 (2000); D. Saltzberg, P. Gorham, D. Walz et al., Observation of the Askaryan Effect: Coherent Microwave Cherenkov Emission from Charge Asymmetry in High Energy Particle Cascades, Phys. Rev. Lett. 86, 2802 (2001). 3. The Trans Iron Galactic Element Recorder (TIGER) experiment The 2-4GSa/s, 1GHz analog bandwidth cpci module, Acqiris DC The Acromag corporation produces a wide product line of PCI I/O modules: 5. Appendix Complete schematics for the ALTO Rev. B board are appended below. The design is hierarchical, with the page numbers of underlying schematics indicated on the symbols above. This ECO annotated version is dated 16-JUN-03 and supercedes any previous versions. Any version found dated later than this will supercede those included.

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