S4 OPERATION DESCRIPTION IN PAMELA INSTRUMENT

Transcription

1 For internal use only S4 OPERATION DESCRIPTION IN PAMELA INSTRUMENT 1

2 1. DESTINATION The bottom detector S4 of PAMELA instrument is intended for: choice of useful events by energy deposition in S4 detector proportional to number of shower particles escaping imaging calorimeter; participation in the elaboration of the first level trigger for starting the read out of information from subsystems of PAMELA instrument by means of sending to TRIG system of PAMELA instrument the signals corresponding to exceeding of three thresholds of pulse amplitude discriminators (ТН1 corresponds to threshold mip, ТН2 corresponds to threshold 50 mips and ТН3 corresponds to threshold mips (I/F-4, Appendix 1). Bottom detector S4 of PAMELA instrument elaborates: Analog signal proportional to energy deposit inside scintillator for the second level trigger and transmission to the ground for future treatment (Interface I/F-3, Appendix 1.); The mark signal for the second level trigger and transmission to the ground for future treatment (Interface I/F-4, Appendix 1.). Bottom detector S4 of PAMELA instrument realizes: - the acquisition of code corresponding to threshold TH3 value from ТС&ТМ system of PAMELA instrument PSCU and the installation of it inside the S4 detector discriminator unit (Interface I/F-5, Appendix 1.); - carrying out of on board tests of S4 by means if internal generator and light emission diodes with every reception of control signal from PSCU PAMELA instrument (Interface I/F- 6, Appendix 1); 2

3 - switching to spare electronics set of S4 with power supply of low voltage to the corresponding set (Interface I/F-1, Appendix 1); - switching of S4 with power supply of high voltage (Interface I/F-2, Appendix 1); - Elaboration of signal STATUS for operative checking of S4 work going to PSCU (Interface I/F-7, Appendix 1). 3

4 2. FUNCTIONING The bottom detector S4 of PAMELA instrument has three operating modes. - Data acquisition mode; - Calibration; - Threshold setting Data acquisition mode S4 is detecting the charged particles and produce three threshold signals for PAMELA instrument TRIG system (main and spare depending on operating set (see Appendix 2) and one analog signal (main or spare) going to ADC of PAMELA TOF system (Appendix 3) and as well as STATUS signal (main or spare, Appendix 4) of S4 capacity for work. After the first level trigger signal is elaborated these data are wrote into the Format S4 (see Appendix 7) and are transmitted to the ground. STATUS signal is elaborated when all tensions supplies S4 by the main set of electronics which means (main LVDS low level) the normal capability of operation. This signal is sent to PSCU of PAMELA. It check it every 3 minutes. With error detection (main LVDS high level) PSCU has to switch S4 low voltage power supply for spare kit and continue to checking of spare STATUS signal each 3 minutes Calibration. Once a day or by command from the Earth the calibration of S4 has to be made. The calibration can be stand alone or during all subdetector calibration (Commands see Appendix 5). The calibration is carried out by following way. 4

5 256 control go to S4 from PSCU of PAMELA instrument by main or spare lines (I/F-6, Appendix 6). The control signal parameters are not agreed. There have to be agreed: - polarity - amplitude - duration - rise time - frequency not more then 10 кhz. During the Calibration mode the first level trigger of PAMELA instrument is locked (PAMELA instrument does not detect particles). The times of beginning and of the end of calibration are fixed in output formats of PAMELA instrument. By receiving of control signal the LED generator (main or spare) produces the pulse provided the stable light bursts of LEDs. At the output (main or spare) the analog signal arises, which is sent to the input of ADC (main or spare) of TOF system and code corresponding to its amplitude goes to from TOF system to PSCU memory through SWB and is written into the S4 format (Appendix 7). Analog signal is sent in parallel to three discriminators (main and spare) And logic signals from S4 outputs (I/F 4) are sent to TRIG system and the marks of exceeding ( 1 ) or not exceeding ( 0 ) are written into format S4 (Appendix 7). As a result the 256 formats are generated and transmitted to the ground for data treatment. After calibration finish S4 is ready to registration mode Threshold setting This mode is switched on by on ground command (commands see Appendix 5). By this command the threshold value is transmitted by serial way from TC&TM unit of PSCU PAMELA/ This code is 5

6 transformed inside S4 into the voltage level defining the threshold range mips (1 bit 2 mip) (I/F 5. Appendix 8). This interface is implemented by 6 twisted pare lines (3 mains and 3 spare) The time of threshold installation is not more then 128 mcs. The time of threshold installation and its value are written down into the data format of S4 (Appendix 7). 6

7 3. ORDER OF S4 SWITCHING ON AND OFF S4 is switching on by following way. By the command from the ground (see Appendix 5) PSCU: 1. In 1 s switch on main (or spare) low voltage power supply ±5,6 V (I/F-1, Appendix 10). 2. switch on main (or spare) high voltage power supply (I/F-2, Appendix 9). In case of necessity of high voltage switching from main to spare source (or vice versa) PSCU sends the following commands (see Appendix 5): 1. switching off high voltage power supply; 2. switching off low voltage power supply; 3. switching on spare (main) low voltage power supply source. 4. switching on spare (main) high voltage power supply source; The switching of are implemented by following way sending commands: 1. switching off high voltage power supply. 2. switching off low voltage power supply; 7

8 3. TEST OF S4 For permanent checking of detector S4 operation the signal STATUS serves elaborated by main (spare) electronics set. This signal is of LVDS standard. Low level corresponds to normal operation of S4 and high one to failure. The signal is sent to PSCU of PAMELA (I/F-7, Appendix 4). 8

9 Appendix 1. Scheme of S4 connections in PAMELA instrument STRUCTURAL LVPS ±5,6 main ±5,6 spare I/F 1 XS2 PC19 HVPS 800v main 800v spare I/F 2 XS1 S4 TOF ACD main ACD spare I/F3 Analog main Analog spare XS4 XS3 TRIG LOGIC main LOGIC spare I/F 4 TH1 main TH2 main TH3 main TH1 spare TH2 spare TH3 spare XS5 TC&TM I/F 5 main spare PSCU (CPU) 256 форм? I/F 6 TR main TR spare XS6? I/F 7 STATUS main STATUS spare 9

10 Appendix 2. Logic Signals I/F-4. PROTOCOL 03/007 of interface agreement 1. Structural scheme LOGICAL SIGNALS TRIG System main CPU TRIG System spare 0,4 mip 50 mip mip STATUS STATUS 0,4 mip 50 mip mip S4 main S4 spare 2. Signals are elaborated in standard LVDS (duration100±50 ns, for threshold signals only) 3. Signals of thresholds go to TRIG system. 4. Signals STATUS go to CPU and has low level when all voltages correspond to specified values and high level when one or more tension values have no normal level. Logic signals ТН1, ТН2 and ТН3 main and the same three spare ones (6 all) arrive into main and spare TRIG system correspondingly. The connectors are nit defined in TRIG system. In S4 there is connector XS5, type PС19 (see connection scheme, Appendix 11). Cable is fabricated by INFN. Connector РС19 is delivered by MEPhI. 10

11 Appendix 3. Analog Signal PROTOCOL of interface agreement ANALOG SIGNALS 1. There are main and spare outputs of analog signals. 2. The analog signals goes to ADC s 3. Structural scheme I/F-3. ADC main Main S4 Technological output ADC spare Spare S4 Technological output 4. The analog signal is positive with amplitude proportional to charge. 5. Rise time is not more then 100 ns. 6. Decrease time near 1 µs. 7. Maximum amplitude corresponding to 500 mip is +5 V. 8. Beginning of output signal coincides in time with logic signal 0,4 mip. 9. Requirements to ADC Input impedance Rin 10 kohm Maximum amplitude of input signal 5 V. ADC for analog signals are ADC of TOF system. ADC main and ADC spare are connected with main and spare outputs of S4 analog signals. Types of connectors in TOF are not defined. S4 connectors XS3 and XS4 of LEMO type (see connection scheme, Appendix 11) Cables are fabricated by INFN. 11

12 Appendix 4. STATUS signal. I/F-7. Main and spare signals are fed to PSCU of PAMELA (connection scheme, Appendix 11). Unit of accepting is not defined. Connector on this unit is not defined. Cable is fabricated by INFN. S4 connector XS6 of РС19 type is delivered by MEPhI. 12

13 Appendix 5. Macrocommands for S4. Feed from ground through Resurs CPU and PAMELA CPU: 1. Switch ON ±5,6 V main, switch OFF spare. 2. Switch ON ±5,6 V spare, switch OFF main. 3. Switch OFF ±5,6 V main and spare. 4. Switch ON high voltage power supply main, switch OFF spare. 5. Switch ON high voltage power supply spare, switch OFF main. 6. Switch OFF high voltage power supply main and spare. 7. Set S4 threshold (includes time of setting and value of threshold). 8. Calibration of S4. 9. Calibration of PAMELA instrument. 13

14 Appendix 6. Control signal interface. The control signals are fed to S4 during calibration mode by main and spare lines. The number of signals is 256 in one session of calibration. 1. Frequency not agreed; 2. Polarity not agreed; 3. Amplitude not agreed; 4. Rise time not agreed; 5. Duration not agreed; 6. Decrease time not agreed; 7. Load not agreed. The control signals are fed by twisted pare. Unit in PAMELA is not defined. The connector is not defined. S4 connector XS6 of PC-19 type (see connection scheme, Appendix 11). Cable is fabricated by INFN. The connector is delivered by MEPhI. 14

15 Appendix 7. S4 format of information. S4 detector information is transmitted to the ground by S4 format which contained: 1. Syncroword (S4) 16 бит 2. Time of event (or number) 32 бит 3. Time of calibration termination 32 бит 4. Main (spare) high voltage power supply 1 бит 5. Main (spare) low voltage power supply 1 бит 6. Mode of work (registration or calibration) 1 бит 7. The type of the first level trigger (PAMELA or ND) 1 бит 8. The value of threshold 8 бит 9. The time of threshold setting 32 бит 10. Analog signal amplitude 8 бит 11. ТН1 state 1 бит 12. ТН2 state 1 бит 13. ТН3 state 1 бит 14. Last STATUS state 1 бит 15. End of format 8 бит ВСЕГО 144 бит 15

16 Appendix 8. Code threshold transmission I/F-5. The code is transmitted by serial form by three lines ML-ADRS, ML-CLOCK and ML-DATA (main three and spare three) The Memory Load command transfers a 16 bit data word, in serial form, from TC&TM Module of PSCU to S4. The interface concepts adopted is based upon the following: Address lines: the ТС&TМ Module provides a set of address lines, i.e. S4 is provided with a dedicated address lines (main and spare). Clock line: clock pulses are provided continuosly and simultaneously to all the users including S4. Sixteen of these clock pulses are gated during the address (sampling) signal interval, together with the 16 bit data. thus enabling S4 to read the data. The clock pulse have a known and reliable phase relationship with the NRZ-L data transitions, this ensuring reliable data read-in by the S4. Data line: the ТС&TМ Module delivers the data (16 bit NRZ-L) to all users connected to it including S4. Selection of S4 is performed by asserting the relevant S4 (main or spare) address line. S4 receives the interface signals (data, clock and address signals) on dedicated differential lines Main and spares. The sampling signal is active (low) only on the addressed channel. Upon receiving data S4 doesn t acknowledge the information. The clock provided by this block is different from the clock signals provided by the Serial Digital Acquisition block; all the clock signals are 16

17 delivered to the user in parallel, even if the ТС&TМ Module is not transmitting/receiving data. SIGNAL WAVEFORM DIAGRAM SAMPL = Memory load address signal to S4 CLOCK = ML Transfer clock signal to S4 ML-16 = ТС&TМ Module serial output to S4's decoder (D15 is the MSB and is transmitted first). Memory Load data is changed on the rising edge of the transfer clock signal. Transmission frequency Description Value t 1 Serial digital acquisition time 128 мкс t 2 t 4 - t нс t 3 Bit time 8 мкс t 4 Half bit time 4 мкс t 5 Last clock to ML address 200 нс t 6 ML address - to first clock 3,8 мкс ML Drivers are of 26НС31 The word has 16 bits. Connector on ТС&TM is not defined. Connector on S4 is XS6 of РС19 type (see connection scheme, Appendix 11. Cable is fabricated by INFN. Connector is delivered by MEPhI. 17

18 Appendix 9. HVPS interface PROTOCOL 01/007 of interface agreement I/F-2 HIGH VOLTAGE INTERFACE 1. S4 uses power supply source: main and spare switched by command. 2. Outputs of power supplies are connected inside power supply system.. 3. S4 has one input. 4 Structural scheme: Main& spare Power supply V one line + S4 5. Polarity: minus 6. Voltage: V 7. Exactness of face-value arrangement: ± 1В. 8. Amplitude of ripples: 100 mv 9. Instability with all destabilizing factors 0,3% 10. Switching ON and OFF: monotonely, with < 500 V/s 11. Maximum consummation current, power: for -800 V 1 ma 0,8 W The main and spare power supplies are the part of power supply system of PAMELA instrument and is switched by PSCU with commands from the ground. Its outputs are connected by defense diodes and connection point (output) is linked with S4 by cable. Connector on S4 is XS1 (see connection scheme, Appendix 11). Output connector on the PAMELA power supply unit is not defined. Cable is fabricated by INFN. Output voltage is set before connection with S4 in range V. The exact value one takes in S4 certificate. 18

19 Appendix 10. LVPS interface PROTOCOL 02/007 of interface agreement I/F-1 LOW VOLTAGE INTERFACE of S4 1. S4 uses +5.6, -5.6 power supply sources: main and spare switched by command. 2. Scheme Main lines S4 PS main +5.6 V common -5.6 V common Main electronics PS spare +5,6 V common -5,6 V common Spare lines Spare electronics 3. Requirements to power supply sources 3.1. Current +5.6 V 400 ma -5.6 V 300 ma 3.2. Full Maximum consumption power including high voltage circuits 5 W 3.3. Leads of power supply should be isolated from housing and one from another. The main and spare power supplies are the part of power supply system of PAMELA instrument and is switched by PSCU with commands from the ground. Output connectors on the PAMELA power supply unit is not defined. Cable is fabricated by INFN. Connector on S4 XS2 of РС19 type (see connection scheme, Appendix 11. Connector РС19 is delivered by MEPhI. The pinout is presented in Appendix

20 Appendix 11. S1 S5 S2 S3 S4 S6 S8T S9T S4 S10T 20

21 S2 (PS main and PS spare ) PC-19 1 Housing 2 Connection check 3 +5,6V main 4 Common +5,6V main 5 Common +5,6V main 6 +5,6V main 7-5,6V main 8 Common -5,6V main 9 Common -5,6V main 10 +5,6V spare 11 +5,6V spare 12-5,6V main 13 Common +5,6V spare 14 Common +5,6V spare 15-5,6V spare 16-5,6V spare 17 Common -5,6V spare 18 Connection check 19 Common -5,6V spare 21

22 S5 (TRIG main STATUS main+spare ) PC-19 1 Housing 2 TRIG (no inv) main 3 TRIG (inv) 4 TRIG_50 (no inv)main 5 TRIG_300 (no inv)main 6 TRIG_300 (inv)main 7 Connection check 8 TRIG_50 (inv)main 9 STATUS (no inv) main 10 STATUS (inv) main 11 TRIG (no inv) spare 12 TRIG (inv) spare 13 Connection check 14 TRIG_50 (no inv) spare 15 TRIG_300 (no inv) spare 16 TRIG_300 (inv) spare 17 TRIG_50 (inv) spare 18 STATUS (no inv) spare 19 STATUS (inv) spare 22

23 S6 (PS main and PS spare ) PC-19 1 Housing 2 GATE (no inv) main 3 GATE (inv) main 4 Connection check 5 CALIBR (no inv) main 6 CALIBR (inv) main 7 DATA (no inv) main 8 STROBE (no inv) main 9 STROBE (no inv) main 10 GATE (no inv) spare 11 GATE (inv) spare 12 DATA (inv)main 13 CALIBR (no inv) spare 14 DATA (no inv) spare 15 DATA (inv) spare 16 Connection check 17 CALIBR (inv) spare 18 STROBE (no inv) spare 19 STROBE (inv) spare 23