ANITA SMEX Digitizer/DAQ. Gary S. Varner University of Hawai, i, Manoa ANITA Collaboration JPL March 2004

Transcription

1 ANITA SMEX Digitizer/DAQ Gary S. Varner University of Hawai, i, Manoa ANITA Collaboration JPL March 2004

2 Overview System overview SMEX Trigger items covered by Andre ROSS descope in Part II Summary of Progress System Definition Further STRAW2 evaluation (DALIREVB) Critical R&D Items (SMEX) RFCeval testing STRAW3 LABRADOR SMEX: BGA option RF pulser Design Review, Fabrication run since Aug. Collab. Meeting 1

3 Proposed Signal Flow Trigger LNA Gain [GHz] Digitize [GHz] 2

4 SMEX DAQ Architecture 3

5 Straw Man Trigger /Digitizers 4

6 Updated August 03 Baseline ANITA Sampling Unit for RF (SURF) Board 5

7 Previous Open Design Issues RF amps/filter mounting Directly onto back of antennas? (modular) Better performance, but power, cooling, cabling issues Miteq LNAs adequate? Sufficient sensitivity (w/ power limit, multi-notch filters)?? Trigger architecture: Global, local, cluster (half-array)?? Logic on SURF boards?? Multi-leveled?? Multi-band?? VETO?? RCP & LCP generation?? Signal digitizing: Half sample interleaving (longer record length)?? Alternatives to current plan?? Multi-buffering (ping-pong) depth?? 6

8 RF Partition Pro Con LNA Payload Better NF Distribute heat No low-noise inside payload can Simplifies cabling inside payload can(s) Pressurized housing? External Power cabling External noise diode signal cables Payload Pro Con Cleaner external cabling Fewer housing penetrations Worse NF EMI shielding internally; complicates cabling inside payload can(s) Impedance matching 7

9 Board mechanics Shielded breakouts TempMon I/F ADC I/F DAC I/F Digital I/O I/F 12 8

10 Trigger Partition Local RF AMP SURF ARF ARF SURF Global Trig Local holds Global digitize RF AMP Global SURF Global Trig Global hold & digitize Potentially lower noise 9

11 Front-end choice Add input protection If possible 10

12 RF Power Budget Needs Update 11

13 ANITA-lite Lessons Lack of working software impacted the schedule RF/DAQ lessons: Need modular packing/higher integration for RF components Power/signal distribution need better solution ~ 200W for 2x antennas (though much doesn t scale) Massive # of vacuum feedthroughs forcing unpressurized operation With careful shielding/choking internal EMI manageable Services/housekeeping: Many deficiencies uncovered Good prototype for actual flight Choice of cpci seems good Working example for RF triggering (& need for VETO?) Faster GPS access (serial port/interconn drop) only serious problem Finer granularity power segmentation better distribution 12

14 Askaryan Signature Time (ns) Significant signal power at large frequencies Strong linear polarization (near 100%) 13

15 RF Transient Recorder Specs >= 1GHz analog input bandwidth ( MHz) multi-gsa/s sampling rate (>>Nyquist limit) minimum phase distortion for clean polarization dynamic range (>= 10 bits) internal Analog to Digital Conversion (ADC) short record length ( ns if optimally matched) self-triggering with fine threshold adjustment bi-polar triggering deadtimeless conclude multi-hit buffering needed 14

16 STRAW Architecture 0.25µm TSMC process 15

17 STRAW3 Data Sheet Available on the ID Lab web-site Should allow any competent EE to design around it (interest from RICE) 16

18 Switched Capacitor Array (SCA) Write pointer is ~4-6 switches once input 17

19 STRAW2 Chip Self-Triggered Recorder Analog Waveform (STRAW) 16 Channels of 256 deep SCA buckets Optimized for RF input Microstrip 50Ω DACs 8192 analog storage cells ADC Self-Triggering: -LL and HL (adj.) for each channel -Multiplicity trigger for LL hits On-chip ADC: 12-bit, >2MSPS Target input Bandwidth: >700MHz 32x256 SCA bank Trigger Sampling Rate: 1-2GSa/s (adj.) Sampling Rates >~8GSa/s possible w/ 0.25µm process Record length: ns External option: MUXed Analog out Die:~2.5mm 2 scalers Fabricated Winter

20 STRAW2 Evaluation Adjustable: GSa/s 256 samples (70 300ns) RF signal input 19

21 RF Response (1) Sub-ns transient ping: <= 100ps leading edge Scope ET sampling: 100 Gsa/s equiv. 20

22 RF Response (2) Very nice tool: FFT analysis of RF transient pulse Have ideas how to improve roll-off matches SPICE simulations of storage cells 1/8 ampl 21

23 STRAW2 Lessons Extremely subtle error in on-chip ADC Worked in 5 previous designs fixed a symbol problem elsewhere Triggering Problem with DAC load Layout was horrible -- interference Input impedance Target 50Ω, 130Ω actual (used wrong extracted parameter), but makes the routing awkward Based upon these results, decided to bifurcate the design: STRAW3 update STRAW2 with bug fixes slight bandwidth improvement LABRADOR dedicated sampling chip with improved ADC 22

24 Updated August 03 Baseline ANITA Sampling Unit for RF (SURF) Board 23

25 LABRADOR Goals Maximum input bandwidth 50Ω impedance Simplified architecture (no trigger functionality) best RF coupling into Switched Capacitor storage cells Classical engineering trade-offs Input trace resistance vs. load capacitance Storage capacitor ktc noise vs. load capacitance Storage switch R on vs. drain load capacitance Analog Transfer Optimum speed Individual channel parallel Improved ADC Ramp type no missing codes Massively parallel to reduce conversion time Address Part II 24

26 RF Transient Recorder Specs >= 1GHz analog input bandwidth ( MHz) multi-gsa/s sampling rate (Nyquist limit min.) minimum phase distortion for clean polarization dynamic range (>= 10 bits) internal Analog to Digital Conversion (ADC) short record length ( ns if optimally matched) self-triggering with fine threshold adjustment bi-polar triggering deadtimeless conclude multi-hit buffering needed LOW POWER!! (need 36(40) * 2 channels) {+ VETO?} [Acqiris > 1kW] Target: 20W/channel 20mW/channel 25

27 LABRADOR Architecture 0.25µm TSMC process 26

28 Readout speed comparison IC STRAW2 - GEISER STRAW2 DALI ADC EXT EXT speed 8MHz 1MHz Total Latency 384 µs 3,072 µs Evt. Size 6kB STRAW3 -- SURF STRAW3 -- FINESSE INT EXT 2.5MHz 10MHz (a) 1,638 µs 410 µs 8kB LABRADOR -- SURF INT 100kHz (b) 240 µs LABRADOR -- serial EXT 10MHz 210 µs 4kB LABRADOR -- parallel EXT 20MHz 12.8 µs (a) 16 channels for STRAW3, 12 channels for STRAW2 (b) 12.8MHz effective: 128x ADC; 100MHz clock, 12b eff. includes additional latency 8x 20MHz ADC in parallel (>300MB/s!!) 27

29 Understanding STRAW2 Performance Contributions considered: Simple Estimates based on R(Z)LC Coupling into package leadframe (TQFP-100) On-chip stripline What is the real limitation? Cannot rule out multiple contributions (2x poles?) 28

30 STRAW2 Model MOSIS ID 3.2mm 7mm ii Micro strip input 29

31 STRAW2 Equiv. Ckt. Lbond=2.6nH (Z=130,L=6mm) 22-45Ω ~1kΩ 78fF 29Ω 0.11Ω ~6fF 48Ω 17Ω ~50Ω Ω STRAW2 STRAW3 M4 M4 M5 98λ M5 98λ 14λ 60λ Z~50Ω Z~30Ω STRAW2 Resistance Estimate Input (RF) Input (ref) bond wire pad M5-M4 Metal 4(sheet) = 0.07 Ohm/sq typ length (sq.) Metal 5(sheet) = 0.03 Ohm/sq typ length (sq.) Poly contact = 5.1 Ohm via 1= 2.7 Ohm via 2= 5.35 Ohm via 3= 8.26 Ohm via 4= Ohm Total per feed 48.3 Rterminator Measured: 130 Ohm Grand Total 30

32 Naïve Calculations EST. Component Length/area Unit Factor Funit Total [ff] Input traces 5 cm 0.2 pf/cm 1000 w.a.g. bonding wire 150 mil 0.3 pf/wire 300 w.a.g. input pad 60 um^2 187 ff/pad 187 Tanner input protection 594 λ 1.1 pf/ckt 1100 SPICE stripline area 2500 um^2 43 af/um^ MOSIS stripline fringe 5 mm 60 af/um 300 MOSIS Switch Drains 256 switches 5.6 ff/drain SPICE Open Switches 6 open 87 ff/gate 522 SPICE TOTAL pf R=R feed R~30Ω C=C load C~2.5pF 1 f3 db = = 2.1GHz. 2 π RC Bonding wire, series R limit Z=Z 0 ~50Ω C~2.5pF 1 f3 db = = 1.27GHz. 2 π ZC Lumped element ~80Ω C~2.5pF 800MHz C probably pessimistic, but 2 nd pole? 31

33 Bounding Case Guidance for Cap Max BW [GHz] pure C + Zo STRAW Total Load Capacitance [pf] 32

34 Storage Capacitor constraints Impact of Storage Cap size 2.5 For 1V useable input range 2 9bits v kt C rms = = store mv Vrms [mv] bits Vrms C store only 78fF!! bits STRAW2 Too big?? 0 12bits Storage Cap [ff] DC SPICE sim shows can make R static ~ 920Ω, but there is a dynamic component also. 33

35 SPICE stripline vs. lumped Transmission line lossy (multiple elements) Two techniques give plausibly consistent results, however there is good reason to be skeptical (GIGO) One 1GHz, length of on-chip stripline is approx.4-6 o (STRAW2/3) [~3 o LABRADOR] 34

36 RF Response SPICE Simulations of direct drive onto storage cap, closed switch gave Substantially higher simulated bandwidths 35

37 Parameter Space Simulation Sample compares 1 Amplitude unloaded 0.25pF load Ref x6 37fF Cstore Big gate SuperD buff Big Cstore Tiny Cap GND source -0.4 Time[ns] 36

38 Turn-off Simulation Switch Transition Timing Gate voltage [V] kΩ 3.4kΩ 604MHz 11.7kΩ 170MHz 11.7kΩ 1.4MHz SMP0 SMP0b GHz Time [ns] 37

39 STRAW2 Bode Analysis Simulate Waveform Acquisition Onto stripline Stored on Cap Value from transient analysis 38

40 DALI Rev. B Evaluation Delay lines for interleaved sampling (>5.4GSa/s in lab) STRAW2 chips PCI bus Interface 39

41 cpci DAQ Each event: 2 chips * 16 channels * 256 SCA * 2 Bytes = 16kB/event MIC P3 CPU DALIREVB On extender Card Even with pokey MIC (~1k$) able To acquire >50Hz continuous (no DMA) 40

42 STRAW2 noise measurement DALI Rev. B board unshielded ~0.5mV typ 500mV Dynamic Range = 10 bits 41

43 DALI Rev. B Evaluation STRAW2 chip CW input SPICE prediction 42

44 LABRADOR case 8 chan. * 256 samples 128x Wilk ADCs 8x HS Analog out, 1x MUX out STRAW3 43

45 LABRADOR Equiv. Ckt. Fixed 0.3Ω ~0.7kΩ 10fF 4.7Ω 0.02Ω ~12fF 28Ω 5Ω ~13Ω Ω STRAW2 LABRADOR M4 M4 M5 238λ M5 98λ 14λ 102λ Z~50Ω Z~13Ω LABRADOR Resistance Estimate Input (RF) Input (ref) bond wire Length λ pad M5-M4 Metal 4(sheet) = 0.07 Ohm/sq typ length (sq.) Metal 5(sheet) = 0.03 Ohm/sq typ length (sq.) Poly contact = 5.1 Ohm via 1= 2.7 Ohm via 2= 5.35 Ohm via 3= 8.26 Ohm via 4= Ohm Total per feed 28 Rterminator Measured: Ohm 50.0 Grand Total 44

46 LABRADOR Bode Analysis ~2GHz (if can get into package) 45

47 RFCeval 0 th order prototype Quick Reference: RFCeval == Radio Freq Comp evaluation board STRAW == Self-Triggered Recorder for Analog Waveforms LABRADOR == Large Analog Bandwidth Recorder And Digitizer with Ordered Readout 46

48 STRAW3 Measurements 1 Measurement on DALIREVB Board 0 Amplitude [db] -1-2 ch.2 ch.3 ch.4 ch.5 ch.6 ch.7 ch

49 TDR Measurements Step input measures S11 48

50 RF Coupling Simulation die on-chip 50Ω stripline STRAW2 Packaging S-Parameters VSWR: 1.9 [2GHz] S11 S21 Bonding wires [1GHz] Frequency [GHz] Utilizes the LC program (FTDT algorithm) Cray developed, available for free under Linux 49

51 TDR Technique Nasty ringing on DALIREVB 50Ω 60Ω Protection diode open 50Ω 50

52 TDR Measurement configs: STRAW2eval RFCeval Static R = 130Ω Static R = 60Ω 51

53 Ball Grid Array (BGA) Option Measurements: consistent with an LC tank circuit of L = 2x bondwire, C = on-chip capacitance Bond-wire estimate = 2.6nH (each) Load capacitance ~3.8pF f 0 = 1/(2*pi*SQRT(LC)) ~ 1.13 GHz Flip-chip/BGA not possible for ROSS Significantly reduced input inductance Better power dissipation Investigating via MOSIS Custom BGA package MOSIS ID 3.2mm 7mm ii 52

54 RF Pulser Prototype RF Pocket Pulser <0.2k$/channel Avtech Pulser 4k$/channel 53

55 RF Pulser Measurements 2 nd Revision in Design Fab next week Multi-stage Low power Significant power > 1GHz Low-power (low duty cycle) operation 54

56 Design Issues for Discussion Interleaving is NOT a slam dunk Need to pay careful attention to the RF routing Density issues drive form factor Need lower C input protection Tentative footprint is deep 6U Conduction cooling R&D, side-plate with PTC? Thermal Vac Qual Testing Plan?? When to freeze the design? (RF parts search) Sample Rate/Buffer depth: As long as can form L1 trigger in 40-55ns, OK? 3GSa/s 256 samples (85ns window) Multi-buffering (ping-pong) depth (4x)?? 55

57 Summary R&D into critical (non-standard) components: Have a near-spec low-power sampler prototype Need for a custom trigger chip? (CF success of ALTO) Plans: RFCeval board in debug STRAW3 working LABRADOR awaiting firmware/debug (S12 measurements) cpci interface development (DALI Rev. B) Near term complete preliminary testing for CSR Building toward a SURFpro end of summer Testing covered in more detail in Part II 56

58 Back-up slides 57

59 SMEX Dual-Crate Scheme During Aug 2003 Collab Meeting challenged to go to 4 Antenna/Digitizer Card Transition module TURF boards Crate Top View CPU CPU PCI bus 7 drops max 48 channel Scenario 4 antenna SURF boards 4 spare cpci slots for other functionality (GPS, housekeeping?) 58