Development of the FVTX trigger

Transcription

1 Development of the FVTX trigger Rikkyo University Toru Nagashima Nov RadLab student seminar 1

2 OVERVIEW Physics motivation Test bench setup in RIKEN Timing measurement FVTX trigger design Trigger logic test & debugging 2

3 OVERVIEW Physics motivation Test bench setup in RIKEN Timing measurement FVTX trigger design Trigger logic test & debugging 3

4 The Ridge in AA Collision p and AA collisions The ridge in pp Pb Pb CMSPreliminary 35-40% PbPb 2.76 TeV PbPbs N =2.76TeV p ϕ pair 2 dn ²d# ²d! 1 N trig Ridge y ϕ x Elliptic flow: cos(2δϕ) arxiv: ! 4 ² # 2 0 JHEP 07 (2011) 076! EPJC 72 (2012) 2012! ²! 2 4 z A preferred plane for particle emission Initial-state geometry + collective expansion Indication of Collective Effects Unexpected ridge-like correlation Smoking gun of a strongly interacting QGP liquid! 13 Slide from Wei Lei, Rice University 4

5 CMS Reported Ridge feature in pp,pa 5 Slide from Wei Lei, Rice University

6 The ridge in pp collisions High Multiplicity Event is the key! Two-particle Δη-Δϕ correlation pp <N>~15, 1<p T <3 GeV/c pp N>110, 1<p T <3 GeV/c Very high multiplicity pp collisions Very high-multiplicity pp events are rare in nature No ridge observed in minimum bias I pp or any pp MC generators High multiplicity trigger in FVTX is to be developed for Run15! <N offline trk >~15 for MB pp Very exotic pp events prob. 6 Raw counts of tracks! Slide from Wei Lei, Rice University 6

7 OVERVIEW Physics motivation Test bench setup in RIKEN Timing measurement FVTX trigger design Trigger logic test & debugging 7

8 Setup in the laser building BCO FEMIB Wedge ROC FEM The readout devices were provided from LANL The setup had been done from July 2013 March

9 Amplitude Calibration Setup in test bench is designed for calibration Some parameters are controllable (channel mask etc.) ADC Wedge Amplitude Hit Information ROC DAQ PC Contains pulser for the calibration Amplitude : pulse height of the calibration pulse ADC : Energy deposit on the sensor ADC Strong correlation between ampl(input) and ADC(output)

10 Self trigger To confirm the setup works correctly, we checked the position dependency on the source collimated source Chip number Wedge(FVTX sensor) 10

11 Right (around chip1,13) collimator source 11

12 Middle (around chip7,20) collimator source 12

13 Left (around chip14,26) collimator source 13

14 OVERVIEW Physics motivation Test bench setup in RIKEN Timing measurement FVTX trigger design Trigger logic test & debugging 14

15 Timing measurement How much BCLK is available for the trigger? The measurement was done using a trigger signal generated by a prototype trigger algorithm Time difference? FEM wedge ROC FEM test pin Scope Pulser for the calibration 15

16 Timing measurement 1ch : calibration pulse 3ch : trigger signal Confirmed the consistency with the self trigger mode later. 2.62us 1.3us (Processing time) 1.3us (additional delay) To avoid counting loss of the late hit information Need to care about the time constraint of GL1 (2us after the collision) 16

17 FVTX Trigger Original Concept collision FEM Trigger 1 BLKC process + 4 BLCK window 1 BCLK process + 1 BCLK Mulit FEM window + 1 BCLK latch + delay LL1 requires to receive the trigger signal by 17 BCLKs after the collision. This is very tight in the present FVTX trigger process time. FEM-IB LL1 GL1 BCLK ~

18 FVTX Trigger Timing Chart collision FEM Trigger 1 BCLK process + 4 BCLK window 1 BCLK process + 1 BCLK Mulit FEM window + 1 BCLK latch + delay FEM-IB Trigger Discri. TTL->ECL ECL-> TTL RBIB GL1 90ns BCLK ~

19 OVERVIEW Physics motivation Test bench setup in RIKEN Timing measurement FVTX trigger design Trigger logic test & debugging 19

20 FVTX Readout All hits are sent to FEM regardless of trigger request FEM Slow Control FEM-IB FPGA 20

21 FVTX Trigger Design Raise a track flag if track like hit pattern is found. FEM If the number of flagged FEMs are more than threshold, then issue a trigger Track flag Slow Control FPGA TRIGGER GL1 FEM-IB 21

22 FEM FPGA EAST #hits > 3/4sta ons FEM-IB FPGA Δφ=15 #hits > 3/4sta ons OR limited to 1 bit #track > 5track/east #track > 5track/west AND TRIGGER WEST At least one hit in 3 out of 4 stations is required within a sector -> Track Flag The trigger signal between FEM-FEMIB is limited to 1 bit. Each trigger logic(and,or,3/4 ) are programmable. 22

23 OVERVIEW Physics motivation Test bench setup in RIKEN Timing measurement FVTX trigger design Trigger logic test & debugging 23

24 FEM trigger All hits are sent to the FEM #hits/event>threshold? -> FEM trigger Prototype of the multiplicity trigger logic had already been developed The logic had to be improved because of the timing constraint 24

25 Double pulse debugging Wedge FEM Second pulse Hit information ~10hits / 1BCLK -> need additional delay to deal with the massive hit events Trigger signal The trigger signal splits into 2 pulses if the additional delay is too short. 25

26 Double pulse debugging Add some logic to ignore the late hit information -> The issue solved disappeared Second pulse is not observed even for 30% FVTX occupancy 26

27 FEMIB trigger 12FEM triggers are sent to 1 FEM-IB FEM-IB FPGA FEM-IB #FEMtrigger>threshold? -> FEM-IB trigger 27

28 FEMIB trigger simulation Need time window to deal with multiple FEM FEMIB trigger FEM IB 12FEMs FEM trigger Input from the 12FEM #firing FEM Simulated by the FPGA simulator 10ns (time lag between the FEMs) 75ns FEMIB TRIGGER TRIGGER signal for GL1 (need to be ~80ns) 28

29 Schedule (RIKEN) More debugging using the simulator - multi hits in consecutive BCO - recovery from massive hit events Efficiency analysis using the trigger emulator (BNL) Nov.4 19 : FEM FEM-IB cable installation 1st week December : VTX/FVTX ready for operation December : FVTX trigger test at IR 29

30 Summary Setup the FVTX trigger test bench for the development The trigger design was made up and it needs few additional hardware (only some cabling) The trigger logic have been developed. Debugging and analysis for update are ongoing 30

31 Backup 31

32 FVTX readout system data line device control BCO VME FEM IB Wedge silicon FPHX ROC FEM NI GL1 32

33 Amplitude Calibration Clear peak at #hit/event =13 Strong correlation between ampl(input) and ADC(output) ADC hits/event observed some unique behavior of the calibration data taking! 33

34 FVTX Readout All hits are sent to FEM regardless of trigger request FEM Slow Control FEM-IB FPGA 34

35 FVTX Trigger Design Raise a track flag if track like hit pattern is found. FEM If the number of flagged FEMs are more than threshold, then issue a trigger Track flag Slow Control FPGA TRIGGER GL1 FEM-IB 35

36 Distance dependency Correspondence between distance and count rate? Source x Wedge ROC Black case 36

37 Distance dependency This decrease is caused by acceptance and energy loss in air 37

38 Why timing measurement? GL1 generates trigger signal 20BCLK after the collision For the trigger design, we have to know the processing time through the devices The measurement was done using a trigger signal that is output by a prototype trigger algorithm 38

39 Dual Port RAM 39

40 Trigger efficiency Visual scaler FEM Trigger signal #Trigger data DAQ PC #Trigger #hits > threshold = 0.88 #hits> threshold (offline) Counting loss? Need to investigate the FPGA logic 40

41 #hits/event Efficiency analysis Trigger threshold #hits counted by FPGA doesn t exactly correspond to the actual #hits. Looks like there is another problem about trigger threshold. It makes sense if the trigger fires when #hits = 12, even though the threshold is set at 13hits. #hits counted by FPGA 41

42 42

43 Timing jitter between FEMs Δt < 0.5ns 43

44 Serial Line connects between FEM and FEMIB FEM FEM-IB 44

45 FEM FEMIB cable production 45

46 Signal shaping 46

47 Oct-Nov. Plan in RIKEN test bench FEM-FEMIB Cable production (Oct) Consistency check of #hits vs. trigger delays Confirm linear increase of #hits can accommodate as trigger delay increases More debugging using the simulator timing jitters, multi-hits in consecutive BCO recovery from massive hit events (FIFO clear) FIFO buffer depth optimization with respect to MIN_HITS requirement of the trigger. (This is a concern the recovery time (clear time) from massive hit events. Develop FEM-IB codes Flexibility to absorb possible timing jitters among 12 FEMs. to take flexible trigger conditions. Signal width tune to be ~80ns for GL1 output Multi FEM test Requires another FEM, wedge for column-c, & data fiber Trigger Emulator development 47