Status of the CSC Track-Finder

Transcription

1 Status of the CSC Track-Finder Darin Acosta University of Florida May 2000 D. Acosta, University of Florida TriDAS Review May

2 Outline Overview of the CSC trigger system Sector Receiver Sector Processor Muon Sorter CSC/DT Interface D. Acosta, University of Florida TriDAS Review May

3 CSC Muon Trigger Scheme Strip FE cards FE LCT Strip LCT + Motherboard card LCT Port Card PC OPTICAL CSC Track-Finder Sector Receiver SR Sector Processor SP FE Wire LCT card Wire FE cards RIM RPC Interface Module TMB 2µ / chamber In counting house RPC 4µ 3µ / port card DT 4µ 3µ / sector CSC Muon Sorter 4µ On chamber In peripheral crate Global µ Trigger Global L1 D. Acosta, University of Florida TriDAS Review May µ

4 The CSC Track-Finder From DT Track-Finder (Vienna) OPTICAL MB1 DT TF ME4 ME2-ME3 12 Sector Processors SP 1 Muon Sorter (Vienna) From CSC Port Cards PC 3µ / port card ME1 SR SP 24 Sector Receivers (+12 for ME4) 3µ / sector 12 sectors MS 4µ To Global Muon Trigger GMT (UCLA) (Florida) (Rice) 4µ WBS: , From DT Track-Finder 8µ RPC D. Acosta, University of Florida TriDAS Review May

5 Sector Receiver Functionality UCLA Receive 6 µ segments via 12 optical links from 2 Muon Port Cards Require 3 Sector Receivers for one 60 sector 2. Synchronize the data 3. Reformat the data into track segment variables } LCT bit pattern η, ϕ, ϕ b,... via s 4. Apply corrections for alignment 5. Communicate to Sector Processor via custom backplane (Channel Link) 6. Fan out ME1/3 µ segments to DT Track- Finder D. Acosta, University of Florida TriDAS Review May

6 Sector Receiver Logic UCLA Front Panel JTAG interface Controller FPGA VME Optical Fiber from MPC Optical Fiber from MPC Optical Receiver Optical Receiver Deserializer Deserializer Front FPGA L U T S L U T S Back FPGA To Backplane To Barrel Repeat for each Muon D. Acosta, University of Florida TriDAS Review May

7 Sector Receiver Scheme UCLA D. Acosta, University of Florida TriDAS Review May

8 Sector Receiver Fell behind schedule after postdoc departure. UCLA Personnel added in December/January: Robert Cousins, physicist, 50% time Vladislav Sedov, electronics engineer, 90% time (10% residual work on ALCT board) Also using paid consultant for some FPGA work (UCLA CS Ph.D. candidate) Schematics now well underway. Long-lead-time parts ordered. Layout planned by beginning of May. Plan to be ready for summer Track Finder test. D. Acosta, University of Florida TriDAS Review May

9 Sector Processor Functionality Florida 1. Accumulate track segments for possibly more than one B.X. 2. Extrapolate in 3D from one station to another for all possible track segment combinations 3. Assemble tracks from extrapolation results 4. Select best 3 tracks and cancel ghosts 5. Assign track parameters: p T, ϕ, η, quality New since last Review: Combined DT/CSC overlap region onto same board as CSC-only region (add MB1 ME2 extrap.) , Improved P T assignment technique Ghost-busting when 2 muons enter 1 CSC chamber (try all combinations) D. Acosta, University of Florida TriDAS Review May

10 Sector Processor Logic Florida Extrapolation Units Track Assembler Units , Bunch Crossing Analyzer From Backplane BXA bus EU1-2 EU1-3 EU2-3 bus TAU1 TAU2 Final Selection Unit FSU EU2-4 EU3-4 TAU3 Assignment Unit EU MB1-2 AU To Front panel FIFO MUX D. Acosta, University of Florida TriDAS Review May

11 Extrapolation Logic Florida Amb(A 1 ) η road finder η road finder Q η (A1B 1) Q η (A2B 1) Q η (A3B 1) Amb(B 1 ) η 1 η (A 1 ) η (B 1 ) SUB η A-η B η 2 η AND OR z φ high CMP φ high Qual(A 1 ) Qual(B 1 ) φ med φ low ABS φ CMP φ med CMP φ low Extrap Qual Q extrap (A 1 B 1 ) quality assignment quality unit assignment unit φ b + CMP φ -φ b + φ b (A 1 ) φ b - CMP φ -φ b - φ (A 1 ) φ (B 1 ) φ b (B 1 ) SUB φ A-φ B φ b + φ b - CMP φ -φ b + CMP φ -φ b - φ AND ϕ ϕ road finder ϕ road finder D. Acosta, University of Florida TriDAS Review May

12 Track Selection and P T Assignment φ φ Florida φ 9 to 3 Sorter with ghost cancellation logic 9 Track Assembler RAMs I.D. Comparison Unit Track Rank Sorter MUX Cancellation Logic and Encoder FIFO Mode (From FSU) MUX η φ 1 φ 2 φ 3 SUB φ 1 -φ 2 SUB φ 2 -φ 3 MUX η ~2M x 8 SRAM η Rank (P T & Quality) Sign New: 3-station sagitta measurement using FPGA preprocessing and RAM (Improves P T resolution from 30% to 20%) D. Acosta, University of Florida TriDAS Review May

13 SP Prototype Layout Florida Custom ChannelLink backplane Standard VME VME/JTAG interface (developed separately) Bunch Crossing Analyzer Extrapolation Units XCV50BG256 XCV400BG560 Track Assembler Units SRAM Final Selection Unit XCV150BG352 XCV50BG256 Assignment Units SRAM Layout complete 12 layers Tests set for 6/1/00 D. Acosta, University of Florida TriDAS Review May

14 Prototype Crate Layout SR SR SP SR CCB Florida One sector is half of Track- Finder crate Six crates for entire system Fully routed for summer tests Smaller prototype tested already US CMS DOE/NSF Review: April 11-13,

15 Pre-Prototype Prototype Tests Florida VME / JTAG interface for SR and SP: Software & hardware for FPGA and SRAM downloading through VME works Channel Link backplane and connector tests: No errors found up to 58 MHz clock (400 MHz on backplane) D. Acosta, University of Florida TriDAS Review May

16 Muon Sorter Functionality Rice 1. Receive 36 muons from 12 Sector Processors bits = 648 bits (& control bits) 2. Sort and rank the best 4 muons Sort is based on 7 bits (5 bits for p T and 2 bits for quality) 3. Send the output to the Global Muon Trigger for association with RPC and DT triggers 4 22 bits = 88 bits New since last Review: Reduction in muon count from 72 to 36 (inclusion of CSC/DT overlap in Sector Processor) allows sorting to be accomplished in one FPGA D. Acosta, University of Florida TriDAS Review May

17 Muon Sorter Logic FF- FLIP-FLOP, - LOOK-UP TABLE RAM Rice FF FF FF FF 14 FF 14 FF FF FF FF 2 8 CLK 40MHz VME INTERFACE FOR READ/WRITE SORTER 4 out of comparisons in parallel SORTER 4 out of comparisons in parallel SORTER 4 out of 8 comparisons in parallel FF FF FF FF 7 8 ALTERA EP20K200EFC ADR1 PAT1 ADR2 PAT2 ADR3 PAT3 ADR4 PAT out of 36 SINGLE-CHIP SORTER BLOCK DIAGRAM AND TIMING D. Acosta, University of Florida TriDAS Review May

18 Sorter Board Block Diagram Rice CONNECTORS TO GMT 9U * 400 MM BOARD VME INTERFACE VME J1 CONNECTOR CCB INTERFACE CONNECTOR TO CUSTOM BACKPLANE GMT LVDS DRIVERS SORTER PLD CONNECTOR TO RECEIVER BOARDS D. Acosta, University of Florida TriDAS Review May

19 Muon Sorter Crate Layout Rice CONNECTORS TO GMT S R R R R CONNECTORS TO RECEIVER BOARDS D. Acosta, University of Florida TriDAS Review May

20 Sorter Receiver Board Block Diagram Rice RECEIVERS POWER CLOCK CONNECTOR TO SP Rx CONNECTOR TO SP CONNECTOR TO SP Rx Rx PIPELINE PLD 10K130E or 20K200E CONNECTOR TO SORTER BOARD D. Acosta, University of Florida TriDAS Review May

21 Summer Plans Crate test with prototype SR, SP, CCB (and TMB, MPC) scheduled for summer 2000 Bench tests start June 1 Integration tests start July 1 Will test optical link connections and trigger algorithms at 40 MHz, verify output and latency All designs are proceeding well, and we should be able to make milestone Conceptual design, schematics, and some layouts already exist Development of test software started D. Acosta, University of Florida TriDAS Review May

22 Separation of DT/CSC Coverage R (cm) Slow simulation of CMS detector in GEANT 3.21 MB2/1 ME1/3 η = Z (cm) Hard boundary defined η=1.04 Separate Track- Finders optimized for each system Information shared across boundary for maximum efficiency Tentative agreement reached on DT/CSC interface Feb 00 D. Acosta, University of Florida TriDAS Review May

23 Advantages of Proposal Interconnections are cut in half when track segments from ME 2/2 and MB 2/2 are not shared (only ME 1/3 and MB2/1 are shared) The mapping of 60 CSC trigger sectors onto 30 DT ones is avoided (no ME 2/2) But, ME1 station has 30 or 20 subsectors, so there may still be a mapping problem The RPC data may be used by the GMT to settle any ghosting problem if a single muon is found by both Track-Finders φ b and η do not need to be sent by the CSC Track-Finder for DT T-F extrapolations D. Acosta, University of Florida TriDAS Review May

24 Advantages Continued The DT Track-Finder may trigger on MB1-MB2 type tracks These track segments and all those sent by the CSC trigger are assumed to be in barrel region The CSC Track-Finder logic is considerably simplified with proposed boundary Already assumed in present prototype D. Acosta, University of Florida TriDAS Review May

25 Issues with Proposal Must demonstrate acceptable efficiency by simulation CSC Sector Receiver must be designed to send only 2 track segments (out of 3) for the barrel-overlap region D. Acosta, University of Florida TriDAS Review May