Time Stamp Synchronization of MBS (DAQ) Systems with White Rabbit Distributed High Precision TOF with White Rabbit

Transcription

1 ime Stamp Synchronization of MBS (DAQ) Systems with White abbit Distributed High Precision F with White abbit Synchronization of globally triggered MBS systems Synchronization of locally triggered (free running) DAQ systems (e.g. ADA, HYDE, MNSE,??) with globally triggered MBS (DAQ) systems Usage of White abbit controlled 200 MHz clocks as time reference for distributed (1-1000m) F measurement systems Nikolaus Kurz, EE, GS, HSPEC/DESPEC, 3-Mar

2 eminder! SNG MBS DAQ: ime Stamp Synchronization with S Gamma FS Ancillary E S M A N S D32 M V M E C P U D 2 V B M N G VX VME CP 3 CAMAC CAMAC G G E M N G VME CP 3 CAMAC CAMAC G G E M N G VME CP Event Builder LynxS PC Event Builder LynxS PC Event Builder LynxS PC CP ime rdering Data Logging nline Analysis LynxS PC All sub-systems inside the dashed boxes are able to run as independent MBS systems. 2

3 Main equirements for FA ime Stamp MBS (DAQ) Synchronization - use White abbit system. White abbit will be the control/field bus for the FA accelerator complex. - couple/synchronize MBS (DAQ) systems utilizing global triggers and (new feature, not covered with S) systems based on individual channel triggers (free running systems) - couple/synchronize VME based and PC Express based MBS systems - high event/particle/hit rates require time stamps with a granularity of <= 10 ns (100 MHz) 3

4 2014 GS est Beam 3B Executive Summary all requirements fulfilled system worked reliably connected various VME and PCe based MBS systems connected 3B silicon tracker prototype system is ready for use 4

5 Available White abbit Hardware - VME W timing receiver VEA2 - PC Express W timing receiver PEXAA5 - standalone W timing eceiver EXPLDE2 (5) - SCU - microca, others - W switches 5

6 op Down: White abbit Network Switch(es) 1 fiber uplink 17 fiber downlinks to white rabbit timing receiver nodes supports PP (Precision ime Protocol) 6

7 White abbit VME iming eceiver VEA2 2 general L N 5 general L out LVDS out USB1 rigger bus SFP to/from W switch L time stamp latch in USB2 HDM: 200 MHz LVDS clock out 100 khz LVDS 0 out 7

8 emplate MBS System with VEA2 4 Linux (silver) VA7 (blue) VEA2 (blue) 8

9 White abbit PC Express iming eceiver PEXAA5 HDM: 200 MHz clock out 100 KHz 0 out L time stamp latch in SFP from/to W switch 9

10 emplate MBS System with PEX / X/ PEXAA 10

11 emplate MBS System with PEX / X/ PEXAA PEX X PEXAA 11

12 Selected Features of White abbit iming eceivers (W) - 64 bit time stamps with 1 ns units, starting from FFs for 256 W time stamps (allows for multi-event readout for globally triggered MBS systems) - time stamp latch units. latches actual time stamp with leading edge of L input signal. nput signal shall be accepted trigger signal and 200 MHz W controlled high precision LVDS clock outputs KHz 0 LVDS pulse train - W time transmission between 0 pulses via serial protocol PEXAA: VEA2: 1 ns time stamp granularity 8 ns (125 MHz native network clock) 12

13 wo Globally riggered, White abbit Synchronized MBS Systems uplink W Switch raw trigger in accepted trigger out trigger decision trigger decision raw trigger in accepted trigger out trigger bus trigger bus 4 V A V E A VME P E X X PC PCe 4 V A VME P E X X P E X A A PC PCe tcp tcp tcp eventbuilder eventbuilder tcp MBS system A tcp time sorter tcp MBS system B data logging and monitoring 13

14 White abbit ime Stamp esolutions MBS Systems Utilizing Global riggers PEXAA5 vs PEAA5 ime stamp Diff: 3.7 ns (MS) PEXAA5 vs VEA2 ime stamp Diff: 6.8 ns (MS) VEA2 vs VEA2 ime stamp Diff: 9.1 ns (MS) 14

15 Synchronization of Free unning System with Globally riggered MBS System uplink W Switch physics raw trigger in 1Hz pulser / trigger accepted trigger out 4 trigger decision V A V E A VME trigger bus P E X X PC PCe 3) 1Hz S reference signal in wo LVDS lines: 1) 200 MHz W Clock in 2) 100 khz pulse train with serial W time reference in FPGA 4) trigger request out free running system 5) region of interest () in tcp tcp MBS system eventbuilder tcp tcp time sorter tcp MBS foreign data receiver data logging and monitoring 15

16 White abbit 100 KHz 0 and - Serial ime Distribution White abbit 200 MHz 10 micro sec 200 MHz Coded 64 bit W time at next MHz 16

17 Summary Synchronization nputs/utputs for Free unning Systems 1) 200 MHz: input, mandatory - disciplined by W - could be other frequency (50 MHz?) on request - basic precision 5 ns (with 200 MHz W clock). Could be improved with fast FPGA in free running system 2) 100 KHz 0 + serial time forwarding: input, mandatory - decoder and encoder FPGA code available - phase stable with 200 MHz W clock - no reset necessary, if new systems couple to a running system 3) 1 Hz reference hit: input, mandatory - allows permanent testing of W time stamp status - allows for continuous data flow. important for time sorter 4) (region of interest): input, important - allows to cut out data outside a programmable time window from free running system - could be accepted trigger signal from globally triggered system - important, if data rate from unwanted hits (noise, delta electrons) becomes too high 5) (trigger request): output, nice to have (depends) - to be used by globally triggered systems as input for trigger processing 17

18 White abbit ime Stamp esolution Global riggers vs Free unning PEXAA5 vs 3B silicon tracker ime stamp Diff: 6.6 ns (MS) 18

19 White abbit ime Stamp (WS) Data Format sub-system id (32 bits, multiples of 0x100) 0x03E1 (16 bit fixed code) WS bits x04E1 WS bits x05E1 WS bits x06E1 WS bits data packets from free running systems: - free running data acquisition systems sends formatted MBS sub-events of hits - each sub-event is headed by WS - each sub-event contains data from many hits (MBS container) - each hit has S of variable size, but significantly smaller than WS - each hit S must have a sufficient correlation to full WS header - hit data format inside MBS container has no dependency for time sorting and can be chosen freely by each detector/sub-system 19

20 distributed F with White abbit controlled 200MHz clock reference 20

21 est Setup F with White abbit 200 MHz eference uplink W Switch raw trigger in trigger decision fiber fiber PEXAA5 PCe accepted trigger out PEXAA5 PCe high precision splitter delays 200 MHz LVDS clock 200 MHz LVDS clock 4 V A V F X 0 V F X 1 hit signals in VME trigger in 21

22 White abbit 200 MHz Clock Effects on F Measured with High esolution VME DC VFX time difference between 2 channels fed in identical VFX: 7.8 ps (MS) time difference between 2 channels fed in different VFX: 22 ps (MS) 300 ps 300 ps 30 ps 30 ps 16 h 16 h trending of average time differences between 2 channels fed in identical VFX (each entry is average of F measurements trending of average time differences between 2 channels fed in different VFX (each entry is average of F measurements 22

23 Acknowledgements White abbit core team: D. Beck, M. Kreider, C. Prados, S. auch, W. erpstra, M. Zweig EE: Jan Hoffmann: Design of White abbit iming eceivers Joern Adamczewski-Musch: Linux device drivers Jochen Fruehauf: VFX, MBS F setups hank You 23