Moller DAQ with the FADC250 B 2. Figure M1 CR SR CL SL FADC SD_FP. VME64x FLEX_I/O ROC CR: CALORIMETER RIGHT [1-4] SR: SCINTILLATOR RIGHT [1-4]

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1 Moller DAQ with the F5 CR: CALORIMETER RIGHT [1-] CR SR CL SL F SR: SCINTILLATOR RIGHT [1-] CL: CALORIMETER LEFT [1-] SL: SCINTILLATOR LEFT [1-] A b a SD_FP A: [ HELICITY, HELICITY_FLIP ] (NIM or ECL) a: [ HELICITY, HELICITY_FLIP ] (LVDS) B B1 NIM / ECL <-> LVDS FLEX_I/O Port 1 VME6x b: [ HELICITY_TRIGGER, DATA_TRIGGER ] (LVDS) B Port B: [ HELICITY_TRIGGER, DATA_TRIGGER ] (ECL) ROC Figure M1

2 Overview Scintillator and calorimeter signals from the left and right halves of a Moller polarimeter are input into the F. Using the flexibility and speed of the FPGA, various logical quantities based on digital sums and hit patterns of the inputs is computed (see detailed description later). Some of these quantities (5) are scaled, while others (3) are used to trigger the capture of the input pulses that produced them. The comparison of the scaler values for the beam in its two helicity states is the object of the study. Figure M shows the free-running accelerator signals HELICITY and HELICITY_FLIP. These are input as control signals into the F front panel (after level conversion by the SD_FP module). The assertion of HELICITY_FLIP indicates that the helicity state is in transition, so scalers and triggers are disabled during this time. When the user issues GO to start a data run, enabling of scalers and triggers (ENABLE_MOLLER) will not begin until the trailing edge of the next HELICITY_FLIP pulse. Similarly, when GO is negated, acquisition will continue until the leading edge of the next HELICITY_FLIP pulse. In this way, data will always be acquired for an integral number of valid helicity periods (ENABLE_MOLLER). At the end of each ENABLE_MOLLER period, scaler data (ten 16-bit words) is transferred from the Moller FPGA to the Control FPGA over the 16-bit control bus. It is stored in an internal as six 3-bit words (1 header 5 scalers). The header identifies the helicity state (bit 31) and the helicity interval number (bits 3-). When the transfer is complete, the scalers are cleared. They are enabled to count again when ENABLE_MOLLER is asserted. At the end of each ENABLE_MOLLER period, the pulse HELICITY_TRIGGER is output from the F front panel. This is used to interrupt the Read Out Controller (ROC) so that the scaler data can be read out. This is done by routing the signal to port 1 of the FLEX I/O module (after level conversion by the SD_FP). For each internally generated trigger, the helicity state and trigger pattern are stored as a single word in the MOLLER. As the data is being collected, the trigger word is transferred to the Control FPGA over the control bus, and appears as a type 1 (user defined) data word in the event. Data from internally generated triggers is stored on the F until a programmed number (block, 55 maximum) of events is acquired. When this happens, a pulse (DATA_TRIGGER) is issued from the F front panel. This signal is routed to port of the FLEX I/O module (after level translation by the SD_FP module). The FLEX I/O interrupts the ROC so that the block of events may be read out. When the read out is complete, the ROC acknowledges the transfer and re-enables DATA_TRIGGER generation.

3 Figure M HELICITY HELICITY_FLIP GO ENABLE_MOLLER ( START RUN ) ( END RUN ) TRANSFER SCALERS CLEAR SCALERS HELICITY TRIGGER ACQUIRE DATA ACQUIRE DATA AQUIRE DATA

4 HALL A Moller Polarimeter Requirement 1 3 LEFT SCIN TILL ATOR 1 3 RIGHT SCIN TILL ATOR When TRIGGER condition is met, send data that cause TRIGGER. TRIGGER condition (or): CL.AND.CR prescaled from 1 to at least 1 CL prescaled from 1 to at least 1 CR prescaled from 1 to at least CAL ORI MET ER 1 3 CAL ORI MET ER CR = Σ I=1, j=1, P J I > threshold CL = Σ I=1, j=1, P J I > threshold SL = (Σ J=1, S1 J > threshold) or (ΣJ=1, S J > threshold) or (ΣJ=1, S3 J > threshold) or (ΣJ=1, S J > threshold) SR = (Σ J=1, S5 J > threshold) or (ΣJ=1, S6 J > threshold) or (ΣJ=1, S7 J > threshold) or (ΣJ=1, S8 J > threshold) F-5 ON BOARD SCALER (COUNTER) to be read out by a separate trigger (helicity and gate bits) at the helicity cycle of 3 to khz. CL and CR CL and SL CR and SR CL and CR and SL and SR CL and CR and (SL and SR delayed > 1 ns)

5 F HARDWARE ARCHITECTURE 16 9 LX5 Control Bus 8 1 LX5 FX 3 ALTERA STRATIX VME BUS Front Panel Lvds Trig, Sync BACK Plane Trig, Sync

6 MOLLER DAQ FIRMWARE ARCHITECTURE TOP LEVEL Capture Data L Calorimeter ( ) L Scint (1..9) R Calorimeter ( 8..5) R Scint (..1) LX5 LX5 Cal Sum 16) Scint Hit () Cal Sum 16) Scint Hit () FX Trig Type, Trig Count, Helicity, Gate Trig Ready trigger ALTERA STRATIX VME BUS trigger Capture Data Front Panel Helicity Gate

7 MOLLER DAQ FIRMWARE ARCHITECTURE LX5 TRIGGER Cal 1 Cal G en1 G en S en1 GS en C = Σ I=1, P I SUM Cal 1- Scint 1- HISTORY Trigger Capture Data To Scint1 8 G en5 REG > SR = j=1, S J > Th x Scint G en8 REG > Threshold HIT Threshold SL = j=1, S J > Th x No change to Look Back Algorithm G Global

8 1 st LX5 SUM nd LX5 SUM 1 st LX 5 HIT nd LX 5 HIT P Programmable -1 - X-Pn1 - P Threshold > Px FixWidth -1 - X-Pn1 SL SR - > P Threshold Px FixWidth Px FixWidth Px FixWidth MOLLER DAQ FIRMWARE ARCHITECTURE FX CR = j=1, P J Px DELAY Px DELAY Px DELAY CL = j=1, P J Px DELAY Px DELAY (min 1 ns) CR CL SR SL d(sl*sr) TRIGGER LOGIC TRIG TYPE CL CR (CR*CL) (CL*SL) (CR*SR) P Prescalar (CL*CR*SL*SR) P Prescalar P Prescalar (CL*CR*d(SL*SR) Trig Ready Hit Window Trig pattern Trig Type En Clear 3 bits Counter En Clear 3 bits Counter En Clear 3 bits Counter En Clear 3 bits Counter enable En 1 bits Counter Helicity(aux), TrigCount C O N T R O L B U S Trig Ready from ALtera FPGA Trigger to ALtera FPGA Hit Pattern to AUX() AUX(1) CNT_CTRL bit from Altera En Clear 3 bits Counter

9 MOLLER DAQ FIRMWARE ARCHITECTURE FX (Hit Window) CL_Prescale CR_Prescale CLandCR Prescale c s En Clr = Counter 8 e c CL e c CR e c CLandCR Trigger

10 MOLLER DAQ FIRMWARE ARCHITECTURE Altera FPGA FRONT PANEL HELICITY Control TRIG READY TO FX AUX()TO FX TRIG FROM FX TRIG TO LX5

11 MOLLER DAQ FIRMWARE ARCHITECTURE Altera FPGA FRONT PANEL HELICITY Control TRIG READY TO FX AUX()TO FX TRIG FROM FX TRIG TO LX5