Pixel Detector for the Protein Crystallography Beamline at the SLS

Transcription

1 Pixel Detector for the Protein Crystallography Beamline at the SLS PSI Ch. Brönnimann 1, E. Eikenberry 1, S. Kohout 1, B. Schmitt 1, C. Schulze 1, R. Baur 2 and R.Horisberger 2 1 Swiss Light Source, Paul Scherrer Institut, CH-5232 Villigen-PSI 2 CMS-Project, Paul Scherrer Institut, CH-5232 Villigen-PSI University of Bonn P. Fischer 3, S. Florin 3 and M. Lindner 3 3 Physikalisches Institut der Universität Bonn, Nussallee 12 D Bonn

2 Data collection in protein crystallography Spot size: - Beam divergence - Mosaicity of the crystal - Distance sample-detector - Point spread function of detector Diffracted beam θ X-ray Detector Diffraction pattern Crystal rotation degree for complete data set - Currently: Discrete rotation, integration over certain rotation angle - Future: Continuous rotation, integration determined by detector frame rate ( Fine phi slicing) Crystallized Protein Resolution: 2d sin( θ ) = λ For d=1a and λ=1a, θ=60 o Beam Beam Energy: kev Intensity: ~10 /s Focal spot size: 2 Adjustable to 25 x 15 µ m Divergency:150 µrad x 28 µrad (FWHM) Diffraction data - reflect crystal symmetry group - orientation of the crystal-> 4 orientation matrix - High dynamic range: >10 between strong and weak reflections - Intensities need to be determined accurately (1%) - Determination of amplitudes and phases leads to electron density maps Detector requirements: 2 - Large area (40 x 40 cm) and/or large number of pixels - Detect a high number of reflection orders (>500) - Accurate determination of integrated intensities - Wide dynamic range (>16 bit, i.e. single photon counting detector) - Fast readout (<0.1s)

3 Pixel Detectors: Principle Si pn-junction Al X-rays 3.6 ev to create 1 eh-pair p+ n+ E drift - + V bias n++ Detector 0.2 mm Pixel Sensor X-rays 0.3 mm 0.2 mm Sensor Pixel Read-out Chip Radiation hard Chip Bump Bonds Pixel electronics Bump Pad Cal Treshold correction CS Amp 1.7fF Global Tresh - Comp + Enable/ Disable Analog Block Ext/Comp Clock Ext Clock Φ 12 Clock Gen Digital Block 15 bit SR counter Reset RBI RBO

4 The SLS Pixel Detector & Size: 40 x 40 cm 2 (0.16m 2 ) & 2000 x 2000 pixels & Pixel size: 200 x 200 µm 2 & Modular detector -> dead area ~6% & High frame rate: >10Hz & High duty cycle: <6% (T ro ~6ms) & In operation: (1000x1000) Base plate (water cooled) Bank with 5 modules Modules with 16 chips

5 SLS Pixel Module Sensor Wire bonds Read-out chips High density flexible capton interconnect Base plate Al support Module Control Board MCB Cable

6 Module Geometry Sensitive Area Horizontal Vertical Total Pixel size mm 0.04 mm^2 Chip Nr of pixels Chip size mm mm^2 Sensor Nr of Pixels Nr of double pixels Sensor active area Module outside dim mm mm^2 Sensor Pixels Readout chip Readout chip Readout chip Readout chip Chip Pixels

7 Main parameters Read-out electronics! Low noise analog block (ENC tot < 100 e-)! Shaping time t sh = 100 ns -> 1MHz! Radiation tolerant! power consumption <100 µw/pixel! Robust comparator! Individual threshold adjustment! Low overall threshold variation (σ < 100e-)! 15 bit pseudo random counter! Large size (20 x 10 mm 2 ) Prototypes Name Size Pixel Architecture Chip Subm. Receiv. Architecture SLS01 8x2 array Analog, comparator, - Dez 98 April 99 counter SLS02 22 x 30 Analog, comparator!, Indiv. May 99 Nov 99 counter, trimbits Coloumn architectur SLS03 1 x 90 As SLS02, final length - Aug 99 Mar 00 column SLS04 22 x 30 As SLS02 but with As SLS02 Dez 99 Exp May 00 correct comparator SLS05 30 x 30 As SLS04, improved trimbit mechanism SLS06 (Final chip) Indiv. Pixel Architecture (Yield tolerant design) Feb 00 Exp July x 85 As SLS05 As SLS05 Exp Oct 00 Exp Feb 01

8 Pixel Layout Designed in radiation hard DMILL technology (R. Baur, Ch. Brönnimann) Size: 200 x 200 µm 2 Bump Pad 15 bit semi-static pseudo random counter+ control logic Low noise preamp (folded cascode) Shaper Threshold trimming (3 Bits) AC-coupled comparator Size 200 x 200 µm

9 SLS02 Architecture 15Bit Counter Column1 Pixel 30 Analog Vcal 1.5f 200f Pad Pr comp clk 10f Mode Icomp 20f 200f 100f Sh Phi1 Clockgen Comp LS + Dis Pixel Column22 DIS Mode Phi2 Pixel1 previous Xor ds_shift ds_shift ds_shift ds_shift ds_shift ds_shift Bit1 Bit2 Bit3 Bit13 Bit14 Bit15 next Xor CLK OUT CLK Mode Column Control Mode Column Column & & > Control & & > Control & & > In CLK Shift Shift Shift Clock Gen Clock Gen DOUT Clock Gen DIS ChipControl Shift FF Shift Clock gen TBI TCL TBO OUT

10 Pixel: Preamp-Shaper I =I +I comp c trim Vcal 1.7f 10f 20f Preamp Shaper Comp 80f 200f FB 100f FC=folded cascode SF=source follower FB=Feedback FC SF Preamp Shaper t peak ~30ns t ~60ns shape

11 SLS02 Analog Part Results Calibration signal Analog out signal! Noise measurements (without detector):! Amplification: ~60mV/1000e- 100ns/div, Ch1: 100mV/div, Ch2: 50mV/div! Linearity limit: ~6000e (21keV) ENC ~50e- (P=75 µw/pixel, t sh = 100 ns) Analog Output [mv] Noise depence on feedback resistors settings VRF\VRFS y = x Signal charge

12 Pixel: Comparator and trimming AC-coupled comparator with diode feedback simple inverter as comparator comparator biasing done via pn-junction of the diode -> expect lower threshold variations on the chip radiation insensitive low power consumption local Threshold setting global Comp Level shift T1 T2 T3 Dis 100f I=5 b µ A Outc Vtrim Inc I~1 c0 µ A I~0.2 c µ A

13 Comparator Results! Minimum Threshold < 700e -! Threshold variation: 130 e- untrimmed Trimbits SLS04 Threshold trimming: Very low trim currents DVthr [e] Trim1 Trim2 Trim4 Trim7 Power Vtrim [V]

14 SLS03: 2cm long column biased via periphery supplies 1. supply in [V] out [V] [V] VD VD VA VA VSF VC VGND Vsh ±0.00 Vg VC Amplitude [mv] AOUT of Pixel #18 and # Pixel 18 Pixel 90 time [ns]

15 SLS05 Architecture RTIN RΦ1 RΦ2 Row Control Shift Shift Shift Shift Shift Shift Column Control Cal In Clk CS Dis & & > RS&CS & Aout + RS&CS LS { Dis 0: Readout 1: Count In Xor Comp clk + comp 200f XOR VC- 30f Vrfs Sh 200f Clockgen Phi2 10f Vrf Phi1 Pr shift shift shift shift shift Bit1 Bit2 Bit3 Bit4 Bit5 shift shift shift Bit15 Bit14 Bit13 1.5f 100f Pad 15-bit counter Vcomp Pixel Trim bit 1 Trim bit 2 PSEL DIN 1: CS active 0: Selected pixel in cnt mode RTOUT CHSEL Shift CTOUT DCLK EN PSEL CAL Chip Control FF VA- CHSEL Shift Shift CTOUT & VD+ CTIN CHSEL CΦ1 CΦ2 CTOUT DOUT AOUT CHSEL PSEL

16 Final Chip: Yield estimation Yield measurements of SLS02 chip (22x30 pixels): Defects due to dynamic logic (Semi-static SR in Pixels): 3.8x10-4 /bit -> 5.8x10-3 /pixel (Yield for 85 pixel column: 60%) Defects in analog part: 3/19=0.842/chip Yield estimation for 48 x 85 pixel chip XY-Adressing, 133 SR-cells: Analog part bad pixels Expected overall yield 0.28 Binomial Distribution 1.000E+00 Probability 8.000E E E E-01 Sum 0.000E Nr of Pixels working

17 Design of a large read-out chip for protein crystallography: Conclusions Prototype chips with 22x30 pixels are working Simulated final chip with one 20mm long column-> working Dynamic logic in DMILL is a yield killer Design with yield tolerant architecture is a must