PARAMETRIC ANALYSIS OF DFAL BASED DYNAMIC COMPARATOR

Transcription

1 HEENA PARVEEN AND VISHAL MOYAL: PARAMETRIC ANALYSIS OF DFAL BASED DYNAMIC COMPARATOR DOI: /ijme PARAMETRIC ANALYSIS OF DFAL BASED DYNAMIC COMPARATOR Heena Parveen and Vishal Moyal Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Technical Campus, India Abstract In Complementary Metal Oxide Semiconductor (CMOS) technology, the advancement in manufacturing of semiconductor processing has changed the designing challenges for the researchers. The challenges that are now being vital are high speed and low power computing devices. This paper presents a novel dynamic comparator with DFAL (Diode Free Adiabatic Logic) inverter that employs the principle of adiabatic logic. As compared to the conventional CMOS technique, the adiabatic logic technique shows more promising results. The proposed Comparator, not only provides low power consumption and reduces the delay, but also improves the energy efficiency in comparison to the conventional Comparator. The design has been simulated using Cadence Virtuoso Spectre simulator in gdpk 9nm Technology. Keywords: Conventional Comparator, Adiabatic Logic, DFAL Inverter, Low Power 1. INTRODUCTION Comparators are known to be the most essential building block in Analog-to-Digital Converters (ADCs) as they act as decision making circuits throughout the transition of analog signals into digital signals. Basically, Comparators compare one input voltage signal against another voltage signal and a binary output signal is produced as per the comparison. Comparators which fall under the classification of regenerative comparators have a wide use in high speed Analog-to-Digital Converters [1] due to their lesser power dissipation, high speed, and no static power consumption. However, certain device mismatch [2] such as parasitic node capacitance, current factor β, and threshold voltage limits the accuracy of such comparators. Also, they cause random offset voltage in comparators which degrade their performance. Using offset cancellation or calibration techniques [3-5] while implementing comparator is also an effective methodology to improve this issue. Furthermore, reduction in the offset voltage can be done by means of a preamplifier in the design of comparator, thereby requiring more consumption of power and more complex design. As the power that has been consumed in conventional CMOS circuits is directly proportional to the circuit load capacitance and the square of the supply voltage [6], most of the researchers are focussing on supply voltage scaling and reducing the circuit load capacitance so that the power consumption can be reduced. For supply voltage scaling, the threshold voltage (V t) of transistor should be proportionally scaled down, but sub-threshold leakage current increases with reduction in threshold voltage (V t). The circuit load capacitance could be further minimized by a reduction in the device sizes but this will somehow affect the driving capability and speed of the circuit. Due to these limitations, in the present scenario, adiabatic logic circuits [7] are being considered for reducing the power consumption. These circuits are based on energy recovery principle, i.e. reusing the energy which is stored in the circuit load capacitance instead of following the usual means of discharging the circuit load capacitance to the ground and wasting the energy. Also, they provide better results than conventional CMOS circuits. So far, several adiabatic circuits have been presented [8]-[1] but these circuits suffer from large delay, complex circuitry, and degradation of output amplitude. To overcome the drawbacks related to diode based adiabatic circuits, 2PASCL [11] circuits were introduced which does not include diodes in its path of charging. Moreover, instead of sinusoidal or ramp power clocks, they use split level sinusoidal power clocks which charges and discharges the circuit capacitance relatively slower than other adiabatic power clocks. Although 2PASCL has an advantage of providing low power dissipation, minute current leakage exists in the circuit as gates are slowly switched ON. Also, 2PASCL circuits suffer from the problem of floating output node because of alternating hold mode in its functioning. DFAL (Diode Free Adiabatic Logic) [12] based circuits not only eliminates the problem of diode based circuits but also reduces the problem of 2PASCL circuits and thus have gained the attraction of many researchers as they offer more promising results. This paper presents a novel dynamic comparator with DFAL inverter that not only utilizes low power [13] but also has less delay. The primary aim is to amend the overall performance in comparison to the conventional dynamic comparator without making the circuitry complex. The paper describes the structure and functioning of the Conventional Comparator in section 2 and includes the operation of DFAL based Comparator in section 3. Simulation results and analysis are addressed in section 4 and are followed by conclusion in section DYNAMIC COMPARATORS Comparators are often described as Clocked comparators. Regenerative feedback is generally used in Comparators and hardly ever in non-clocked comparators. The conventional dynamic comparator which has a wide use in analog-to-digital converters is shown in Fig.1. Its working procedure is explained as follows: Comparators have two modes of operation- reset and evaluation phase. These operating modes operate according to the clock input that is provided to the circuit. When clock input is LOW in reset phase, transistor Mtail will be in OFF state. The reset transistors (M 5 and M 6) will become ON and will pull both the output nodes (i.e. Out n and Out p) to voltage V dd for initiating the starting condition. During the evaluation phase, when the clock input becomes HIGH, transistors M 5 and M 6 will become OFF and simultaneously M tail will be ON due to which Out n and Out p which were at V dd will start falling with different rates of discharging. 354

2 ISSN: (ONLINE) ICTACT JOURNAL ON MICROELECTRONICS, APRIL 217, VOLUME: 3, ISSUE: 1 Fig.1. Conventional Comparator The case when V INP is found to be greater than V INN, here the voltage at Out p will discharge faster than that of Out n. Since the voltage at the node Out p is discharged by the drain current of transistor M 2, the voltage will fall down to V dd V thp before the voltage at node Out n is discharged by the drain current of M 1, as a result of which transistor M 7 will be ON. Consequently, the backto-back inverters will begin the latch generation and the voltage at node Out n will become V dd and the voltage at node Out p will fall down to the ground. The case when V INN is found to be greater than V INP, the circuit will work in a vice versa manner. The proposed comparator operates in two modes evaluation and hold. In the evaluation mode, V 1 will go high and V 2 will go low, whereas in the hold mode, V 1 will go low and V 2 will go high. During the evaluation mode, when the voltage given to the circuit is LOW, transistor M 11 will be in OFF state while the transistors M 7 and M 8 will be in ON state. The transistors M 7 and M 8 are responsible for driving the DFAL inverters. When M 7 and M 8 are turned ON, M 9 and M 1 also turns ON and thus will charge the load capacitances C L resulting in a HIGH state at the output nodes (i.e. Out n and Out p). Conversely, when the applied voltage is HIGH, transistor M 11 will become ON and transistors M 7 and M 8 will become OFF which in turn will turn OFF the pmos transistors (M 9 and M 1) and turns ON the nmos transistors (M 3, M 4, M 5 and M 6). Thus, the discharging process and the charges to be recycled to the power clock (V 2) will occur through nmos transistors (M 3, M 4, M 5 and M 6) resulting in a LOW state at the output nodes (i.e. Out n and Out p). In the hold mode, when the voltage given to the circuit is LOW and nmos transistors (M 3, M 4, M 5 and M 6) turns ON, no transition will occur at the output, i.e. the output will remain low. The same process happens when the applied voltage to the circuit is HIGH and pmos transistors (M 9 and M 1) turn ON. Because of the hold mode, dynamic switching reduces and hence energy dissipation can also be reduced. 3. PROPOSED DYNAMIC COMPARATOR The structure of the proposed dynamic comparator with DFAL inverter is shown in Fig.2. The primary motive of the project is reducing the consumption of power and delay of the conventional dynamic comparator by a certain level, by replacing its back-to-back inverter with a DFAL inverter that shows lower power consumption and less delay than the CMOS inverter. 3.1 CIRCUIT OPERATION The proposed dynamic comparator consists of two split level sinusoidal power clock supply voltages V 1 as well as V 2 where one of the clocks will be in phase whereas the other one will be inverted. The voltage level of V 1 exceeds V 2 by V 1/2, which will minimize the voltage difference between the electrodes and this will result in the reduction of power dissipation. The power clocks described in the operation of the proposed comparator are composed of DC as well as sinusoidal components and can be expressed as shown in Eq.(1) and Eq.(2) respectively. Vdd 3 V1 sin t Vdd 4 4 (1) Vdd 1 V2 sin t Vdd 4 4 (2) Fig.2. Comparator Technology Simulator Table.1. Specifications for simulation Cadence gdpk 9nm CMOS Cadence Virtuoso Spectre MOS Dimensions W=12nm/L=1nm for all circuits Supply Voltage Clock Frequency 3V Two times the input frequency 4. SIMULATION RESULTS AND DISCUSSION The Comparator and Conventional dynamic comparator are designed and simulated using Cadence Virtuoso Spectre simulator in gdpk 9nm Technology at a supply voltage of 3V. The simulated waveform verifying the working of the proposed comparator with DFAL inverter is shown in Fig

3 HEENA PARVEEN AND VISHAL MOYAL: PARAMETRIC ANALYSIS OF DFAL BASED DYNAMIC COMPARATOR Fig.3. Simulation results of Comparator 4.1 POWER EFFICIENCY AND DELAY BY VARYING THE FREQUENCY In order to verify the functioning of the proposed circuit, simulation of both proposed dynamic comparator and the conventional dynamic comparator has been done and their delay and power are measured and compared with varying frequency. The input frequency and clock frequency are varied at the same time from 1MHZ to 1 and the load capacitance has been set to 5fF. The clock frequency has been taken two times the input frequency and the power dissipation and delay are calculated for 1 clock cycles of charging and discharging and are shown in Fig.4 and Fig.5 respectively. It may be observed that with the increase in frequency, the power dissipation of both the comparators (dynamic and the proposed one) increases, whereas the proposed dynamic comparator (with DFAL inverter) has a lesser power dissipation in each of the frequency as compared to the conventional dynamic comparator although a continuous reduction in delay has been observed for both the comparators with varying frequency. So, from the above analysis, it is clear that with the improvement in power and speed of the proposed comparator, the overall PDP (Power Delay Product) has also been improved in comparison to the conventional dynamic comparator. This indicates that the proposed dynamic comparator with DFAL inverter can be utilized for a wide frequency range with an improved performance than the dynamic comparator with CMOS inverter. 4.2 POWER EFFICIENCY AND DELAY BY VARYING THE LOAD CAPACITANCE In order to verify the driving capability of the proposed comparator against the conventional dynamic comparator, extra load capacitance has been added one by one at the output node from 2fF to 2fF. The input frequency and clock frequency are kept constant at 4 and 8 respectively. Then, the power and delay are calculated for 1 clock cycles of charging and discharging and are shown in Fig.6 and Fig.7 respectively. When the capacitive load is increased gradually from 2fF to 2fF, the power dissipation of the proposed, as well as dynamic comparator, increases correspondingly and it can be clearly noticed that at each stage of varying load capacitance, the proposed comparator has better efficiency than the conventional dynamic comparator. While the load capacitance increases, it can be noticed that the delay at the output of each comparator also increases and thus a significant enhancement can be observed in the overall PDP (Power Delay Product) for the proposed dynamic comparator against the conventional dynamic comparator. The power, delay, energy saving percentage and adiabatic gain with respect to load capacitance and frequency of proposed and conventional dynamic comparator based on DFAL and CMOS inverters respectively has been estimated and are shown in Table.2 and Table.3 respectively. As a comparison parameter, we have used adiabatic gain which can be illustrated as the ratio of the energy dissipated per operation of a conventional CMOS circuit and its corresponding adiabatic circuit. It can be noticed that the proposed dynamic comparator offers an energy saving of almost 9% and adiabatic gain of around 1.5 at all observed load capacitances and frequencies Frequency () Fig.4. Power Dissipation of the Comparators with frequency Frequency () Fig.5. Delay of the Comparators with frequency Load Capacitance (ff) Fig.6. Power Dissipation of the Comparators with Load Capacitance 356

4 ISSN: (ONLINE) ICTACT JOURNAL ON MICROELECTRONICS, APRIL 217, VOLUME: 3, ISSUE: Fig.7. Delay of the Comparators with Load Capacitance Table.2. Comparison of Power Dissipation, Delay and Power Delay Product (PDP) with varying load capacitance at input frequency= 4 and clock frequency = 8 in 1 clock cycles of charging and discharging Comparators 2fF 1fF 15fF 2fF PDP (pj) Energy Saving (%) Adiabatic Gain Table.3. Comparison of Power Dissipation, Delay and Power Delay Product (PDP) with varying frequency at 5fF in 1 clock cycles of charging and discharging Comparators PDP (pj) Energy Saving (%) Adiabatic Gain Load Capacitance (ff) CONCLUSION A novel DFAL based Comparator has been presented. The main intention behind this proposed theory is to present a low-power energy efficient and high performance dynamic comparator with a DFAL based inverter. The conventional and proposed design of dynamic comparator has been simulated and analyzed. The design has been simulated using Cadence Virtuoso Spectre Simulator in gdpk 9nm technology at 3V supply voltage. The results of simulation and evaluation of performance comparison show that the proposed dynamic comparator is more power efficient than the conventional dynamic comparator. Also, the delay and PDP (Power Delay Product) of the proposed dynamic comparator are considerably lower as compared to the conventional dynamic comparator. Thus, an energy saving of almost 9% and adiabatic gain of around 1.5 at all observed load capacitances and frequencies has been offered by the proposed dynamic comparator. In high speed ADCs and other VLSI applications, the Comparator would be very effective. REFERENCES [1] V. Deepika and Sangeeta Singh, Design and Implementation of A Low Power, High Speed Comparator, Procedia Materials Science, Vol. 1, pp , 215. [2] Jun He, Sanyi Zhan, Degang Chen and Randall L. Geiger, Analyses of Static and Random Offset Voltages in Comparators, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 56, No. 5, pp , 29. [3] Islam T. Abougindia, Ismail Cevik, Fadi N. Zghoul and Suat U. Ay, A Precision Comparator Design with A New Foreground Offset Calibration Technique, Analog Integrated Circuits and Signal Processing, Vol. 83, No. 2, pp , 215. [4] Takayuki Okazawa, Ippei Akita and Makoya Ishida, A Digitally Calibrated Comparator using Time- Domain Offset Detection, Analog Integrated Circuits and Signal Processing, Vol. 81, No. 3, pp , 214. [5] Masaya Miyahara, Yusuke Asada, Daehwa Paik and Akira Matsuzawa, A Low-Noise Self-Calibrating Comparator for High-Speed ADCs, Proceedings of IEEE Asian Solid-State Circuits Conference, pp , 28. [6] N.H.E. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 3 rd Edition, Pearson Education, 211. [7] Philip Teichmann, Fundamentals of Adiabatic Logic, Adiabatic Logic, Vol. 34, pp. 5-22, 212. [8] Irfan Ahmad Pindoo, Tejinder Singh, Amritpal Singh, Ankit Chaudhary and P. Mohan Kumar, Power Dissipation Reduction Using Adiabatic Logic Techniques for CMOS Inverter Circuit, Proceedings of IEEE 6 th International Conference on Computing, Communication and Networking Technologies, pp. 1-6, 215. [9] Yong Moon and Deog Kyoon Jeong, An Efficient Charge Recovery Logic Circuit, IEEE Journal of Solid-State Circuits, Vol. 31, No. 4, pp ,

5 HEENA PARVEEN AND VISHAL MOYAL: PARAMETRIC ANALYSIS OF DFAL BASED DYNAMIC COMPARATOR [1] Yibin Ye and Kaushik Roy, QSERL: Quasi-Static Energy Recovery Logic, IEEE Journal of Solid-state Circuits, Vol. 36, No. 2, pp , 21. [11] N. Anuar, Y. Takahashi and T. Sekine, Two Phase Clocked Adiabatic static CMOS Logic and its Logic Family, Journal of Semiconductor Technology and Science, Vol. 1, No. 1, pp. 1-1, 21. [12] Shipra Upadhyay, R.A. Mishra, R.K. Nagaria and S.P. Singh, DFAL: Diode-Free Adiabatic Logic Circuits, ISRN Electronics, Vol. 213, pp. 1-12, 213. [13] Heena Parveen and Vishal Moyal, Implementation of Low Power Adiabatic based Inverter for Comparator, International Journal of Science and Research, Vol. 6, No. 1, pp ,