Low-Power Comparator Using CMOS Inverter Based Differential Amplifier

Transcription

1 Low-Power Comparator Using CMOS Inverter Based Differential Amplifier P.Ilakya 1 1 Madha Engineering College, M.E.VLSI design, ilakya091@gmail.com, G.Paranthaman 2 2 Madha Engineering college, Asst. Professor, E.C.E Dept, paranthaman@gmx.com. Abstract As per the Moore s law, there is an extreme increase in the number of on chip devices, this will increase the chip density results in power dissipation and thus the power utilization is unsatisfied. So to avoid this problem, the Low Power System arises. As a part of microelectronics, it's been proposed to make the choice of minute circuit with attraction added by use of MOS cells. Since we often use an operational amplifier in our specialty, we chose to recreate a comparator of CMOS cell design.in such situation we have to use the higher speed and the lowest power consumption based comparators. Nowadays, differential amplifier is widely employed in many circuits. If we reduced the power consumption of a single differential amplifier the power consumption of the whole circuit will be considerably minimized. In this paper, we are presenting lowest power and high speed comparators using, an inverter based differential amplifier, even in small supply voltages. This comparator design having the small count of transistors which is used to reduce the delay time. Thus, this paper is to design an advanced differential amplifier circuit using CMOS technology with lesser power consumption & delay. Thus the Post-layout simulation, analyze the results in a 0.18-μm CMOS technology. This design could be done through the TANNER EDA tools. Index Terms dynamic clocked comparator, inverter based differential amplifier, higher speed analog- to- digital comparator (ADCs), low power analog design. I. INTRODUCTION COMPARATOR is one of the fundamental building blocks in most analog-to-digital converters (ADCs). Much higher speed ADCs, such as ash ADCs, require higher-speed, low-power comparators with small chip area. Higher-speed comparators in ultra deep sub micrometer (UDSM) CMOS technologies suffer from low supply voltages, especially which is to consider the fact that threshold voltages of the devices not been scaled at the same pace as the supply voltages of the modern CMOS processes [1]. Hence, designing high-speed comparators is more challenging when the supply voltage is low. In other words, in a given technology, to achieve high speed, larger transistor are required to compensate the reduction of supply voltage, which also means that more area and power is needed. Low-voltage operation results in limited commonmode input level, which is mainly in many high-speed ADC architectures. Dynamic comparators have been presented for various architectures. Further, based on the double-tail structure proposed in [10], a new dynamic comparator is presented, which doesn t require boosted voltage or stacking of the too much transistor. Merely by adding a few minimum-size transistor to the a conventional doubletail dynamic comparator, latch delay time is reduced. This modification results also considerable power savings when compared to the conventional dynamic comparator and inverter based differential amplifier.the proposed comparator of [7] works down to a supply voltage of 0.5 V with a maximum clock frequency of 500 MHz and consumes 16 µw. Despite the effectiveness of these approaches, the effect of component mismatch in the additional circuitry on the performance of the comparator should be considered. The structures of double-tail dynamic comparator proposed in [10] is based on designing a separate input and cross-couple stages. This separation enables fast operation over a wide common-mode and supply voltage range. II. EXISTING DOUBLE-TAILCOMPARATOR Fig. 1, demonstrates the Schematic diagram of the double-tail comparators. Due to the better performance of double-tail architecture of a low - voltage application, the proposed comparator is designed based on the double-tail structure. The main idea of the comparator is to increase VFinn / fp in order to increase the latch regeneration speed. For this purpose, two control transistor (Mc1 and Mc2) has been added to the reset stage in parallel to M3/M4 transistor but in a cross-coupled manner. In the past, pre-amplifier based comparators been used for ADC architectures such as flash and pipeline. The main drawbacks of pre-amplifier based comparators is the more Offset voltage. To overcome this problem, dynamic comparator are often used that make a comparison once every clock period and require much less offset voltage. However, these dynamic comparator suffers from large power dissipation compared to pre-amplifier based comparator. The main problem with all these dynamic comparator is the output signal of the latch stage is fluctuating during clock transition.this is happening due to the presence of noise in input terminals. 91

2 The tans' - conductance of the latch is increased. In other words, positive feedback is strengthened. Hence, the latch will be Delay = t0 + latch Latch = CL out on VoutV0gm, if + gmr1, IV. CMOS INVERTER BASED DIFFERENTIAL AMPLIFIER The CMOS inverter-based differential amplifier topology in fig 3.uses two CMOS inverters as the amplifier input. This input stage design the advantage of combining the trans-conductance of the n and p transistor design. Fig 1. Schematic of existing double-tail comparator III. OPERATION OF THE EXISTING DOUBLE-TAIL DYNAMIC COMPARATOR The operation of the comparator is as follows, During reset PE (CLOCK = 0, Mtail1 and Mtail2 are off, to avoid static power), M3 and M4 pulls both Finn and fp nodes to VDD, therefore transistor Mc1 and Mc2 are cut off. In between the stage transistors, M1 and M2, reset both outputs to ground. During decision-making PE (CLOCK = VDD, Mtail1, and Mtail2 are on), transistors M3 and M4 turn off. Furthermore, at the beginning of the control transistor is still off (since Finn and fp are about VDD). Thus, Finn and fp start to drop with different rates according to the input voltages. Suppose VINP > VINN, thus Finn drops faster than fp. As long as Finn continues falling, the PMOS control transistor (Mc1 in this case) starts to ON, pulling fp node back to the VDD, so another control transistor (Mc2) remains off, allowing Finn to be discharged completely. In other words, unlike the a conventional double-tail dynamic comparator, in which VFinn/fp is just a function of input transistor trans-conductance and the input voltage difference (9), in the structure as soon as the comparator detects that, for instance node Finn discharges faster, a PMOS transistor(mc1) turns on, pulling back to the VDD. To overcome this issue, two NMOS switches are used below the input transistor [Msw1 and Msw2]. Fig 2. Schematic of existing double-tail dynamic comparator Fig 3. Inverter based amplifier design This combination of the two trans-conductances should provide 6db, increases in gain over a traditional common source, amplification stage, with approximately the same DC bias current. When this architecture is implemented with a standard supply voltage (>2vt), the overall trans-conductance can be increased significantly depending on how transistors in the inverters are sized and the resulting current through the inverter. Higher current through the inverter allows significantly higher bandwidths to be achieved. Another advantage of this topology is an increase in output swing and linearity when compared to a traditional common source or cascade amplifier if the respective trans-conductance of the p and n type transistor are approximately equal in magnitude. For noise, the inverter-based topology offers lower equivalent noise resistance compared to the equivalent common source topology. V. INVERTER BASED AMPLIFIER CIRCUIT: A Differential amplifier circuit is a special type of amplifier that two inputs and two outputs. This circuit, PMOS transistor MP acts as the load of the driver NMOS transistor MN, and vice versa. That is, each transistor acts as the load of the other. This device amplifies input signals on the two input lines that are out of and rejects input signals that a commoner such as induced noise. The CMOS differential amplifier is used for various applications because of the number of advantages can be derived from these types of amplifier, as compared to a single ended amplifier. Differential amplifier is used where linear amplification a minimum of distortion is desired. 92

3 Fig 4. Schematic diagram of proposed comparator Where gmc1, 2 is the trans-conductance of the controlling transistors. So, the input-referred offset voltage due to the Mc1,2. V i <V DD, V TP <0, V o -V DD <0. VI. PROPOSED COMPARATOR DESIGN The new approach of analog circuit techniques that is compatible with future CMOS technologies. There are several important advantages of this approach. First, the need to develop expensive CMOS technologies with lower threshold voltages is avoided. Secondly, higher efficiency DC-DC converters are not required. Thirdly, circuit techniques that permit low voltage operation with large thresholds offer the potential for more fully utilizing the technology at higher voltage and at lower voltage if, in fact, low threshold technologies do become standard technologies. The main purpose of the input stage is to amplify differential signals and reject common-mode input voltages. An important specification of an input stage is the common mode input range. If the common mode voltage is kept within this range, the input stage will properly respond to small differential signals. Hence an application to be designed such that the common mode input voltage stays within the common-mode zinput range. Other important specifications of the input stage are the referred noise, offset, and the common-mode rejection. The active load consists of cross-coupled inverter pair which a great impact on improving the gain of the circuit. Sub-threshold conduction is only one component of leakage, other leakage components that can be roughly equal in size depending on the device design are gateoxide leakage and junction leakage. Understanding sources of leakage and solutions to tackle the impact of leakage will be a requirement for most circuit and system designers. V (2) /VIN = E+01 INPUT RESISTANCE AT VIN = 1.000E+20 OUTPUT RESISTANCE AT V (2) = 2.536E+05 To reduce the sub-threshold effect here we design the inverter based differential amplifier. The phase margin PM is the distance of the phase angle at the unity gain frequency with respect to 180 (in the non-inverting amplifier case) or with respect to 0 (in the inverting amplifier case). In our case this is with respect to 0. That is, the phase angle of the transfer function A(s) at the unity gain 93 frequency or the gain bandwidth frequency is also the phase margin, PM. For the MN transistor: V GSN = V i - V SS, V DSN = V o - V SS. Therefore V i = V GSN,, and V o = V DSN For the MP transistor: V GSP = V i - V DD, V DSP = V o - V DD. Therefore V i = V GSP,, and V o = V DSP VII. PERFORMANCE EVALUATION A.Effect of Threshold Voltage Mismatch of MC1, MC2,i.e., The differential current due to the threshold voltage mismatch can be obtained from I dig = gmc1, 2 VThc1, 2 Where gmc1, 2 is the trans-conductance of the controlling transistor. So, the input-referred offset voltage due to the Mc1,2. B. Kickback Noise Principally in latched comparators, the large voltage variation on the regeneration nodes are coupled, through the parasitic capacitances of the transistor, to the input of the comparator. Since the circuit preceding it does not zero output impedance, the input voltage is disturbed, which may degrade the accuracy of the conversion. This disturbance is usually called kickback noise. In [11], it's been shown that the fastest and most powerful efficient comparators generate more kickback noise. This is true about our proposed dynamic comparator. Although it improves the double-tail VThC1. VIII. SIMULATION RESULTS This work presents that comprehensive delay analysis for clocked dynamic comparators. Two common structures of the conventional dynamic comparator and conventional double- tail dynamic comparators have been analyzed. A new dynamic comparator with low-voltage, low-power capability has been proposed in order to improve the performance of the comparator and also reduces the delay. The area estimation is evaluated using post layout simulation in 0.18-µm CMOS technology with VDD = 1.2 V. The delay and the energy per conversion of the mentioned dynamic comparators versus supply voltage variation in comparison with the other two structures, the delay of the proposed double-tail dynamic comparator is significantly reduced in low-voltage supplies. It is obvious that at higher supply voltages, all structures approximately.. However, by decreasing the supply voltage, three structures start to be deferred. It is evident that the double-tail topology can operate faster and can be used in lower supply voltages, while consuming nearly the same power as the conventional dynamic comparator. The case is even much better for the proposed comparator when compared to the other existing comparator. Output of Pre layout simulation of Inverter based Differential Amplifier

4 Comparator structure Technology CMOS Supply voltage(v) Power (W) Delay (ms) INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY COMPARISON TABLE: POWER DISSIPATION Fig 5. Simulation output of proposed comparator It Shows the layout of the comparator. Particular was taken in the layout to avoid affecting delay and power of the comparator. It the delay of 5 ms -1. The Existing Double tail comparator The Existing Double tail dynamic comparator Inverter based differential amplifier 180nm 0.8v 125mW nm 0.8v 84mW nm 0.8v 70mW 5 CONCLUSION Fig 6. Simulation output of existing double tail comparator. Fig 6. Shows the simulation output of the existing double tail comparator and it performs the delay of 7.4ms -1. Fig 7. Simulation output of existing double tail dynamic comparator. It Shows the simulation output of existing double tail dynamic comparator and it performs the delay of 8.7 ms -1. In this the CMOS Inverter-based amplifier design that works with low power consumption when compared to double tail latched comparator and pre-amplifier based clocked comparator. While the idea of inverter based amplifier is not conceptually novel, the idea of better controlling the current through the inverters using the concept of sub-threshold for low power applications, as well as decreases the delay time and common-mode control makes the concept of inverterbased amplifier more practical in real applications, particularly for applications for low power and low supply voltages. The simulation results show that the proposed circuit can operate efficiently with low power dissipation as well as decreases the delay time also. REFERENCES [1] B. Goll and H. Zimmermann, A comparator with reduced delay time in65-nm CMOS for supply voltages down to 0.65, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 11, pp , Nov [2] A. Mesgarani, M. N. Alarm, F. Z. Nelson, and S. U. Ay, Supplyboosting technique for designing very low-voltage mixedsignal circuits in standard CMOS, in Proc. IEEE Int. Midwest Symp. Circuits Syst. Dig. Tech. Papers, Aug. 2010, pp [3] M. Maymandi - Nejad and M. Sachdev, 1-bit quantiser with rail to rail input range for sub-1v modulators, IEEE Electron. Lett., vol. 39,no. 12, pp , Jan [4] S. U. Ay, A sub-1 volt, 10-bit supply boosted SAR ADC design in standard CMOS, Int. J. Analog Integer. Circuits Signal Process. vol. 66, no. 2, pp , Feb [5] B. Goll and H. Zimmermann, A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47μW at 0.6V, in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009,pp [6] D. Shinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, A double-tail latch-type voltage sense amplifier with 18ps Set up+hold time, in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers,. 2007, pp [7] S. Babayan - Mashhadi and R. Lot fi, An offset cancellation technique for comparators using body-voltage trimming, Int. J. Analog Integr. Circuits Signal Process., vol. 73, no. 3, pp , 94

5 Dec [8] J. He, S. Zhan, D. Chen, and R. J. Geiger, Analyses of static and Dynamic random offset voltages in dynamic comparators, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 5, pp , May [9] J. Kim, B. S. Leibo wits, J. Ren, and C. J. Madden, Simulation and analysis of random decision errors in clocked comparators, IEEE Trans. [10] P. M. Figueire do and J. C. Vital, Kickback noise reduction technique for CMOS latched comapartors, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 7, pp , Jul [11] E.Sackinger and W. Guggenbuhl, Design of Fully Differential CMOS Amplifier for Clipping Control Circuit World Applied Science Journal 3(1),pp , [12] "Analysis and design of a low-voltage Low-Power Double-Tail Comparator"Samaneh Babayan-Mashhadi,Reza Lotfi [13] Umamaheswari.V.S.Rajaramya.V.G,"Low Power High Performance Doubletail Comparator" from nternational Journal of Scientific Engineering and Technology 95