Power Reduction in Dynamic Double Tail Comparator With CMOS

Transcription

1 Power Reduction in Dynamic Double Tail Comparator With CMOS Babu Lal Choudhary M. Tech. Scholar Apex Institute of Engineering and Technology, Jaipur, India Vimal Kumar Agarwal Associate Professor Apex Institute of Engineering and Technology, Jaipur, India Abstract:- With the developing interest of computerized converters that are effective in territory, ultra low power and higher in speed has pushed in the heading to utilize dynamic regenerative comparators to improve the proficiency of power and speed and take it to most extreme level. In this paper, a most recent element comparator is recommended, where a few changes are made in hardware of element comparator for speedier working and low utilization control. At the point when some measure of voltage is provided by not expanding the quantity of transistors, there will be more unpredictability in the circuit for minimizing the utilization of static power. At first inverter circuit is wiped out that is in charge of reversal of clock heartbeat. In the following stride two more switches are associated; they minimize the utilization of static power. We are actualizing a 130nm proposed re-enacted dynamic comparator. The result of 0.8V VDD is given as result by the proposed framework. As saw from session of results, the recommended dynamic comparator has the ability of minimizing the deferral and power rather than base paper hardware. Keywords: Clock gating, Double-tail comparator, dynamic clocked comparator I. INTRODUCTION In the branch of electronics, comparator is referred to be a component that put two voltages or currents in comparison to each other & generates a digital signal as outcome and points out the one which is larger in value. It is comprised of two analog input terminals V- & V+ and a binary digital outcome V0. The outcome produced will be V0 = 1, if V > V 0, if V < V... (1) A comparator is comprised of defined differential amplifier with high gain value. They are mainly employed in the devices that compute & digitize analog signals like ADCs (Analog to Digital converters) and relaxation oscillators as well. A. Differential Voltage The differential voltages must lie in the area as characterized by makers. The coordinated comparators of before times, for example, LM111 family and some fast comparators, for example, LM119 family require differential voltages to be lower in esteem than the provided voltage (±15 V versus 36 V).[1] The differential voltages in rail-to-rail comparators ought to stay in the scope of force supply. When they are powered through a bipolar (dual rail supply), or, when supplied power through a uni-polar TTL/CMOS power supply: Vs- V+, V- VS+...(2) 0 V +, V - V cc... (3) Specified rail-to-rail comparators comprising p-n-p input transistors, such as in LM139 family, it allows input potential to get drop up to 0.3V down to negative rail supply, but don t let it to go more than positive rail [2]. Précised ultra-fast comparators such as LMH7322, let the input signal to be swing down to negative rail & above positive rail though by the margin of 0.2V only [3]. Differential input voltage (which is the voltage in two inputs) of a latest rail-to-rail comparator is generally confined by full swing of power supply. Volume 7 Issue 3 October

2 B. Op - Amp Voltage Comparator Fig 1:- A simple op-amp comparator An op-amp (operational amplifier) is having a maintained differential input & high value of gain. This goes along the features of comparators & can be replaced in the components where there is a need of lower performance [4]. Hypothetically, a fundamental operation amp works in open circle format (without having negative input) that can be utilized as a comparator with lower execution. At the point when non-modifying input (V+) works over high voltage esteem than upsetting information (V-), the higher pick up of operation amp prompts immersion of most elevated estimation of positive voltage that can be delivered as result. As the estimation of non-rearranging input (V+) gets down than transforming input (V-), the result gets immersed over the most negative voltage which can be delivers as result. There is a confinement over yield voltage of operation amp by provided voltage. The exchange capacity of an operation amp working in straight state along a negative input that utilizations directed split voltage control supply is composed to be: Vout = A0 (V1 - V2). However, this condition can't be connected to non direct hardware of a comparator and working in an open circle (without negative criticism). For all intents and purposes, there are great deals of drawbacks in applying an operation amp as comparators as opposed to a predetermined comparator as it were [5]. OP-amps are designed to work in linear state along the negative feedback. So, it takes much more time to recover from state of saturation. Most of the op-amps are comprised of integrated compensation capacitor that enforces limitations of slew rate over the signals having high frequency. Simultaneously an op-amp helps in designing sloppy comparator having propagation delays that can last in tens of microseconds. As the op-amps are not having any integrated hysteresis, an external hysteresis network is required for input signals moving at a slow speed. The specification of quiescent current in an op-amp is remaining validated in a state where feedback is active. Few op-amps express a raised quiescent current where value of inputs is not equal. A comparator is designed in a manner to generate well limited voltages of output that intimate with the digital logic in an easy manner. There is a need to verify the digital logic compatibility where op-amp is used as comparator. Various multi-sectional op-amps can express high level of channel-to-channel interaction when they are implemented as comparators. Various op-amps are comprised of back-to-back diodes in their inputs. The inputs of op-amps follow one another but this is fine. Though, inputs of comparators are not similar to each other. The diodes can lead to unanticipated currents by the inputs. C. Conventional Dynamic Comparator The organized outline as exhibited in figure 3 as an ordinary element comparator is executed at a vast scale in A/D converters having no such utilization of static power, high estimation of information impedance and rail-torail yield swing [1], [17]. The working of comparator is depicted underneath. In the reset stage where CLK = 0 and Mtail is off, yield hubs Outn and Outp are pulled by the VDD for framing a begin condition and achieve a substantial rationale state in reset stage. As the CLK + VDD in correlation stage, transistors M7 and M8 are killed and Mtail is on. Yield voltages (Outp, Outn), that are as of now pre-charged to VDD, start releasing over various pace on the premise of related info voltage (INN/INP). For a situation when VINN < VINP, rate of releasing of Outp is more than Outn, so as Outp (which is released by transistor M2 deplete current), boils down to level of VDD Vthp before Outn (released by transistor M1 deplete current), the succeeding PMOS transistor (M5) gets enacted on setting off the lock era that is driven by consecutive inverters (M3, M5) and (M4, M6). Henceforth, Outn pulls to VDD and Outp motivates releases to ground. On the off chance that VINN > VINP, working of hardware will be in Volume 7 Issue 3 October

3 the other way around way. Fig 2:- Conventional Dynamic Comparator for Tanner Fig 3:- Conventional Dynamic Comparator [19] D. Conventional Double-Tail Dynamic Comparator A conventional double tail comparator is appeared in Figure 5 [10]. This outline is having low stacking and thus can work over less voltage supply rather than conventional element comparators. The twofold tail comparator empower both of the bigger current in locking stage and more extensive Mtail2 for quick hooking that is autonomous from info normal mode voltage (Vcm) and little current found in information organize (little Mtail1) for low counterbalance [10]. The working of comparator is clarified beneath, in the reset stage when (CLK = 0,Mtail1, Mtail2 are deactivated), the fp and fn hubs get pre-charged by M3-M4 transistors to the VDD, that leads releasing of MR1 and MR2 transistors yield hubs to ground. In the period of basic leadership (as CLK = VDD, Mtail1 and Mtail2 are initiated), M3-M4 are deactivated and voltages over fp and fn begin dropping by a rate displayed by IMtail1/Cfn(p) and over top of this, info subordinate differential voltage Vfn(p) will be framed. The transistors MR1 and MR2 shapes a middle of the road express that go through Vfn(p) to cross coupled inverters and additionally protects the information sources and yields that prompts minimizing the kickback noise [10]. Volume 7 Issue 3 October

4 Fig 4:- Conventional Double-Tail Dynamic Comparator Fig 5:- Schematic diagram of the conventional double-tail dynamic comparator [19]. For better performance of a double tail design in applications with low voltages, the suggested comparator is based on double tail architecture. The main motive behind the suggested comparator is to raise the Vfn/fp so that speed of latch regeneration could be increased. To achieve this, two control transistors Mc1 & Mc2 are summed up to first level in parallel to M3/M4 transistors but connected in cross coupling. Operation of Comparator In the reset phase (where CLK = 0, Mtail1 & Mtail2 are deactivated avoiding the state of static power) both of the nodes of fp & fn pull the nodes of M3 & M4 to VDD. Thus, transistors Mc1 & Mc2 are cut off. Both of the latch outputs are reset to ground by the MR1 & MR2 intermediate transistors. In the phase of decision making (as CLK = VDD, Mtail1 & Mtail2 are activated), M3-M4 are deactivated. Further on starting of this phase, the control transistors remain deactivated (as fp & fn are around V DD ). So, fp & fn Volume 7 Issue 3 October

5 start dropping over different rates as per input voltages. It is presumed that VINN < VINP, hence rate of dropping for fp is more than fn (as more current is provided by M2 than M1). Till the time fn keeps falling, associated PMOS control transistor (Mc1) gets activated and pulls the node fp back to VDD while other control transistor (Mc2) remains deactivated and lead to complete discharging of fn. In different wording, as by un-similarity to the traditional double-tail dynamic comparator where V fn/fp is a function only of input transistors trans conductance & input voltage difference, in the design as soon the comparator identifies that rate of discharging if rate of discharging of instance node fn is fast, PMOS transistor (Mc1) is activated and pulls the other node fp to VDD. Fig 6:- Double Tail Comparator So, with the passage of time, the difference observed in fp & fn (Vfn/fp) is increased in an exponential form that leads to minimizing the time period of latch regeneration. In spite of the efficiency of the suggested idea, one point that must be taken into consideration is that in the circuitry, as by control transistor (Mc1) is activated, current is drawn to ground by VDD through input & tail transistor (such as Mc1, M1 & Mtail1) that leads to consumption of static power. For coping up by this problem, two NMOS switches are employed below input transistors Msw1 & Msw2. As the phase of decision making begins. By the fact that fp & fn are pre-charged to VDD (in reset phase), both of switches are closed and fp & fn start dropping with different rates. As the comparator recognize that rate of discharging of either one of the fp/fn is fast, control transistors will take action to rise the voltage difference. It is presumed that fp is pulled to VDD & fn must get discharged thoroughly. Thus, switch implied in path of charging of fp will be opened (to prevent the current drawn from VDD) but other switch linked to fn will get closed to permit the discharging of fn node completely. In different wordings, functioning of control transistors along the switches enumerates the working of latch. II. PROPOSED METHODOLOGY A. Proposed Methodology -1 The schematic diagram of the suggested double tail dynamic comparator is presented in figure 7. By the two NMOS switches (Mn1 & Mn2) are summed up to switching transistors (Msw1 & Msw2) for minimizing the Volume 7 Issue 3 October

6 consumption of static power. The circuitry works in a similar manner to earlier comparator design. This circuitry makes use of power gating methodology for minimizing the consumption of static power. The additional transistors get switched by high input voltage or else remain deactivated & minimize the consumption by sending the static power to ground. Fig.7. Schematic diagram of the proposed double tail dynamic comparator B. Proposed Methodology- 2 Fig8 :- Proposed Double tail Dynamic comparator In this technique, we limit the amount of transistors. We are applying inverter circuitry for inversion of Volume 7 Issue 3 October

7 input clock pulse through the PMOS transistor as marked by Red circle in figure 9. In the suggested technique, the inverter circuitry is removed & PMOS is replaced by NMOS. This technology has the ability to minimize the consumption of power & area of circuitry. Fig 9 :- Dynamic Double tail comparator In the figure 10, PMOS & inverter circuitry are replaced by NMOS. (Marked as a red circle). Fig 10 :- Propose Dynamic Double tail comparator. A. Conventional Dynamic Comparator III. RESULTS A conventional dynamic comparator is the structure where two voltages are put in comparison, input Volume 7 Issue 3 October

8 voltage is 0.8V & outcomes of Vp & Vn voltages are compared. Initially, Vp > Vn, Vp = 0.8V & Vn = 0.7V. Fig 11: - Conventional dynamic comparator As observed from conventional dynamic comparator waveform, rate of discharging of outn is more than outp. The consumption of power for dynamic comparator is e-007 watts. B. Conventional Double-Tail Dynamic Comparator Fig 12:- Waveform for Conventional dynamic comparator The conventional double tail dynamic comparator is that layout where two voltages are compared, where input voltage is 0.8V & we compare the Vp & Vn in comparison. Initially, Vp > Vn is considered. Vn = 0.7V and Vp = 0.8V. In this layout, some substitution transistors are implemented. The consumption of power by conventional double till dynamic comparator is calculated as e-007 watts. Fig 13: - Conventional Double-Tail Dynamic Comparator Volume 7 Issue 3 October

9 C. Double-Tail Dynamic Comparator Fig 14:- Waveform for Conventional Double-Tail dynamic comparator The double tail dynamic comparator is that layout where two voltages are compared, where input voltage is 0.8V & we compare the Vp & Vn in comparison. Initially, Vp > Vn is considered. Vn = 0.7V and Vp = 0.8V. In this layout, some substitution transistors are implemented. The consumption of power by conventional double till dynamic comparator is calculated as e-007 watts. Fig 15 :- Double-Tail Dynamic Comparator Fig 16: - Waveform of Double-Tail Dynamic Comparator Volume 7 Issue 3 October

10 D. Proposed Double Tail Comparator Fig 17: - Proposed double tail comparator The clock gating Double tail dynamic comparator is that layout where two voltages are compared, where input voltage is 0.8V & we compare the Vp & Vn in comparison. Initially, Vp > Vn is considered. Vn = 0.7V and Vp = 0.8V. In this layout, some additional transistors are implemented. The consumption of power by conventional double till dynamic comparator is calculated as e-007 watts. Fig 18:- Waveform of Proposed double tail comparator Design Conventional Double-Tail Dynamic Comparator Conventional Double-Tail Dynamic Comparator Power Consumption e-007watts e-007 watts Dynamic Comparator e-007 Watts Proposed Double Tail Dynamic Comparator e-007 watts Table 1:- Comparison table Volume 7 Issue 3 October

11 IV. CONCLUSION AND FUTURE SCOPE In this paper, a most recent element double tail comparator is displayed having low voltage and low power capacity for minimizing the utilization of static power by expansion of two exchanging transistors. In the second system the inverter of PMOS outline get supplanted by NMOS according to the figure 9 and 10. The results from post design re-enactment in 0.13-µm CMOS innovation affirms that utilization of force of proposed comparators minimized all things considered. This hardware can be executed in simple to advanced converter plans. By this hardware we can create sense enhancers, operational Trans-conductance intensifier and pre-characterize speaker. Here, work is done to improve the productivity of framework by actualizing GDI and altered GDI approach. GDI can minimize the utilization of static power. GDI can be implemented in clock gating to minimize the utilization of force. REFERENCES [1] B. Goll and H. Zimmermann, A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 11, pp , Nov [2] S. U. Ay, A sub-1 volt 10-bit supply boosted SAR ADC design in standard CMOS, Int. J. Analog Integr. Circuits Signal Process., vol. 66, no. 2, pp , Feb [3] A. Mesgarani, M. N. Alam, F. Z. Nelson, and S. U. Ay, Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS, in Proc. IEEE Int. Midwest Symp. Circuits Syst. Dig. Tech. Papers, Aug. 2010, pp [4] B. J. Blalock, Body-driving as a Low-Voltage Analog Design Technique for CMOS technology, in Proc. IEEE Southwest Symp. Mixed-Signal Design, Feb. 2000, pp [5] M. Maymandi-Nejad and M. Sachdev, 1-bit quantiser with rail to rail input range for sub-1v modulators, IEEE Electron. Lett., vol. 39, no. 12, pp , Jan [6] Y. Okaniwa, H. Tamura, M. Kibune, D. Yamazaki, T.-S. Cheung, J. Ogawa, N. Tzartzanis, W. W. Walker, and T. Kuroda, A 40Gb/ s CMOS clocked comparator with bandwidth modulation technique, IEEE J. Solid-State Circuits, vol. 40, no. 8, pp , Aug [7] B. Goll and H. Zimmermann, A 0.12 µm CMOS comparator requiring 0.5V at 600MHz and 1.5V at 6 GHz, in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2007, pp [8] B. Goll and H. Zimmermann, A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47µW at 0.6V, in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp [9] B. Goll and H. Zimmermann, Low-power 600MHz comparator for0.5 V supply voltage in 0.12 µm CMOS, IEEE Electron. Lett., vol. 43, no. 7, pp , Mar [10] D. Shinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, A double-tail latch-type voltage sense amplifier with 18ps Setup+Hold time, in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2007, pp [11] P. Nuzzo, F. D. Bernardinis, P. Terreni, and G. Van der Plas, Noise analysis of regenerative comparators for reconfigurable ADC architectures, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp , Jul [12] A. Nikoozadeh and B. Murmann, An analysis of latched comparator offset due to load capacitor mismatch, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 12, pp , Dec [13] S. Babayan-Mashhadi and R. Lotfi, An offset cancellation technique for comparators using body-voltage trimming, Int. J. Analog Integr. Circuits Signal Process., vol. 73, no. 3, pp , Dec [14] J. He, S. Zhan, D. Chen, and R. J. Geiger, Analyses of static and dynamic random offset voltages in dynamic comparators, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 5, pp , May [15] J. Kim, B. S. Leibowits, J. Ren, and C. J. Madden, Simulation and analysis of random decision errors in clocked comparators, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 8, pp , Aug [16] P. M. Figueiredo and J. C. Vital, Kickback noise reduction technique for CMOS latched comapartors, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 7, pp , Jul [17] B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, Yield and speed optimization of a latch-type voltage sense amplifier, IEEE J. Solid-State Circuits, vol. 39, no. 7, pp , Jul [18] D. Johns and K. Martin, Analog Integrated Circuit Design, New York,USA: Wiley, [19] Samaneh Babayan-Mashhadi," Analysis And Design Of A Low-Voltage Low-Power Double-Tail Comparator", Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, Vol. 22, No. 2, February 2014 Volume 7 Issue 3 October