Mixed signal systems and integrated circuits

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1 005 10/13 Mixed signal systems and integrated circuits Akira Matsuzawa Tokyo Institute of Technology 005/10/13 Mixed Signal ADC Matsuzawa 1

2 005/10/13 Mixed Signal ADC 3. ADC Dynamic performances in ADC ADC architectures Integrating ADC Successive approximation ADC Flash ADC Folding ADC Two step parallel ADC Interpolating ADC Design of pipeline ADC Basic circuit blocks for ADCs Operational amplifier Sample and hold switches Comparators Offset cancel circuits Implementation & design of high performance A/D and D/A converters Design challenges

3 Basic functions in ADC Sampling: Sampling the analog signal with accurate timing. Quantization: Express the converted data with certain accuracy. 標本化 (Sampling) 量子化 (Quantizing) 電圧 Voltge 電圧 Voltage 時間 Time 時間 Time ADC 符号化 (Coding) Analog Sampling Quantizing Coding Digital CLK 005/10/13 Mixed Signal ADC 3

4 005/10/13 Mixed Signal ADC 4 Static performance INL and DNL are the major static performances of ADC and DAC. INL: Integrated Non-Linearity DNL: Differential Non-Linearity

5 005/10/13 Mixed Signal ADC 5 Quantization noise Quantization causes noise Higher SNR needs higher resolution P n I/O characteristics Δ / Δ / = e P( e)de = Δ / Δ / QP( e) 1 = Δ, 0,all other e e e 1 de Δ Δ < Δ = 1 P s = SNR SNR N 1 ( Δ ) db P P s n = Quantization noise N 1 ( Δ ) P = 10log P s n 1 = 1. 5 Δ N = 6. 0 N 1. 76

6 005/10/13 Mixed Signal ADC 6 Dynamic performance Dynamic performance indicates the ratio between signal and noise or distortions. We should use suitable terms for the kind of applications. SNR = 10log Signal power Total noisefloor power SFDR = 10log Signal power L arg est spurious power THD = 10log Total harmonic distortion power Signal power SNDR = 10log Signal power Noise and distortion power ENOB = SNDR

7 005/10/13 Mixed Signal ADC 7 BER requirement The lower bit error rate requires the higher ADC/DAC resolution. Resolution (quantization noise) affects BER. DAC requirement for QAM ADC requirement for digital read-channel

8 005/10/13 Mixed Signal ADC 8 Input signal level SNR decreases with decreasing the input signal level. This is because the quantization noise is same, but the input signal is small. 1) No AGC: Lower SNR 8b, theoretical line Input ADC Data ) Use AGC: Higher SNR Auto Gain Controller Input ADC Data Full scale Input signal level (db)

9 005/10/13 Mixed Signal ADC 9 Performances and applications of ADCs Conversion Frequency (MHz) Flash HDD Digital I/F DVD VDSL Pipeline Motor servo Digital TV Cellular phone GSM handset Resolution(bit) Digital Camera ADSL Progress of technology Conventional Audio Sigma Delta CD/MD DVD Audio DVD Player

10 005/10/13 Mixed Signal ADC 10 ADC Architecture:Flash and pipeline Flash is used for ultra-high speed conversion with low resolution. Pipeline is used for high resolution with moderate conversion speed. Vref Vin CLK Comparator Flash Deliverables; Folding Interpolation Encoder v in MSB 1-bit DAP S/H 1-bit DAP 1-bit DAP Comparator Pipeline D 1 D D 3 D 4 D 5 D 6 D 7 v ref v 4 ref 4 1-bit DAP 1-bit DAP 1-bit DAP Digital approximater (DAP) Amplifier Suitable for CMOS Switched capacitor operation LSB 1-bit DAP Ultra-high speed (--GHz) Low resolution (<8bit) Large power consumption High resolution(<14bit) Moderate speed(<100mhz) Low power consumption

11 005/10/13 Mixed Signal ADC 11 Integrating ADC (1) High resolution (0bit and more) Very low speed (DC measurement) Can realize zero offset voltage Small analog elements and easy to be embedded with digital circuits S Reset Control signal S 1, S -v in S/H v ref S 1 Reference R C v x integrator Comparator Controller Counter Digital out Clock

12 Integrating ADC () S 1 -v in C Comparator v ref R v x PhaseⅠ PhaseⅡ -v in -v in Going to 0 -> 1, when Vx becomes negative. v ref v ref v x v in 大 T ( v ) in vx ( T ) = dτ = 0 RC vin RC T 0 PhaseⅠ T Time 005/10/13 Mixed Signal ADC 1

13 005/10/13 Mixed Signal ADC 13 Successive-Approximation ADC (1) Comparator v 1 in S/H Control logic Binary search algorithm Comparator input D 1 D Time Successive-approximation Register D 1 D DAC Digital out Reference voltage Multi clock cycles are needed.

14 005/10/13 Mixed Signal ADC 14 Successive-Approximation ADC () Charge-Redistribution ADC Virtual ground Sampling mode v x =0 S v out 16C 8C 4C C C C Comparator S 1 Sampled input signal Reference voltage v in v ref

15 005/10/13 Mixed Signal ADC 15 Successive-Approximation ADC (3) Charge-Redistribution ADC Hold mode S v x = -v in v out 16C 8C 4C C C C S 1 Sampled input signal Reference voltage v in v ref

16 005/10/13 Mixed Signal ADC 16 Successive-Approximation ADC (4) Charge-Redistribution ADC Determine the output bits from MSB to LSB v = v x in v ref Bit cycling mode S v out 16C 8C 4C C C C S 1 Sampled input signal Reference voltage v in v ref

17 Flash ADC R/ R R R R R R R R/ V DD v in Φ Comparator Ultra fast operation: Several GHz No sample and hold Low resolution: <9 bit Large input capacitance Area and power increase exponentially with resolution 005/10/13 Mixed Signal ADC 17 Encoder Digital out

18 005/10/13 Mixed Signal ADC 18 Two step parallel ADC One of the basic architectures for video-rate ADCs Vin Vrb Vrt Matrix switches 入力信号 ~ 上位比較器列 下位比較器列 Upper conversion Encoder Lower comparators Upper comparator マトリクススイッチ 1 1 Lower comparators Encoder 5 5 Clock generator 15 上位コンパレータ 16 エンコーダ 加算器 8 Encoder Adder 出力データ Output data C7 D7 C6 D6 C5 D5 C4 D4 C3 D3 C D C1 D1 上位基準抵抗列下位基準抵抗列参照電圧を切り替える Change the reference signals Input voltage Lower conversion GND

19 005/10/13 Mixed Signal ADC 19 Chopper inverter comparator Pros: Simple, low power, small area, low voltage, and sample and hold action Cons: large absolute offset, suffer the power supply noise, sensitive to Vdd. Vdd Vin=Vr: No change Vin>Vr: Vout goes down Vin S1 on off C Vg Vout Vdd/ Vout Vdd Vin Vr S3 off on S on off GND -G(Vr-Vin) Vr S1, S:ON, S3:OFF; Signal sampling S1, S:OFF, S3:ONN; Offset cancel and amplify 0 0 Vdd Vg Vdd

20 005/10/13 Mixed Signal ADC 0 Two step parallel ADC SW 1 Cc1 Cc Vin Latch Vrc SW c SW 3 SW 4 インバータ1c インバータc インバータ1f インバータf 上位コンパレータ For upper conversion SW 1 Cf1 Cf Latch Vrf SW f SW 3 SW 4 下位コンパレータ For lower conversion Realizing simultaneous signal sampling channel lower conversion units realize two times higher operation Overlap scheme relaxes needed offset voltage for comparators

21 005/10/13 Mixed Signal ADC 1 Two step parallel ADC: Timing chart simultaneous sampling Hold in lower conversion when upper comparators compares 外部クロック Clock 上位コンパレータ Upper comparators Sam pling C om parison Sam pling C om parison Alternative action 下位コンパレータ R Lower comparators (R) Sam pling Hold C om parison 下位コンパレータ L Lower comparators (L) H old C om parison S a m p lin g Hold 出力データ Output data D A T A (R ) DATA (L) DATA (R)

22 005/10/13 Mixed Signal ADC Overlapping scheme Set the reference voltage range in the lower conversion wider than that of the upper conversion to form the overlapping scheme. This scheme can relax the requirement for the mismatch voltage to the upper comparators [0] Upper range [1] Lower range Over range Overlapping Otherwise, sub-ranging and two step parallel ADC cause the conversion errors. [-1] Under range Overlapping

23 005/10/13 Mixed Signal ADC 3 Conversion errors in Sub-ranging ADC Same Larger Lower Upper conversion values Output value 15 is missed Wider period for 15 Lower conversion values Input signal

24 005/10/13 Mixed Signal ADC 4 Accuracy of the flash ADC High resolution flash ADC is quite difficult. Because DNL degrades directly by transistor mismatch. Ideal quantization voltage σ off Offset voltage distribution 100 Analog bipolar Digital bipolar MOS V q V a Actual quantization voltage Yield (%) 10 1 DNL<0.5 LSB DNL<1.0 LSB DNL ( LSB ) V = a V V q q Offset voltage (mv) at sigma

25 Interpolation by internal division method x y y 0 0 0b xo = ax = ax y1 = a( x x y 1b C 0 C 1 y 0 y 0b y 1 y 1b n m n m m n m m n m Interpolation circuits 0 ) = a( x x 0 ) y y n nb 1 = m 1 = m y n y nb 005/10/13 Mixed Signal ADC 5 y {( m n) y0 ny1} {( m n) y0b ny1b} n X n m m-n y 0b y 0 ynb yn x 0 Interpolation method y 1 x y 1b

26 005/10/13 Mixed Signal ADC 6 Capacitive interpolation Vin 上位比較器 Vin S1a Vr c ラッチ Vr Ci a Vo1a 前段増幅器第 1 補間回路第 補間回路 下位比較器 INV1a S1b Cc q1a Vb S Vr f ラッチ Vr4Vq Ci b Cc q1b INV Cp qp ラッチ INV1b Vo1b ラッチ 回路状態 1, I NV1 a, I NV1 b: 増幅状態, I NV : バイアス状態 S1a Vr f' ラッチ ラッチ INV1a Cc q'1a S 除去されたインバータ S1b Cc INV q'1b Cp Interpolation, offset cancel, amplification, in a pipeline manner. INV1b 回路状態, I NV1 a, I NV1 b: バイアス状態, I NV : 増幅状態

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