ADC-Based Backplane Receivers: Motivations, Issues and Future

Transcription

1 JOURNAL OF SEICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, 2016 ISSN(Print) ISSN(Online) ADC-Based Backplane Receivers: otivations, Issues and Future Hayun Chung Abstract The analog-to-digital-converter-based (ADCbased) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both frontend ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using systemlevel models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process. anuscript received Sep. 25, 2015; accepted Dec. 28, 2015 Department of Electronics and Information Engineering, Korea University, Sejong, South Korea hcchung@korea.ac.kr Index Terms Analog-to-digital converter, backplane receiver, high speed, low power, system-level modeling I. INTRODUCTION As the ever-growing demands for higher data rate call for more sophisticated equalization schemes and the advances in fabrication technology favor digital circuit implementation, backplane receivers that rely on a frontend analog-to-digital converter (ADC) and a digital equalizer are gaining more popularity in these years [1-8]. Such ADC-based receivers not only provide opportunity to utilize advanced digital signal processing (DSP) techniques to perform higher-level of equalization, but also enable more robust circuit implementation against process variation, leakage, and noise. oreover, as their digital counterparts scale well with process, power, area, and speed of the ADC-based receivers continue to improve as the fabrication technology advances. One of the major challenges in implementing such ADC-based receivers is designing a high-speed front-end ADC with low-power consumption. In order to correctly digitize high data-rate signals running at 10 s of Gbps, the front-end ADC requires high input bandwidth and high sampling rate at the same time. eanwhile, to meet the tight power budgets of the backplane link system, power consumption of the front-end ADC should be minimized. Unfortunately, designing a high-speed ADC consuming low power is non-trivial [7, 9-17]. Flash ADCs are widely used for high-speed operation as they have short conversion times. However, they suffer from high power consumption, especially when the ADC resolution is high, as the number of comparators increase exponentially with the number of ADC bits. Successive

2 JOURNAL OF SEICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, approximation register (SAR) ADCs, on the other hand, can significantly reduce power consumption, but they suffer from long conversion times. In the coming sections, we will discuss which type of ADC would be preferable as the front-end ADC of a backplane receiver. Another issue associated with the ADC-based receiver is high power consumption and complexity of the digital equalizer. Digital equalizers scale well with fabrication technology offering power and area reduction as the process advances and are immune to various on-die nonidealities (e.g., PVT variation and noise). However, when the operation speed is high, they suffer from high power consumption and complexity. Therefore, a careful design is required when implementing a digital equalizer for the backplane transceiver operating at 10 s of Gbps. Finally, as both front-end ADC and digital equalizer can consume high power and suffer from high complexity, it is important to optimize the backplane transceiver performance at system-level. The system-level optimization also provides useful information that can be used in deciding design parameters for front-end ADC and digital equalizer. The rest of this paper is organized as follows. Section II describes overall architecture of the ADC-based receiver. Sections III and IV then discuss major design issues and approaches associated with implementation of the front-end ADC and digital equalizer, respectively. To meet tight power and performance budgets of the backplane transceiver, it is important to optimize powerperformance tradeoff of the ADC-based receiver on system-level. Therefore, an example of system-level optimization framework is presented in Section V. Finally Section VI summarizes and concludes this paper. Fig. 1. Frequency responses of various backplane channels [18]. (a) II. ADC-BASED RECEIVER ARCHITECTURE In high-speed backplane link systems, a backplane channel consists of everything on the path from one chip to the other, including backplane trace, line card trace, connectors, vias, and so on. Such a complex structure leads to losses and reflections that can degrade quality of the signal. Fig. 1 shows frequency responses of various backplane channels. Clearly, the losses and reflections severely degrade signal integrity at high frequencies. Fig. 2 compares pulse responses transmitted through one of the backplane channels in Fig. 1 (i.e., 20 bottom) (b) Fig. 2. Pulse responses transmitted through a 20 bottom trace at (a) 1 Gbps, (b) 10 Gbps. at 1 Gbps and 10 Gbps. Red stems show pre-, main-, and post-cursor intersymbol interference (ISI) components at the sampling points. Compared to the 1 Gbps data, the 10 Gbps data transmission requires much heavier

3 302 HAYUN CHUNG : ADC-BASED BACKPLANE RECEIVERS: OTIVATIONS, ISSUES AND FUTURE Analog Digital Analog Digital Analog Equalizer ADC Digital Equalizer (a) Fig. 4. ADC-based backplane receiver architecture with a digital equalizer. in I AIN I TAP1 I TAP2 I TAP1 (b) out decision history Fig. 3. Backplane receiver with an analog equalizer (a) receiver architecture, (b) conceptual circuit diagram of the analog equalizer. equalization to recover the original signal while the 1 Gbps pulse response has only 2 post-cursor components, the 10 Gbps pulse response has 1 pre-cursor and 10 postcursor components. Traditionally, backplane receivers with an analog equalizer have been widely used. Fig. 3(a) illustrates the analog-equalizer-based backplane receiver architecture. The receiver consists of an analog equalizer followed by a slicer. The analog equalizer directly manipulates the incoming high-speed signal to cancel the effects of postcursor components. Then, the slicer makes decision by comparing the equalized output with a reference voltage to convert an analog signal to a digital signal. Fig. 3(b) shows a conceptual circuit diagram of an analog currentsumming finite impulse response (FIR) decisionfeedback equalizer (DFE). The equalizer turns on/off currents that are proportional to post-cursor components based on previous decision history to subtract the effect of the post-cursor components. Such a structure enables fast and low power operations. However, as it relies on previous decision history, pre-cursor components cannot be compensated. oreover, since each current summing stage adds capacitive loading at the output node, it suffers from bandwidth limitations when heavy equalization is applied. For this reason, the analog equalizers cannot efficiently deal with high-speed data streams as seen in Fig. 2(b), high-speed signals not only require precursor cancellation but also need to cancel out large number of post-cursors that can limit the bandwidth of the analog equalizer. To overcome such difficulties, ADC-based backplane receivers that rely on a digital equalizer have been proposed. Fig. 4 shows the ADC-based receiver architecture that consists of a front-end ADC, a digital equalizer and a digital slicer. Once the high-speed input signal is digitized in the front-end ADC, the digital equalizer cancels the effect of unwanted cursor components. Unlike the analog equalizer that rely on linear current summing structure, the digital equalizer can support both linear and nonlinear types of equalization allowing adoption of more sophisticated equalization techniques. oreover, as digital circuits can reconfigure themselves depending on channel environments, the receiver can be reused to save unnecessary efforts in designing and fabricating the chip. ost importantly, as digital circuits scale well with fabrication process, power consumption and area of the digital equalizers will scale as process continues to advance. Although there are many benefits of utilizing such ADC-based receiver architecture, they often suffer from high power consumption and complexity as both the front-end ADC and digital equalizer can be power consuming and complex especially when operating at high data rates. Therefore, a careful circuit design together with high-level optimization are required to meet tight power and performance budgets of high-speed link systems. III. FRONT-END ADC In ADC-based receivers, the front-end ADC converts an incoming high-speed analog signal to a digital code.

4 JOURNAL OF SEICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, Fig. 5. ADC survey: sampling rate vs. ENOB [19]. Fig. 6. ADC survey: sampling rate vs. FO [19]. As the high-speed backplane link operates at 10 s of Gbps, the front-end ADC requires both high input bandwidth and high sampling rate in order to accurately quantize the incoming high-speed signal. At the same time, to meet the tight power budgets of the backplane link system, the power consumption of the front-end ADC has to be minimized. However, achieving high input bandwidth, high sampling rate, and low power consumption simultaneously is non-trivial. In the past years, various types of ADCs have been extensively studied to meet such requirements for the front-end ADC. This section analyzes previously reported high-speed ADCs in terms of power, speed and architecture to provide guidelines in designing front-end ADCs for backplane receivers. All the data points and graphs presented in this section are created based on the ADC survey [19] that lists all the ADCs presented in IEEE International Solid-State Circuits Conference and Symposium on VLSI Circuits from 1997 to Fig. 5 shows the effective number of bits (ENOB) of the ADCs with sampling rate higher than 1 GS/s. As the sampling rate increases the ENOB decreases, as higher ADC resolution leads to longer conversion times that limit the sampling rate. Notice that no ADCs achieve ENOB higher than 6 bits when the sampling rate is higher than 10 GS/s. Luckily, in case of high-speed backplane link system, 4-6 bits of ADC resolution is good enough to restore the transmitted bits. Once the target ADC resolution is decided (e.g., 4-6 bits), it is important to minimize power consumption while maintaining high sampling rate to meet the tight power budget of the backplane link system. Figure-ofmerit (FO) is a widely used measure for the ADC performance describing energy consumption per bit resolution and defined as, FO = Power f s 2 ENOB Fig. 6 presents FO versus sampling rate. Knowing that the power budgets per serial I/O link are lower than a few hundred mw, the FO of the front-end ADC should be lower than 0.5 pj/conversion-step in order to meet the overall power budgets [20]. Although such level of FO may not be difficult to achieve for ADCs with low sampling rates, it becomes very challenging to meet when the sampling rate is high (e.g., higher than 10 GS/s) due to clocking costs and high degree of time interleaving. For such reason, only a handful of ADCs with FO lower than 0.5 pj/conversion-step exist when the sampling rate is higher than 10 GS/s. Therefore, a careful design choices should be made based on a study on previous high-speed ADC architectures. In Fig. 6, blue O s and black X s represent ADCs with and without time interleaving, respectively. Notice that, all the ADCs with sampling rate higher than 10 GS/s employ time interleaving structure, as it is very challenging to achieve such high sampling rate with a single path structure. Fig. 7 shows the percentage of different ADC architectures adopted in high-speed ADCs presented in Fig. 6. When all the ADCs are considered, flash architecture is most widely used as they have short conversion times that translate to high sampling rates. (1)

5 304 HAYUN CHUNG : ADC-BASED BACKPLANE RECEIVERS: OTIVATIONS, ISSUES AND FUTURE (a) Table 1. Performance summary of high-speed front-end ADCs Architecture [7] [8] [13] [15] [21] [22] TI-flash TI-SAR TI-flash TI-flash TI-flash TI-SAR Technology (nm) Resolution (bits) ENOB (bits) Sampling rate (GS/s) ax. input freq. (GHz) Power (mw) FO (pj/conv.-step) Area (mm 2 ) N/A Two-stage THA Duty cycle ctrl. Input THA Reference Gen. Comparators 2 N 1 N Thermometer-to-binary Output (b) Fig. 7. ADC survey: pie diagram of the ADC type (a) overall ADCs, (b) TI-ADCs [19]. However, as flash ADCs consume high power they are not ideal for multi-way time interleaving, where multiple sets of ADCs are employed to achieve high aggregate sampling rate. Therefore, when only time-interleaved (TI) ADCs are considered, flash ADCs turn out to be less popular. Instead, successive approximation resistor (SAR) ADCs are widely employed. The time-interleaved SAR ADCs leverage the extremely low power and extremely small area characteristics of the SAR ADCs. Although conversion time of a single SAR ADC may be long, by utilizing multiple paths of ADCs, the timeinterleaved SAR ADC can achieve high aggregate sampling rate. Since the power consumption and area are extremely low and small for a single SAR ADC, the total power consumption and area may be still lower and smaller than that of flash ADCs even when multiple ADCs are combined. Table 1 summaries performance of Fig. 8. An example of high-speed flash ADC with two-stage THA and duty-cycle control [23]. previously reported high-speed front-end ADCs with sampling rate higher than 10 GS/s and FO lower than 1 pj/conv.-step. Rest of this section reviews high-speed front-end ADC circuit design examples utilizing the flash and SAR architectures. Fig. 8 shows an example of high-speed flash ADC [23]. While flash ADCs support high sampling rates based on their short conversion times, they suffer from high power consumption and bandwidth limitation as the number of comparator connected to the track-and-hold amplifier (THA) output increases exponentially with the ADC bit resolution. The two-stage THA separates high-speed input node from the heavily loaded-due to the multiple comparators-tha output. This significantly improves input bandwidth as the input node only sees the loading from the second amplifier. oreover, since the second amplifier only needs to track a DC voltage held by the first track-and-hold stage, the size of the second amplifier can be much smaller than the

6 JOURNAL OF SEICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, Input aster T&H SAR ADC 1 CDAC SAR ADC SR N Output N digitized input N 1 E DFE 1-bit decision SAR ADC N Tap weight update logic Fig. 9. An example of high-speed time-interleaved SAR ADC with master T&H [22]. case when only one amplifier is employed (i.e., without track-and-hold stage). This not only improves input bandwidth-by downsizing the first amplifier-but also reduces power consumption significantly. Distorting duty cycle of the sampling clock and allocating longer tracking times for the second THA stage may further improve the ADC performance at very high sampling rates. Such design techniques enable high sampling rate, high input bandwidth and low power consumption, simultaneously, making them a good candidate for highspeed front-end ADCs. Although a single path ADC may not support 10 s of GS/s, higher sampling rates over 10 GS/s can be achieved by time interleaving just a few number (i.e., 2) of such high-speed flash ADCs. Unlike flash ADCs, SAR ADCs often suffer from long conversion times that lead to low sampling rates. However, they provide extremely low power and compact area performances, which makes them ideal for multi-way time interleaving. Leveraging this fact, multiple (e.g., 8-16) SAR ADCs can be time-interleaved to achieve high aggregate sampling rates (e.g., 10 GS/s) while keeping the overall power consumption low. Fig. 9 shows an example of a -way TI-SAR ADC [22]. In case of TI-SAR ADC, multiple SAR ADC paths may add large parasitic capacitive loading at the input node degrading the input bandwidth. Therefore, similarly to the case of flash ADC, a two-step track-and-hold can be employed to improve input bandwidth and save power. In order to support high sampling rates, the master trackand-hold (i.e., first-stage track-and-hold) should operated at high-speed (i.e., target sampling rate), while the local track-and-hold can operate at much slower rate (i.e., target sampling rate divided by ) that corresponds to the sampling rate of each SAR ADC path. As the time interleaving depth grows, more multi-phase clocks are required. Therefore, in case of deep TI-SAR ADCs, Fig. 10. Digital EQ architecture. careful clock distribution design is required. IV. DIGITAL EQUALIZER Once the front-end ADC digitizes the input signal, the digital equalizer (EQ) equalizes the signal in digital domain to restore the original data sequence. One of the major benefits of the ADC-based receivers is that, leveraging the advanced digital signal processing (DSP) techniques, various types of linear and nonlinear equalization schemes can be adopted to optimize power and performance of the backplane receiver. Unfortunately, recent studies on the digital equalizer of the ADC-based receiver are focused on the digital counterpart of the analog finite-impulse-response-filter-based (FIR-filterbased) equalizer and more advanced forms of digital equalizers are yet to be explored. In this section, we will discuss design challenges in digital equalizers based on the FIR-filter-based structure and suggest design choices to overcome implementation difficulties. While the digital implementation of equalizers enable robust operations against PVT variations and noise compared to their analog counterparts, they suffer from high hardware complexity and power consumption when the data rate is high. Therefore, a detailed analysis on critical path delay, complexity and power consumption is crucial to meet the tight power-performance budgets of the overall link system. Fig. 10 shows an example of FIR-filter-based digital EQ architecture that consists of a feed-forward equalizer (E), a slicer, a decision-feedback equalizer (DFE) and a tap-coefficient update logic. Unlike the analog EQ, digital EQ supports feed-forward equalization as they can easily store, shift and modify digitized input signal. However, as the FIR-filter-based E implementations require multi-bit multipliers that may lead to high power consumption, they are often avoided. As variations on the

7 306 HAYUN CHUNG : ADC-BASED BACKPLANE RECEIVERS: OTIVATIONS, ISSUES AND FUTURE digitized input N Feedback loop 1 1-bit decision channel response due to temperature and aging effect are slow, the tap-coefficient update logic can run at much slower rate than the other EQ blocks and its contribution on power consumption and complexity are negligible. The DFE utilizes 1-bit decision history to cancel out post-cursor ISI components. Fig. 11 shows a functional model of the DFE based on a FIR filter. The delayed set of slicer outputs (i.e., the 1-bit decision history) are multiplied by tap-coefficients and weighted sum of the decision history is fed back to the slicer to set the slicing level for the next decision. Since the whole feedback procedure-including 1-bit decision making, tapcoefficient multiplication and summation-should be completed within a clock cycle (i.e., 100 ps assuming 10 Gbps), implementing the DFE operating at high data rates is very challenging. Fig. 12 illustrates three implementation approaches that can extend loop bandwidth-loop unrolling, loop delay extension and time interleaving. Loop unrolling shown in Fig. 12(a) pre-calculates the slicer levels such that one can be quickly selected when the decision is made. This method can significantly reduce the loop delay as time-consuming multiplying and summing processes can be excluded from the feedback loop. The DFE with loop unrolling may still suffer from a speed bottleneck as keeping the loop delay-consisting of a 2:1 multiplexer and a flip-flop delays-within a clock cycle may be challenging as the data rate approaches 10 s of Gbps. Extra combinational logic can be employed to extend the loop delay by one clock cycle and overcome the speed bottleneck [25], as shown in Fig. 12(b). In case further relaxation on timing constraint is required, time interleaving can be adopted as shown in Fig. 12(c) at the expense of complexity. When loop unrolling is employed, the magnitude Δ Δ µ 0 µ 1 Fig. 11. Functional model of a FIR-filter-based DFE. Δ µ N-1 FIR filter comparator and slicer can be merged with the front-end ADC by replacing the ADC reference levels with the precalculated equalizer slicing levels [4, 5, 8, 26]. Fig. 13 illustrates such a DFE structure, called reduced-slicer partial-response DFE (RS-PRDFE). The RS-PRDFE can relax implementation overheads on both front-end ADC and digital EQ, reducing overall complexity and power consumption when employed in an ADC-based receiver. However, as the structure only supports FIR-filter-based equalization, more equalization techniques utilizing advanced DSP techniques including nonlinear equalization cannot be exploited. Structure-wise, it is more accurate to consider the RS-PRDFEs as loop unrolled analog equalizers than digital equalizers, as the pre-calculated slicer levels are converted back to analog domain relying on digital-to-analog converters (DACs) to make decisions. To find digital EQ architectures that can truly exploit the benefits of ADC-based receiversthat can utilize advanced DSP techniques and minimize front-end ADC implementation overheads-system-level verification and optimization based on high-level models are crucial. V. SYSTE-LEVEL OPTIIZATION As seen previously, both front-end ADC and digital EQ can be power consuming and complex when operating at high data rates. Therefore, a careful design based on a system-level optimization utilizing high-level simulators (e.g., ATLAB, XODEL and CppSim) is crucial to meet tight power and performance constraints of the overall high-speed link systems. High-level behavioral and power models allow quick estimation on the performance and power consumption. Leveraging the fast simulation times, a system-level design-space exploration can be performed to find optimal design parameters of the ADC-based receivers (e.g., ADC resolution, EQ resolution, number of EQ taps, etc.). Fig. 14 shows an example of a system-level model configuration of an ADC-based receiver. As the frontend ADC handles a high-speed analog input signal that are susceptible to variability and noise, an accurate behavioral model is required to correctly estimate the digitized output. At the same time, since fast performance estimation is crucial in system-level optimization, the behavioral model should support short

8 JOURNAL OF SEICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, in clk slice0 slice1 slice2 slice3 slice4 slice5 slice6 slice7 1 2:1 T clk out (a) in clk slice0 slice1 slice2 slice3 slice4 slice5 slice6 slice7 1 (b) 2:1 T clk 2 out in clk/2 clk/2 slice0 slice1 slice2 slice3 slice4 slice5 slice6 slice7 slice0 slice1 slice2 slice3 slice4 slice5 slice6 slice :1 2:1 T clk 2 T clk 2 out_even out_odd (c) Fig. 12. High-speed implementation choices for a three-tap DFE (a) loop unrolling, (b) loop unrolling with loop delay extension, (c) loop unrolling with delay extension and time interleaving [24] 2014, IEEE.

9 308 HAYUN CHUNG : ADC-BASED BACKPLANE RECEIVERS: OTIVATIONS, ISSUES AND FUTURE in N Shift Register Ref. Gen. (DAC) 2 N :1 1-bit decision Slicer level selection Tap weight update logic Pre-calculate slicer levels based on FIR-filter-based equalization Fig. 13. RS-PRDFE architecture. Performance estimation Power estimation System-level modeling Front-end ADC (Accurate behavioral model) Front-end ADC (Realistic power model) Digital Equalizer (Simple functional model) Digital Equalizer (Realistic power model) Fig. 14. Configuration of a system-level model of an ADCbased receiver. Fig. 15. Example of a system-level optimization based on a design-space exploration [24] 2014, IEEE. simulation times. In order to achieve high simulation accuracy and short simulation time simultaneously, fine time steps (e.g., 10-3 of symbol time) can be adopted only near and at the point of interest (i.e., THA sampling point). Adopting time-domain interpolation techniques can further improve accuracy with minimal increase in simulation complexity. Finally, including only major circuit non-ideality effects (e.g., input-dependent sampling instant, R on variation, circuit bandwidth limitation, comparator offset and etc.) and excluding insignificant effects greatly reduces complexity of the behavioral model and enable fast simulations. Once the input signal is digitized, the digital equalizer can rely on a simple functional model with coarse time step (i.e., one sample per symbol time) to estimate its performance, as digital circuits are more robust against variability and noise. To estimate the power consumption of the ADCbased receiver, a realistic model based on practical implementation choices is required. While the front-end ADC has relatively simple structure with few building blocks, the digital equalizer, especially running at high data rates, can be complex as seen in the previous sections. Therefore, having a power model based on practical and detailed implementation choices (e.g., loop unrolling, loop delay extension and time interleaving) is important to get a reliable estimation. The power model decides required implementation choices based on the given loop delay constraint. The equalizer power consumption then can be calculated by summing up the power consumed in each circuit blocks (e.g., D flip-flop and multiplexer) where the total number of circuit blocks is determined by the implementation choices and design parameters (e.g., number of EQ taps). As the system-level model enables fast estimation on performance and power, various types of architectures (e.g., with different types of front-end ADC types and linear/nonlinear digital equalizers) can be tested in early stages of design to determine possible design choices. Also, wide rages of design parameters can be swept to find the optimal design point for a given structure. Fig. 15 shows an example of a system-level optimization framework based on a power-performance design-space exploration [24] using ATLAB. The equalizer performance is measured in mean-squared error (SE) and the power is measured in watts (W). Note that based on the Q-function, SE of and 0.03 can be translated to BER of and 10-3, respectively. The Pareto frontiers, shown in a black line, suggest optimal design points in terms of power and performance tradeoffs. Depending on the power and performance

10 JOURNAL OF SEICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, 2016 Fig. 16. ADC bit resolution versus equalizer performance. budgets, one of the Pareto frontier points can be chosen as a design point to suggest design parameters of the building blocks. For example, the point marked with black circle comprising 5.5-bit front-end ADC and a digital equalizer with a 1-tap E and a 6-tap DFE can be chosen as an optimal design point to achieve SE of As discussed in the previous sections, designing a high-speed front-end ADC can be very challenging. Since power consumption and speed of the ADCs are highly dependent on ADC resolution (e.g., power consumption and capacitive loading grow exponentially with ADC resolution in flash ADCs), minimizing the ADC resolution can significantly improve power and speed performances of the ADC-based receiver. As system-level models allow fast estimations on equalizer 309 performance, minimum ADC bit resolutions required to achieve target BER performance can be found at the early stage of design. Fig. 16 shows equalizer performance as a function of ADC resolution, assuming a 14-bit digital equalizer with a 1-tap E and a 6-tap DFE. The optimal design point assuming SE is marked with a black circle. As the digital equalizer assumes linear FIR-filter-based architecture, quantization error due to coarse ADC resolution significantly degrades equalizer performance. As a result, at least 5.5-bit ADC resolution is required to achieve roughly BER (i.e., SE), which is very challenging to implement when the sampling rate is higher than 10 GS/s. As reducing ADC resolutions can significantly improve speed, power and area of the overall receiver, developing a nonlinear equalizer algorithm that works well with a coarse ADC (e.g., 2-3 bit ADC) is crucial in realizing a high-speed, low-power ADC-based receiver. Such system-level models also allow us to estimate future ADC-based receiver trends as the device parameters can be easily replaced to study the impact of new devices. Fig. 17 illustrates the impact of fabrication technology scaling, scaled from 65 nm to 22 nm. While the equalizer performance does not scale well with process as the channel environment stays the same, the power consumption reduces significantly as power consumption of the digital equalizer scales very well with the fabrication technology. The power consumption reduces roughly by a factor of three as the process technology reduces from 65 nm to 22 nm. Such good scalability along with other benefits of the digital equalizers (i.e., robustness against PVT variation, good Fig. 17. Design-space of the ADC-based receiver (a) 65 nm, (b) 22 nm COS processes [24] 2014, IEEE.

11 310 HAYUN CHUNG : ADC-BASED BACKPLANE RECEIVERS: OTIVATIONS, ISSUES AND FUTURE flexibility and ability to support both linear and nonlinear types of equalizations) makes the ADC-based receivers more attractive as the fabrication technology continues to advance. VI. CONCLUSION The ADC-based backplane receivers provides various benefits-1) scalability with fabrication process, 2) portability, 3) immunity to PVT variations and 4) ability to support both linear and nonlinear equalizations and utilize advanced DSP techniques. However, designing such an ADC-based receiver is non-trivial as both frontend ADC and digital equalizers can be complex and power consuming when operating at high speed. Therefore a careful design is required. As the front-end ADC needs to deal with high speed input signals, they require high sampling rate and input bandwidth. Simultaneously, their power consumption should be kept low as the backplane link system has tight power budgets. Flash ADCs with shallow time interleaving and SAR ADCs with deep time interleaving are two most popular choices for the front-end ADCs. The flash-type front-end ADCs exploit their short conversion times to achieve high sampling rates with minimal degree of time interleaving (e.g., 2-4 paths). However, as flash ADCs suffer from high power consumption, techniques to minimize power consumption (i.e., two-stage THA and comparators with minimum size devices) are crucial to keep the overall power consumption low. The SAR-type front-end ADCs take advantage of the low power consumption of a single SAR ADC. Since a SAR ADC consumes extremely low power, large number of ADCs (e.g., 8-16) can be timeinterleaved to achieve high aggregate sampling rate. To minimize the impact of phase mismatch between the sampling clocks and maximize the input bandwidth a master-slave T&H structure can be employed. While various types of equalization including nonlinear equalization can be employed in the digital EQ, current form of digital EQs rely on the conventional FIRfilter-based structure and other forms of digital EQ utilizing more advanced DSP techniques haven t been studied yet. As the digital EQs are power consuming and complex at high data rates, they also require careful design. Techniques such as loop unrolling, loop delay extension and time interleaving can be employed at the expense of complexity to achieve high speed operations. In recent years, RS-PRDFEs that merge the front-end ADC and the digital EQ have been proposed to minimize power consumption and complexity of the ADC-based receivers. However, as they rely on the FIR-filter-based architecture, other types of more advanced equalizations cannot be adopted. To optimize power and performance tradeoffs and enable studies on feasibility of various types of equalizations, a system-level model of the ADC-based receivers can be utilized. Simulations with more advanced device parameters suggest that the power consumption of the ADC-based receiver scales very well with process, making it more attractive as the fabrication technology continues to advance. ACKNOWLEGENT This work was supported by the Korea University Grant. REFERENCES [1] Harwood,. et al: A 12.5Gb/s SerDes in 65nm COS using a baud- rate ADC with digital receiver equalization and clock recovery. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, (2007) [2] Cao, J. et al.: A 500mW digitally calibrated AFE in 65nm COS for 10Gb/s serial links over backplane and multimode fiber. IEEE Int. Solid- State Circuits Conf. Dig. Tech. Papers, (2009) [3] Chen, E.-H. et al.: 10Gb/s serial I/O receiver based on variable reference ADC. IEEE Symp. VLSI Circuits Dig. Tech. Papers, (2011) [4] Kim, J. et al.: Equalizer design and performance trade-offs in ADC-based serial links. IEEE Trans. Circuits Syst. I, 58(8), (2011) [5] Chen, E.-H., Yousry, R., Yang, C.-K.: Power optimized ADC-based serial link receiver. IEEE J. Solid-State Circuits, 47(4), (2012) [6] Ting, C. et al.: A blind baud-rate ADC-based CDR. IEEE J. Solid-State Circuits, 48(12), (2013)

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