EE247 Lecture 12. Midterm exam Tues. Oct. 23rd

Transcription

1 EE Lecture Administrative issues Midterm exam Tues. Oct. rd o You can only bring one 8x paper with your own written notes (please do not photocopy) o No books, class notes or any other kind of handouts/notes, calculators, computers, PDA, cell phones... o Midterm includes material covered to end of lecture EECS Lecture : Data Converter Performance Metrics H. K. Page EE Lecture Data converters Static converter error sources Offset Full-scale error Differential non-linearity (DNL) Integral non-linearity (INL) Measuring DNL & INL Servo-loop Code density testing (histogram testing) EECS Lecture : Data Converter Performance Metrics H. K. Page

2 Summary of Last Lecture Filters (continued) Example: Switched-capacitor filters in CODEC integrated circuits Switched-capacitor filter design summary Comparison of various filter topologies Data Converters ADC & DAC transfer curve Sampling, aliasing, reconstruction Amplitude quantization EECS Lecture : Data Converter Performance Metrics H. K. Page Ideal ADC ("Quantizer") Accepts analog input & generates it s digital representation Quantization step: Δ (= LSB) Full-scale input range: -.Δ ( N -.)Δ E.g. N = Bits V FS = -.Δ to.δ Digital Output Code Ideal converter with infinite # of bits ADC characteristics - 8 V FS ADC Input Voltage [ Δ] EECS Lecture : Data Converter Performance Metrics H. K. Page

3 Quantization Error Quantization error Difference between analog input and output of the ADC converted to analog via an ideal DAC Called: Quantization error Residue Quantization noise V in ADC. Ideal DAC Residue - Σ ε q (V in ) + EECS Lecture : Data Converter Performance Metrics H. K. Page Quantization Error For an ideal ADC: Quantization error is bounded by Δ/ +Δ/ for inputs within full-scale range V in ADC Model D + out ε q (V in ) Digital Output Code Quantization error [LSB] ideal converter with infinite bits ADC characteristics ADC Input Voltage [Δ] EECS Lecture : Data Converter Performance Metrics H. K. Page

4 Quantization Error PDF Probability density function (PDF) Uniformly distributed from Δ/ +Δ/ provided that: Busy input Amplitude is many LSBs No overload Not Gaussian! Zero mean Variance +Δ / Δ / e Δ e = de= Δ PDF /Δ Ref: W. R. Bennett, Spectra of quantized signals, Bell Syst. Tech. J., vol., pp. -, July Δ/ +Δ/ error B. Widrow, A study of rough amplitude quantization by means of Nyquist sampling theory, IRE Trans. Circuit Theory, vol. CT-, pp. -, 9. EECS Lecture : Data Converter Performance Metrics H. K. Page Signal-to-Quantization Noise Ratio If certain conditions the quantization error can be viewed as being "random", and is often referred to as noise In this case, we can define a peak signal-to-quantization noise ratio, SQNR, for sinusoidal inputs: N Δ e.g. N SQNR 8 db N SQNR= =. db Δ 98 db db =.N +. db Accurate for N> Real converters do not quite achieve this performance due to other sources of error: Electronic noise Deviations from the ideal quantization levels EECS Lecture : Data Converter Performance Metrics H. K. Page 8

5 SQNR Measurement log(sqnr) db/octave SQNRpeak =.N +. db Ideal Realistic db Dynamic Range Vin [db] EECS Lecture : Data Converter Performance Metrics H. K. Page 9 Static Ideal Macro Models DAC D in V out V in ADC + ε q D out +-.LSB ambiguity EECS Lecture : Data Converter Performance Metrics H. K. Page

6 Cascade of Data Converters q ADC DAC V in + ε V out D in DAC ADC + εq D out EECS Lecture : Data Converter Performance Metrics H. K. Page Static Converter Errors Deviation of converter characteristics from ideal: Offset Full-scale error Differential nonlinearity DNL Integral nonlinearity INL EECS Lecture : Data Converter Performance Metrics H. K. Page

7 ADC Offset Error DAC Ref: Understanding Data Converters, Texas Instruments Application Report SLAA, Mixed-Signal Products, 99. EECS Lecture : Data Converter Performance Metrics H. K. Page Full-Scale Error ADC Actual full-scale point Ideal full-scale point DAC Ideal full-scale point Full-scale error Full-scale error Actual full-scale point EECS Lecture : Data Converter Performance Metrics H. K. Page

8 Offset and Full-Scale Error Note: For further measurements (DNL, INL) connecting the endpoints & deriving ideal codes based on the non-ideal endpoints eliminates offset and fullscale error Digital Output Code ADC characteristics ideal converter Offset error Full-scale error - 8 ADC Input Voltage [LSB] EECS Lecture : Data Converter Performance Metrics H. K. Page Offset and Full-Scale Errors Alternative specification in % Full-Scale = % * (# of LSB value)/ N Gain error can be extracted from offset & full-scale error Non-trivial to build a converter with extremely good full-scale/offset specs Typically full-scale/offset is most easily compensated by the digital pre/post-processor More critical: Linearity measures DNL, INL EECS Lecture : Data Converter Performance Metrics H. K. Page

9 ADC Differential Nonlinearity DNL = deviation of code width from Δ (LSB). Endpoints connected. Ideal characteristics derived eliminating offset & full-scale error. DNL measured Digital Output Code 8 ADC Transfer Curve Real Ideal -. LSB DNL error LSB DNL error +. LSB DNL error 8 ADC Input Voltage [Δ] EECS Lecture : Data Converter Performance Metrics H. K. Page ADC Differential Nonlinearity Ideal ADC transitions point equally spaced by LSB For DNL measurement, offset and full-scale error is eliminated DNL [k] (a vector) measures the deviation of each code from its ideal width Typically, the vector for the entire code is reported If only one DNL # is reported that would be the worst case EECS Lecture : Data Converter Performance Metrics H. K. Page 8

10 Example Offset, Full-Scale Error, Gain,& DNL A bit ADC is designed to have an ideal: LSB=.V V FS =.8V The measured transitions levels for the end product is shown in the table, compute offset, fullscale, gain error, & DNL Transition # Ideal transition point [V]. Real transition point [V]. - Offset: (real transition-ideal)= -.V, in LSB -./.= -.LSB.. - Full-scale error (real last transition-ideal) =.8-.=.V in LSB./.=+.LSB LSB after correcting for offset & full-scale error: LSB=(Last transition-first transition)/( N -).... LSB=(.8-.)/=.V..8 EECS Lecture : Data Converter Performance Metrics H. K. Page 9 ADC Differential Nonlinearity Example V FS = N..V=.88V -Gain relative to ideal Gain=.8/.88=.9 Code # Code Width [V] - Width [LSB] DNL [LSB] - Find all code widths Width[k]=Transition[k+]- Transition[k] -Divide code width by LSB W[k] Find DNL: DNL[k]=W[k]-LSB EECS Lecture : Data Converter Performance Metrics H. K. Page

11 ADC Differential Nonlinearity Example DNL [LSB]. -. Max. DNL - Code # Code # DNL [LSB] EECS Lecture : Data Converter Performance Metrics H. K. Page ADC Differential Nonlinearity Examples Digital Output Code 8 ADC characteristics Ideal Converter Missing code (+./- LSB DNL) Digital Output Code 8 Note: As input increases at a point output decreases instead of increase: Non-monotonic Non-monotonic (> LSB DNL) ADC Input Voltage [Δ] ADC Input Voltage [Δ] EECS Lecture : Data Converter Performance Metrics H. K. Page

12 ADC DNL DNL=- implies missing code For an ADC DNL < - not possible undefined Can show: all i DNL[i] = For a DAC DNL < - possible EECS Lecture : Data Converter Performance Metrics H. K. Page DAC Differential Nonlinearity To find DNL for DAC Draw end-point line from st point to last Find ideal LSB size for the end-point corrected curve Find segment sizes: segment [m]=v[m]-v[m-] segment[m] V[LSB] DNL[m] = V[LSB] Unlike ADC DNL, for a DAC DNL can be <-LSB EECS Lecture : Data Converter Performance Metrics H. K. Page

13 DAC Differential Nonlinearity EECS Lecture : Data Converter Performance Metrics H. K. Page Impact of DNL on Performance Same as a somewhat larger quantization error, consequently degrades SQNR How much later in the course... The term "DNL noise", usually means "additional quantization noise due to DNL" EECS Lecture : Data Converter Performance Metrics H. K. Page

14 ADC Integral Nonlinearity INL = deviation of code transition from its ideal location INL is also a vector INL[k] If one INL # reported Worst case INL ADC Transfer Function Output INL Max Real Ideal Most common End-point: Straight line through the endpoints is usually used as reference, i.e. offset and full scale errors are eliminated in INL calculation INL INL Max Input Ideal converter steps found for the endpoint line, then INL is measured INL Curve Digital Output EECS Lecture : Data Converter Performance Metrics H. K. Page ADC Integral Nonlinearity Best-Fit INL = deviation of code transition from its ideal location Output Best-Fit A best-fit line (in the leastmean squared sense) fitted Real Ideal Ideal converter steps found then INL measured Input ADC Transfer Function INL Note: Typically INL #s smaller for best-fit compared to end-point INL Curve EECS Lecture : Data Converter Performance Metrics H. K. Page 8

15 ADC Integral Nonlinearity End-Point INL = deviation of code transition from its ideal location Typically, end-point INL reported in publications Digital Output Code - LSB INL - 8 ADC Input Voltage [Δ] EECS Lecture : Data Converter Performance Metrics H. K. Page 9 ADC Integral Nonlinearity Best Fit versus End-Point Best-Fit A best-fit line (in the least-mean squared sense) Ideal converter steps is found then INL is measured Digital Output Code -/ LSB INL +/ LSB INL Best Fit End-point INL max =LSB Best-fit INL max =+-/LSB - 8 ADC Input Voltage [Δ] EECS Lecture : Data Converter Performance Metrics H. K. Page

16 ADC Integral Nonlinearity Can derive INL by: - Construct uniform staircase between st and last transition INL for each code: T[m] T[ideal] INL[m] = W[ideal] - Can show m INL[m] = i= DNL[i] INL is found by computing the cumulative sum of DNL EECS Lecture : Data Converter Performance Metrics H. K. Page ADC Differential & Integral Nonlinearity Example m INL[m] = i= DNL[i] Code # - DNL [LSB] INL [LSB] - Notice: INL[] undefined INL[]= INL[ N -]= EECS Lecture : Data Converter Performance Metrics H. K. Page

17 DNL [LSB] INL [LSB]. -. ADC Differential & Integral Nonlinearity Example -. Max. DNL -. Max. - INL Code # Code # INL [LSB] - EECS Lecture : Data Converter Performance Metrics H. K. Page DNL [LSB] Can derive INL by: Connect end points Find ideal output values INL for each code: DAC Integral Nonlinearity V[m] V[ideal] INL[m] = V[LSB] - Can show m INL[m] = i= DNL[i] INL is found by computing the cumulative sum of DNL EECS Lecture : Data Converter Performance Metrics H. K. Page

18 DAC Integral Nonlinearity EECS Lecture : Data Converter Performance Metrics H. K. Page DAC DNL and INL * Ref: Understanding Data Converters, Texas Instruments Application Report SLAA, Mixed-Signal Products, 99. EECS Lecture : Data Converter Performance Metrics H. K. Page

19 Example: INL & DNL Large INL & Small DNL Large DNL & Small INL EECS Lecture : Data Converter Performance Metrics H. K. Page Monotonicity Monotonicity guaranteed if INL. LSB The best fit straight line is taken as the reference for determining the INL. This implies DNL LSB EECS Lecture : Data Converter Performance Metrics H. K. Page 8

20 Non-Monotonic DAC segment[m] V[LSB] DNL[m] = V[LSB] segment[] V[LSB] DNL[] = V[LSB]. = =.[LSB]. DNL[] == =.[LSB] DNL< -LSB for a DAC Non-monotonicity When can non-monotonicity cause major problems? Analog Output [LSB] -.. Digital Input EECS Lecture : Data Converter Performance Metrics H. K. Page 9 Non-Monotonic ADC Code associated with two transition levels! For non-monotonic ADC DNL not nonmonotonic steps Digital Output Analog input Δ Δ Δ Δ Δ Δ Δ EECS Lecture : Data Converter Performance Metrics H. K. Page

21 How to measure DNL/INL? DAC: Simply apply digital codes and use a good voltmeter to measure corresponding analog output ADC Not as simple as DAC need to find "decision levels", i.e. input voltages at all code boundaries One way: Adjust voltage source to find exact code trip points "code boundary servo" More versatile: Histogram testing Apply a signal with known amplitude distribution and analyze digital code distribution at ADC output EECS Lecture : Data Converter Performance Metrics H. K. Page Code Boundary Servo Input Digital Code A A<B Digital Comp. B A B i C R ADC Input V REF f S ADC Under Test C i ADC Output EECS Lecture : Data Converter Performance Metrics H. K. Page

22 Code Boundary Servo i and i are small, and C is large, so the ADC analog input moves a small fraction of an LSB each sampling period For a code input of, the ADC analog input settles to the code boundary shown ADC Digital Output Δ Δ Δ Δ Δ Δ Δ ADC Analog Input EECS Lecture : Data Converter Performance Metrics H. K. Page Input Digital Code Code Boundary Servo A A<B Digital Comp. B A B i i C ADC Output R C Good DVM V REF f S ADC EECS Lecture : Data Converter Performance Metrics H. K. Page

23 Code Boundary Servo A very good digital voltmeter (DVM) measures the analog input voltage corresponding to the desired code boundary DVMs have some interesting properties They can have very high resolutions (8½ decimal digit meters are inexpensive) To achieve stable readings, DVMs average voltage measurements over multiple Hz ac line cycles to filter out pickup in the measurement loop EECS Lecture : Data Converter Performance Metrics H. K. Page Code Boundary Servo ADCs of all kinds are notorious for kicking back high-frequency, signal-dependent glitches to their analog inputs R Good DVM V REF f S ADC A magnified view of an analog input glitch follows C EECS Lecture : Data Converter Performance Metrics H. K. Page

24 Code Boundary Servo Just before the input is sampled and conversion starts, the analog input is pretty quiet As the converter begins to quantize the signal, it kicks back charge analog input start of conversion /f S time EECS Lecture : Data Converter Performance Metrics H. K. Page Code Boundary Servo The difference between what the ADC measures and what the DVM measures is not ADC INL, it s error in the INL measurement analog input DVM measures the average input including the glitch How do we control this error? ADC converts this voltage /f S time EECS Lecture : Data Converter Performance Metrics H. K. Page 8

25 Code Boundary Servo A large C fixes this Good DVM At the expense of longer measurement time V REF f S R ADC C EECS Lecture : Data Converter Performance Metrics H. K. Page 9 Histogram Testing Code boundary measurements are slow Long testing time May miss dynamic errors Histogram testing Quantize input with known pdf (e.g. ramp or sinusoid) Measure output pdf Derive INL and DNL from deviation of measured pdf from expected result EECS Lecture : Data Converter Performance Metrics H. K. Page

26 Histogram Test Setup V REF f S Ramp V REF ADC PC Time Slow (wrt conversion time) linear ramp applied to ADC DNL derived directly from total number of occurrences of each the output of the ADC EECS Lecture : Data Converter Performance Metrics H. K. Page A/D Histogram Test Using Ramp Signal Example: Ramp slope: μv/μsec LSB =mv Each ADC code msec f s =khz T s =μsec n = samples/code Digital Output ADC Input/Output Analog input n/f s Ramp Time EECS Lecture : Data Converter Performance Metrics H. K. Page

27 A/D Histogram Test Using Ramp Signal Example: Ramp slope: μv/usec LSB =mv Each ADC code msec Digital Output ADC Input/Output f s =khz T s =μsec n = samples/code n/f s Ramp Analog input # of Samples Per code Time EECS Lecture : Data Converter Performance Metrics H. K. Page Measuring DNL Ramp speed is adjusted to provide large number of output/code - e.g. an average of outputs of each ADC code (for / LSB resolution) Ramp test can be quite slow for high resolution ADCs Example: bit ADC & sampling rate ( or, codes)( conversions/code) =. sec, conversions/sec EECS Lecture : Data Converter Performance Metrics H. K. Page

28 Ramp Histogram Example: Ideal -Bit ADC Digital Output Code ADC characteristics ideal converter Code Count ADC Input Voltage [Δ] ADC output code EECS Lecture : Data Converter Performance Metrics H. K. Page Ramp Histogram Example: -Bit ADC with Error ADC characteristics ideal converter 8 Digital Output Code -. LSB DNL +. LSB INL Code Count 8 +. LSB DNL 8 ADC Input Voltage [Δ] ADC output code EECS Lecture : Data Converter Performance Metrics H. K. Page

29 Example: Bit ADC DNL Extracted from Histogram - Over-range bins removed ( and full-scale) - Compute average count/bin (/= in this case) Code Count, End bins removed 8 ADC output code EECS Lecture : Data Converter Performance Metrics H. K. Page Example: Bit ADC DNL Extracted from Histogram. Normalize: - Divide by average count/bin (ideal bins have exactly the average count, which, after normalization, is ) Normalized Code Count ADC output code EECS Lecture : Data Converter Performance Metrics H. K. Page 8

30 Example: Bit ADC DNL Extracted from Histogram - Subtract from the normalized code count - Result is DNL (+-.Lsb in this case) DNL = Counts / Mean(Counts) ADC output code EECS Lecture : Data Converter Performance Metrics H. K. Page 9 Example: -Bit ADC Static Characteristics Extracted from Histogram Width of all codes derived from measured DNL (Code=DNL + LSB) DNL histogram used to reconstruct the exact converter characteristic (having measured only the histogram) INL- (deviation from a straight line through the end points)- is found Reconstructed Characteristic - 8 ADC Input Voltage EECS Lecture : Data Converter Performance Metrics H. K. Page

31 Example: Bit ADC DNL & INL Extracted from Histogram DNL and INL of Bit converter (from histogram testing) Digital Output Code ADC characteristics ideal converter -. LSB DNL +. LSB INL +. LSB DNL DNL [LSB] INL [LSB] bin # ADC Input Voltage [Δ] - bin # EECS Lecture : Data Converter Performance Metrics H. K. Page ADC Histogram Testing Sinusoidal Inputs Highly linear ramp signals not readily available (>8 tobits) Solution: Use sinusoidal test signal (may need to filter out harmonics) Problem: ideal histogram is not flat but has bath-tub shape ADC Output- Raw Histogram EECS Lecture : Data Converter Performance Metrics H. K. Page

32 A/D Histogram Test Using Sinusoidal Signals At sinusoid midpoint crossings: dv/dt max. least # of samples At sinusoid amplitude peaks: dv/dt min. highest # of samples Digital Output Time ADC Input/Output Analog input Sinusoid # of Samples Per code EECS Lecture : Data Converter Performance Metrics H. K. Page Resulting DNL and INL DNL = +. / - LSB, missing code if (DNL<-.9) DNL [LSB] - code INL = +. / -.9 LSB INL [LSB] - code EECS Lecture : Data Converter Performance Metrics H. K. Page

33 Correction for Sinusoidal PDF References: [] M. V. Bossche, J. Schoukens, and J. Renneboog, Dynamic Testing and Diagnostics of A/D Converters, IEEE Transactions on Circuits and Systems, vol. CAS-, no. 8, Aug. 98. [] IEEE Standard Is it necessary to know the exact amplitude and offset of sinusoidal input? No! EECS Lecture : Data Converter Performance Metrics H. K. Page DNL/INL Code function [dnl,inl] = dnl_inl_sin(y); %DNL_INL_SIN % dnl and inl ADC output % input y contains the ADC output % vector obtained from quantizing a % sinusoid % Boris Murmann, Aug % Bernhard Boser, Sept % histogram boundaries minbin=min(y); maxbin=max(y); % histogram h = hist(y, minbin:maxbin); % cumulative histogram ch = cumsum(h); % transition levels T = -cos(pi*ch/sum(h)); % linearized histogram hlin = T(:end) - T(:end-); % truncate at least first and last % bin, more if input did not clip ADC trunc=; hlin_trunc = hlin(+trunc:end-trunc); % calculate lsb size and dnl lsb= sum(hlin_trunc) / (length(hlin_trunc)); dnl= [ hlin_trunc/lsb-]; misscodes = length(find(dnl<-.9)); % calculate inl inl= cumsum(dnl); EECS Lecture : Data Converter Performance Metrics H. K. Page

34 DNL/INL Code Test % converter model B = ; % bits range = ^(B-) - ; % thresholds (ideal converter) th = -range:range; % ideal thresholds th() = th()+.; % error fs = e; fx = 9e + pi; % try fs/! C = round( * ^B / (fs / fx)); t = :/fs:c/fx; x = (range+) * sin(*pi*fx.*t); y = adc(x, th) - ^(B-); hist(y, min(y):max(y)); DNL [LSB] INL [LSB] DNL = +. / -. LSB, missing codes (DNL<-.9) INL = +. / -. LSB code dnl_inl_sin(y); EECS Lecture : Data Converter Performance Metrics H. K. Page Histogram Testing Limitations The histogram (as any ADC test, of course) characterizes one particular converter. Test many devices to get valid statistics. Histogram testing assumes monotonicity E.g. code flips will not be detected. Dynamic sparkle codes produce only minor DNL/INL errors E.g.,,,,,,, look at ADC output to detect Noise not detected or could improves DNL E.g. 9, 9, 9,, 9, 9, 9,, 9,,,, Ref: B. Ginetti and P. Jespers, Reliability of Code Density Test for High Resolution ADCs, Electron. Lett., vol., pp. -, Nov. 99. EECS Lecture : Data Converter Performance Metrics H. K. Page 8

35 Example: Hiding Problems in the Noise INL missing codes DNL "smeared out" by noise! Always look at both DNL/INL INL usually does not lie... [Source: David Robertson, Analog Devices] EECS Lecture : Data Converter Performance Metrics H. K. Page 9