Integrated Direct RF Sampling Front-end for VHF Avionics Systems

Transcription

1 Integrated Direct RF Sampling Front-end for VHF Avionics Systems Omar Yeste and René Jr. Landry ICNS 2015 April, 22 April, 22 ICNS

2 Outline 1. Introduction 2. Direct RF Sampling: Bandpass sampling 1. Sampling frequency 2. Dynamic range 3. FPGA Architecture 4. Simulation Results 5. Conclusion April, 22 ICNS

3 1. Introduction Benefits of SDR for Aviation Minimization of SWaP-C requirements GHG emissions reduction Design, development and installation time and cost Maintenance, repair and modernization time and cost Reprogrammability & reconfigurability Scalability Reduced number of parts Increased reliability April, 22 ICNS

4 1. Introduction Context of the Work AVIO-505 project Software defined radios for highly integrated system architecture Objectives: Integration of navigation, communication and surveillance systems under a single universal reconfigurable platform Demonstrate the capabilities and performance of SDR in aerospace Address new regulatory initiatives (NextGen) Partners: Academic: ETS Montreal, Ecole Polytechnique Montreal, UQAM Industrial: Bombardier, MDA, Marinvent Corporation, Nutaq April, 22 ICNS

5 1. Introduction SDR: ADC next to the Antenna Interference suppression Bandpass sampling Demultiplexing & Digital down conversion Multisystem receiver Multiband RF filter ADC FPGA Multi-core CPU April, 22 ICNS

6 1. Introduction Objective of the Work Feasibility study of DRFS for VHF systems Challenges: Required sampling frequency - f s ( ) Dynamic range - DR ( ) ADC: f s vs. DR trade-off Implementable: FPGA resources Digital down-conversion Filtering Decimation April, 22 ICNS

7 2. DRFS Sampling VHF Frequency Bands VOR LOC COMM GS April, 22 ICNS

8 2.1. Sampling Frequency Bandpass Sampling 1. Static Approach a) Fixed sampling frequency b) All RF channels available at the FPGA c) Higher ADC FPGA throughput 2. Dynamic Approach a) Sampling frequency depends on spectrum usage b) Vacant channels overlap c) Lower ADC FPGA throughput ( Τ 1 10th of Static) d) Stop to reconfigure (continuity, availability) Algorithm for computing f s in the paper April, 22 ICNS

9 2.1. Sampling Frequency Static Approach (MHz) April, 22 ICNS

10 2.1. Sampling Frequency Dynamic Approach 0 f s 14 MHz April, 22 ICNS

11 2.2. Dynamic Range Sensitivity System Sensitivity Min. Field Max. Input Power Strength Requirement VOR -93 dbm -120 dbw/m 2-27 dbm LOC -87 dbm -114 dbw/m 2-33 dbm GS -77 dbm -95 dbw/m 2-33 dbm System Sensitivity Criterion ACARS -102 dbm (> 99% of messages) VDL -98 dbm BER < 10-3 Voice -105 dbm SINAD < 12 db Spurious Level: < -117 dbm SFDR: > 90 db ENOB: > 12 April, 22 ICNS

12 2.2. Dynamic Range Sensitivity Loss AGC required to avoid saturation Sensitivity loss as a function of received power Distance TX Power SFDR = 95 dbfs Gains/Losses Frequency 200W 25W 10W April, 22 ICNS

13 3. FPGA Architecture Channel Frequency (Register) DDS Multiplex ADC Cosine Sine I Q CIC decimation I Q FIR decimation I Q April, 22 ICNS

14 3. FPGA Architecture Channel Bandwidth April, 22 ICNS

15 3. FPGA Architecture Channel Bandwidth April, 22 ICNS

16 3. FPGA Architecture Design Parameters Item Parameter Static Dynamic ADC Sampling rate 137 MSPS 14.5 MSPS Output word length 14 bits SFDR 96 db DDS Resolution 25 KHz Output word length 16 bits Decimation Number of stages 5 CIC Differential delay 2 Output sampling rate 250 KSPS Input word length 16 bits Output word length 67 bits 51 bits Cutoff frequency 12.5 KHz Passband ripple 0.1 db Stopband attenuation 60 db FIR Decimation 5 Length (number of taps) 88 Output sampling rate 50 KSPS Decimation 5 Output word length (bits) 32 April, 22 ICNS

17 3. FPGA Architecture Resources Used DDS & Mixers CIC FIR 1 Channel Totals 10 Channels Totals Item Absolute Relative Registers % LUTs % Slices % BRAMs 1 0.1% DSPs 2 0.1% Registers 1, % LUTs % Slices % BRAMs 0 0.0% DSPs % Registers % LUTs % Slices % BRAMs 0 0.0% DSPs 2 0.1% Registers 2, % LUTs 1, % Slices % BRAMs 1 0.1% DSPs % Registers 25, % LUTs 12, % Slices 6, % BRAMs % DSPs % April, 22 ICNS

18 4. Results ADC Output 3 db FS 90 db April, 22 ICNS

19 4. Results CH 1 Output April, 22 ICNS

20 4. Results CH 2 Output April, 22 ICNS

21 4. Results CH 3 Output April, 22 ICNS

22 Conclusion Direct RF Sampling is feasible VHF avionics systems Current ADC technology provides enough DR and sampling rate Small sensitivity loss near powerful ground facilities (> 20 dbm) FPGA architecture based on DDS and CIC April, 22 ICNS

23 Future work Implementation into fast prototyping platforms PicoDigitizer Lab Tests Flight Tests Extension to L-Band avionics systems DME/XPDR/UAT Higher bandwidth April, 22 ICNS

24 Questions? Thank you Contact us: April, 22 ICNS