A PROTOTYPING OF SOFTWARE DEFINED RADIO USING QPSK MODULATION

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1 INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14) ISSN (Print) ISSN (Online) Volume 5, Issue 12, December (2014), pp IAEME: Journal Impact Factor (2014): (Calculated by GISI) IJECET I A E M E A PROTOTYPING OF SOFTWARE DEFINED RADIO USING QPSK MODULATION G.Sandhya, Mrs. Arathyiyer 1, 2 Dept. of Electronics and Communication Engineering, SNGCE, Kerala, India ABSTRACT The aim of this thesis is to design and implement a software defined radio based wireless communication system. Software defined radio is a feasible solution for reconfigurable radios, which can perform different functions at different times on the same hardware.the design of the transmission side of a SDR( Digital Modem) based on the use of specialized Digital Up Converters (DUC) where baseband processing is performed and up conversion to Intermediate Frequency (IF) is performed. Similarly in receiver side of digital communication Digital Down Converter (DDC) is used. QPSK is used as both modulation and demodulation techniques. The baseband section of a wireless communication system is first simulated and then implemented in hardware. The performance of the system in real time is also analyzed by implementing the system in hardware using Xilinx Spartan 6E field programmable gate array. A comparison of the simulation results with the results obtained from implementing the system on Spartan 6E hardware is presented and discussed. It is shown that the simulation results and experimental results are similar. Keywords: DDC, DUC, FIR, QPSK. 1. INTRODUCTION Software Defined Radio (SDR) are Radios that provide software control of a variety of modulation techniques wide and narrowband operation, communication security function and waveform requirements of current and evolving standards over a broad frequency range. SDR is a collection of hardware and software technologies that enable re-configurable system architectures for wireless networks and user terminals. SDR provides an efficient and comparatively inexpensive solution to the problem of building multimode, multi-band, multifunctional wireless devices that can be adapted, updated or enhanced by using software upgrades. A working definition of a software defined radio is a radio that is considerably defined in software and whose physical layer behavior can be significantly altered through changes to its software. Thus, the same piece of hardware can be used to realize different applications by modifying the software. The concept of Software-defined radio (SDR) has been around for many years. The ability to perform field upgrades and reconfiguration of waveforms has a large benefit to the military community. But, only recently has semiconductor technology evolved to make SDR possible. Typical architectures implement waveforms in the digital domain using Microprocessors, FPGAs, and DSP Processors. 130

2 Fig 1: Basic Block of SDR 1.1 DUC (Digital Up Converter) The Digital up Converter is a digital circuit which implements the conversion of a complex digital baseband signal to a real pass band signal. The input complex baseband signal is sampled at a relatively low sampling rate, typically the digital modulation symbol rate. The baseband signal is filtered and converted to a higher sampling rate before being modulated onto a direct digitally synthesized (DDS) carrier frequency. The DUC typically performs pulse shaping and modulation of an intermediate carrier frequency appropriate for driving a final analog up converter and is used extensively in wireless and wire line communication systems. The sampling rate is an important cost factor in digital signal processor (DSP) Implementation due to the throughput requirements imposed on the computing platform. A common way to relax the requirements on the analog product in mixed analog-digital system is to use oversampling techniques. This introduces the need for interpolation and decimation filter in the digital part of system. In wide band communication systems where the bit rates are high, these filters must be designed to work at very sample frequencies. Often, the systems are battery powered which means that it is essential to reduce the powercomputation as well. 1.2 DDC (Digital Down Converter) The Digital Down Converter is a digital circuit which implements the conversion of a intermediate frequency signal to baseband complex signal centered at zero frequency. The baseband signal is filtered and converted to a lower sampling rate before being demodulated. In addition to down conversion, DDC s typically decimate to a lower sampling rate, allowing follow-on signal processing by lower speed processors. A DDC consists of three sub-components Direct Digital Synthesizer (DDS) which generates a complex sinusoid at the intermediate frequency, a pair of multipliers to convert from IF to baseband, and a pair of low-pass filters and decimators. The multipliers perform the down-conversion function, but in addition to down-converting by creating a difference signal at the IF minus the DDS frequency. 1.3 QPSK Modulation QPSK or Quadrature Phase-Shift Keying is a higher order modulation scheme used in digital modulation. In satellite or telecommunication system, modulation is the process of conveying a message signal over a medium. To extend the range of the analog signal or digital data, we need to transmit it through a medium other than air. The process of converting information so that it can be successfully transmitted through a medium is called modulation. We are working with QPSK modulation which is kind of a digital modulation. 2. OUR APPROACH The Proposed methodology of prototyping of SDR using QPSK consist design of the transmission side of a SDR( Digital Modem) based on the use of specialized Digital Up Converters (DUC) where baseband processing is performed and up conversion to Intermediate Frequency (IF) is performed. Similarly in receiver side of digital communication Digital Down Converter (DDC) is used. QPSK is used as both modulation and demodulation techniques. 2.1 DUC (Digital Up Converter) A block diagram of the Digital up Converter is shown in Figure Spectral shaping of the complex input signal is performed by the PFIR filter. Typically this filter would be performing a Nyquist transmit filter operation with a ratechange of 2. Bias-free convergent rounding or truncation is employed between each processing stage to limit the bit growth through the DUC. Output from each of the PFIR filters is input to each of the CFIR filters, which is used to compensate for the droop within the CIC filter and performs the second rate-change. The CFIR also performs a rate-change of 2. The CFIR 131

3 filter s output drives the input to the interpolating CIC filter, which is used for high sample rate change of 4. The complex data stream from the CIC filter is mixed with a local oscillator generated by the DDS. Results from the mixers are combined, forming the final DUC result. The DUC result is often used as the input to a digital-to-analog converter (DAC) to generate an intermediate frequency analog signal. Fig 2.1: BLOCK DIAGRAM OF DUC 2.2 PFIR (Pulse Shaping FIR Filter) FIR filters P(z) operate on the sequences di(j) and dq(j) applied to the DUC input ports DIN_I and DIN_Q. The sequences di(j) and dq(j) are up sampled by a factor of 2 by filtering with the Pulse Shaping Filter coefficients p(k), with the resulting sequences u(k) sampled at a rate of Fsk = 2Fs. The pulse shaping finite impulse response filter P(z) typically conditions the transmitter signal s channel response and inter symbol interference characteristics. Pulse shaping techniques are intended to decrease the profile of the transmitted signal, without compromising its information bearing properties, so that all the system creates less overall interference with one another. The CFIR and PFIR are polyphasemultirate filter structures that interpolate by a factor of 2, 4, or 8. Fig 2.2: BLOCK DIAGRAM OF PFIR FILTER 2.3 CFIR (Compensating FIR Filter) Compensation filter is a type of FIR filter used to compensate for loses in cascaded integrator comb(cic) filter in the typical filtering applications a reasonably flat pass band and narrow transition region filter performance is required. These desirable properties are not provided by the CIC filters alone, with their drooping pass band gains. Compensation filter C(z) provides a sampling rate increases of 2 (interpolation) as shown in figure3.2.2a, and filter is intended to compensate for the roll-off in the pass-band of the 3rd stage CIC filter. Typically, the C(z) will have a wide transition band to minimize the filter length. The coefficients needed to compensate for the CIC roll-off depend on the number of comb (differentiator) stages implemented in the CIC filter. Fig 2.3: BLOCK OF CFIR FILTER 132

4 2.4 CIC Filter (Cascaded Integrator Comb Filter) Cascaded integrator-comb, also called Hogenauer filters, are multi-rate filters that are used for realizing large sample rate conversions in digital systems. The main advantage of this filter is it does not use multipliers, and consists of only adders, subtractors and registers. They are typically employed in applications that have a large excess sample rate. That is the system sample rate is much larger than the bandwidth occupied by the signal CIC Interpolator Filter A CIC interpolation filter, as shown in figure 4, has two major sections: a comb section, which is a cascade of N combs and an integrator section, which is a cascade of N integrators. There is an interpolator or rate expansion switch (change by a factor R) between the two filter sections. The rate change switch is also known as a zero-stuffer as it pads zeros. The interpolator up samples the output of the last comb stage increasing the sample rate from fs/r to fs. One of the distinguishing factors of CIC filters is, the sampling rate of Comb filters is different from sampling rate of integrator, and i.e. the comb runs at a lower sampling frequency, which makes it easily programmable. Figure gives a detailed structure of a CIC interpolator. FIG 2.4.1: CIC INTERPOLATION FILTER CIC Decimation Filter A Multirate filter system is needed in the receiver; such filter can be implemented using a Cascaded Integrator- Comb (CIC) filter. The CIC is a linear phase FIR filter implemented without the use of multiplication operations operating as a multirate filter to connect two signal processing system components operating at different sampling frequencies. FIG 2.4.2: CIC DECIMATION FILTER 2.5 Direct Digital Synthesiser A Direct Digital Synthesizer (DDS) also known Numerically Controlled oscillator (NCO) synthesizes a discrete-time, discrete valued representation of a sinusoidal waveform. It is an established method of generated periodic sinusoid signals whenever high frequency resolution, fast changes in frequency and phase, and high spectral purity of the output signal is required. A major advantage of the DDS is that its output frequency, phase and amplitude can be precisely and rapidly manipulated under digital processor control. 133

5 2.6 DDC (Digital Down Converter) The Digital Down Converter is a digital circuit which implements the conversion of a intermediate frequency signal to baseband complex signal centered at zero frequency. The baseband signal is filtered and converted to a lower sampling rate before being demodulated. In addition to down conversion, DDC s typically decimate to a lower sampling rate, allowing follow-on signal processing by lower speed processors. The DDC receives an incoming digital IF signal and modulates the signal into baseband and produces an inphase signal and a Quadrature signal as outputs. The design of the DDC can be implemented using FPGAs. The Quadrature demodulation is performed by the multiplication of the IF signals with a digital oscillator, the implementation of the digital oscillator is accomplished using a direct digital synthesizer (DDS). Fig 2.6: Block of DDC 2.7 QPSK (Quadrature Phase Shift Keying) Modulation/ Demodulation Modulation is very important block in communication system to transmit the data through channel without loss of data & to reduce size of antenna incase of wireless communication it is also important aspect for FDM. Because of these requirements many models are proposed to design a stable & low power modulator because the requirement of the sine wave as carrier most of the previously proposed models uses the analog circuitry for modulators but the stability of the analog system very much depends upon physical condition of the device as temperature, humidity etc. hence to make design robust & immune to physical conditions we are here proposing the FPGA based technique which not only improves the stability but also the power requirement of the system it also works on higher bit rate than the previously proposed analog systems. The proposed model involves a FPGA based 4X1 multiplexer, one clock & four delay blocks to produce four phases then the output is filtered by the analog filter to produce smooth sinusoidal wave at the output. Fig 2.7: BLOCK OF QPSK MODULATION QPSK demodulation techniques is used in the receiver section where we need to demodulate and convert to data which a user can retrieve the send message. Demodulation technique is vice versa of the process shown in the modulation technique. 2.8 Transmitter end of SDR A radio contains a transmitter and receiver. A simplistic explanation of a radio transmitter is a device that puts a voice frequency message onto an RF signal and transmits that message over the air. This is done by converting the mechanical vibrations of the voice message to electrical pulses, amplifying those pulses, modulating that message onto an RF carrier (by mixing the signal with an oscillator), amplifying that RF signal, and transmitting it via an antenna as shown in fig

help of DDS and taking that as output from the mixers of the Digital Up Converter block and modulating and sending which is shown in the fig 3.4. 2.

6 Fig 2.8: Block of Transmitter In the thesis, explained the two blocks of transmitter one is digital up converter which helps to increasing the data rate of the message and mixing it carrier signal with the help of DDS and taking that as output from the mixers of the Digital Up Converter block and modulating and sending which is shown in the fig Receiver end of SDR A radio receiver is a reverse of the process. The received RF signal is amplified and filtered; the voice message is detected (separated) from the RF signal; it is amplified then converted to mechanical vibrations which represent the message. Digital radios digitize the message with an ADC and manipulate the digital signal with a DSP as shown in fig 2.9. Fig 2.9: Block of Reciever In this thesis, the proposed method shown the working of the receiver with the help of two blocks one is digital down converter and demodulator. 3. SIMULATION RESULTS AND DISCUSSIONS 3.1 Pulse Shaping FIR filterp(z) It provides a sampling rate increase of 2 and typically performs transmitter Nyquist pulse shaping. Here we are increasing the data rate of the input data which will provide the added advantage like fast transfer of data and reduces the loss due to interference. Initially we are supplying a 3bit input which will be converted to 8bit output which is again fed to the CFIR filter where again we increase the bit size of the output of the CFIR. FIG 3.1: SIMULATION OF PFIR 3.2 Compensation Fir Filter The second filtering stage is CFIR, internally the CFIR has a MAC unit. The output of PFIR is given to CFIR. The CFIR stage is a real filter operating on a complex input signal. The Compensation filter CFIR operates on lower sampling rate of the signal as compared to the CIC filter that operates at a higher sampling rate, interpolation factor for each filter. FIG 3.2: SIMULATION OF CFIR 135

3.3 CIC FILTER 3.3.1 CIC INTERPOLATOR FILTER For transmitter, a CIC interpolation filter should be used since it provides excellent results with low computational load.

The design of both stages is related to the increase ratio between the input (low sample rate frequency) and the output(high sample rate frequency) of the filter.

The low sampling comb stage followed by the high sampling integrator stage employs a low pass linear phase FIR filter. FIG 3.

7 3.3 CIC FILTER CIC INTERPOLATOR FILTER For transmitter, a CIC interpolation filter should be used since it provides excellent results with low computational load. A standard interpolation filter implementation is composed of a zero-insertion phase and a low pass filter phase. The design of both stages is related to the increase ratio between the input (low sample rate frequency) and the output(high sample rate frequency) of the filter. The CIC interpolation filter implements both phases using a unique design approach. The low sampling comb stage followed by the high sampling integrator stage employs a low pass linear phase FIR filter. FIG 3.3.1: SIMULATION OF CIC INTERPOLATOR CIC DECIMATION FILTER A Multirate filter system is needed in the receiver; such filter can be implemented using a Cascaded Integrator- Comb (CIC) filter. The CIC is a linear phase FIR filter implemented without the use of multiplication operations operating as a multirate filter to connect two signal processing system components operating at different sampling frequencies. FIG 3.3.2: SIMULATION OF CIC DECIMATION 3.4 DUC (Digital Up Converter) After synthesis is done coming to FPGA implementation. For the FPGA implementation Spartan 3E kit and the logic analyzers are used. The logic analyzer is used to see the output wave from in digital format. Field Programmable Gate Arrays (FPGAs) are the leading implementation path for reprogrammable, high performance applications like Digital Signal Processing (DSP). FIG 3.4: SIMULATION OF DUC 136

3.5 DDC (Digital Down Converter) After synthesis is done coming to FPGA implementation. For the FPGA implementation Spartan 3E kit and the logic analyzers are used.

Field Programmable Gate Arrays (FPGAs) are the leading implementation path for reprogrammable, high performance applications like Digital Signal Processing (DSP). FIG 3.5: SIMULATION OF DDC 3.

Here we simulated a QPSK design with modulator at one end and demodulator at another end to confirm the working of QPSK modulator and Demodulator that they retrieve data or performs viceversa. FIG 3.

8 3.5 DDC (Digital Down Converter) After synthesis is done coming to FPGA implementation. For the FPGA implementation Spartan 3E kit and the logic analyzers are used. The logic analyzer is used to see the output wave from in digital format. Field Programmable Gate Arrays (FPGAs) are the leading implementation path for reprogrammable, high performance applications like Digital Signal Processing (DSP). FIG 3.5: SIMULATION OF DDC 3.6 QPSK Modulation/Demodulation In this part of paper, we provide the simulation results for testing the Verilog HDL code modulator. Here we simulated a QPSK design with modulator at one end and demodulator at another end to confirm the working of QPSK modulator and Demodulator that they retrieve data or performs viceversa. FIG 3.6: SIMULATION OF QPSK Modulator/Demodulator 3.7 Prototype of SDR The model for SDR Transmitter and Receiver is developed based upon specification using Xilinx Spartan 6E. Hardware is modeled in HDL and simulated using Isim. FIG 3.7a: RTL VIEW OF PROTOTYPE SDR FIG 3.7b: SIMULATION OF PROTOTYPE SDR 3.8 Summary In this Chapter, the experimental setup, simulation and corresponding results for the baseband section of a wireless communication system is presented. The parameters set to carry out the simulation were also presented. Also real time implementation of the system is presented. The results obtained from the simulation were discussed and the simulation results were compared with the results from real time implementation. It was demonstrated that the results obtained from simulation and hardware implementation are the same. 137

9 4. ADVANTAGES AND DISADVANTAGES OF SDR It is believed by many that the successful deployment of SDR will revolutionize the field of communication. One of the advantages of SDR is that it can be changed quickly to support multiple standards. The ability to configure devices, which may be used by many communication systems (e.g., cellular phones, wireless-fidelity (WI-FI) transceivers, frequency modulation (FM) and analog modulation (AM) radios, terminals of satellite communications), will be remarkable. With SDR, the same piece of hardware will be configured to perform different functions. The reconfigurability of the platform will ensure hardware reusability. System re-programmability allows hardware reuse until a new generation of hardware platforms is available. This will provide cost and time savings. Manufacturers will not be limited to reduced hardware platform set. As a consequence, mass production will allow lowered costs. Another advantage of SDR would be the possibility to improve the software in successive steps, and the correction of software errors and bugs discovered during the operation. In addition, SDR can enhance the interoperability of different systems in many applications such as the military, law enforcement, or search and rescue teams. Incompatibility of radio systems that has always hindered the seamless operation of the military, the law enforcement agencies and many rescue teams, will be eliminated. With the increase of channel data rates through multiplexing and spectrum spreading, SDR could be used in cellular networks, GSM based PCS network, and future generation systems network. A new approach to wireless base station design using SDR has the potential of offering significant benefits such as reduced size, complexity, and power consumption. More importantly, SDR can support a variety of air interface standards, modulation schemes and protocols, simultaneously. Some commercial telephone service providers have begun expressing interest in the SDR economic benefits in long term. More highlights on the benefits of SDR are given in Section. While SDRs offer benefits as outlined above, there are drawbacks in the design and implementation of SDR. Those include: (1) The difficulty of designing software for various target systems or standards. (2) The difficulty of designing air interfaces to digital signals and algorithms for different standards. (3) The problem of poor dynamic range in some communication systems design. 5. CONCLUSION This thesis consists of two major tasks. First, a study of the software defined radio concept and, second test bed development and implementation of software radio transmitter and receiver. The first task of this thesis was to investigate the current state of the art in software defined radio. This is a very large subject area with many promising applications. The second task is to build a software defined radio based wireless communication system. In this thesis, the baseband section of the communication system was simulated and then targeted to hardware implementation. 6. REFERENCES [1] Design and FPGA Implementation of High Speed, Low Power Digital Up Converter for Power Line Communication Systems. European Journal of Scientific Research, ISSN X Vol.25, No.2 (2009), pp , EuroJournals Publishing, Inc [2] Eugune B Hogenaver, An economical class of digital filters for decimation and interpolation, IEEE transaction on acoustics, speech, and signal processing, Vol.29, No.2, pp , April [3] XilinxlogiCORE, Digital Up Converter (DUC) v1.4, DS276 May 23, 2005 inx.com. [4] Ulversøy: software defined radio: challenges and opportunities ieee communications surveys & tutorials, vol. 12, no. 4, fourth quarter [5] J. Mitola, III, The software radio architecture, IEEE Commun. Mag., vol. 33, no.5, May 1995, pp [6] E. Buracchini, The software radio concept, IEEE Commun. Mag., vol. 38, no. 9, Sep. 2000, pp [7] R. Baines, The DSP bottleneck IEEE Commun. Mag., vol. 33, issue 5, May 1995, pp [8] Z. Kostic and S. Seetharaman, DSPs in Cellular radio communications, IEEE Commun.mag., vol. 35, issue 12, dec pp [9] Gaurav Purohit, Divya Vyas, Kota Solomon Raju, V.K Chaubey and Arvind Nehra, Hardware Co-Simulation of BPSK and QPSK for Software Defined Radio, International Journal of Electronics and Communication Engineering & Technology (IJECET), Volume 4, Issue 7, 2013, pp , ISSN Print: , ISSN Online:

Keywords: CIC Filter, Field Programmable Gate Array (FPGA), Decimator, Interpolator, Modelsim and Chipscope.

Keywords: CIC Filter, Field Programmable Gate Array (FPGA), Decimator, Interpolator, Modelsim and Chipscope. www.semargroup.org, www.ijsetr.com ISSN 2319-8885 Vol.03,Issue.25 September-2014, Pages:5002-5008 VHDL Implementation of Optimized Cascaded Integrator Comb (CIC) Filters for Ultra High Speed Wideband Rate