ADX216. ADC Interleaving IP-Core

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1 VER R1102P ADC Interleaving IP-Core FEATURES Doubled Sampling Rate of ADCs Wide Signal Bandwidth Self Calibration Resolution up to 16 Bits Available for CMOS-Processes or FPGAs Integration with any Nyquist-rate ADCs Low Power Dissipation APPLICATIONS Wireless Communication Software Defined Radio Medical Imaging Measurement and Instruments Radio Base Stations High-Speed Data Acquisition Radar Systems The ADX216 interleaving IP-core enables superior ADC performance by means of digital post-processing of timeinterleaved ADCs. By using ADX216 in conjunction with two ADC cores the sample rate is doubled compared to usage of a single ADC core. This results in substantially increased usable signal bandwidth. By using the ADX216 the usable signal bandwidth is stretched to 90% of the ADC array Nyquist frequency. This makes it ideal for applications requiring wide signal bandwidth. The IP-core estimates and removes the distortion, originating from ADC channel mismatch, transparently and without a need for a specific calibration signal. SYSTEM LEVEL BLOCK DIAGRAM Figure 1 gives an overview of how the ADX216 is integrated with two ADCs. The interleaving core can be used together with any Nyquist-rate ADCs from the vendor of your choice. INP INM A/D A/D D15_A - D0_A OVR_A D15_B - D0_B OVR_B ADX216 core Figure 1. System level overview D15 - D0 FUNCTIONAL BLOCK DIAGRAM The internals of the core is depicted in Figure 2. Mismatch is estimated and the result is fed to the reconstructor which corrects the data from the ADCs. OVR OPERATION Due to the tolerances in production there is always a minor variance in geometries over a chip. This results in mismatch of the ADCs characteristics. The IP-core removes this mismatch digitally. Also, the characteristics of the ADCs changes over time by temperature drift and ageing, therefore the core continuously monitors the input and corrects the signal to achieve maximum performance. The estimation is performed autonomously in the background without any need for interaction or programming. Neither is there a need for a specific calibration signal, since the estimation is done on runtime input to the system (so-called blind estimation). Signals can only be reconstructed for a specific Nyquist zone, which is selectable by input to the IP-core. D15_A - D0_A D15_B - D0_B Reconstructor D15 - D0 Estimator OVR_A OVR_B SELB Control ADX216 OVR Figure 2. ADX216 block diagram This datasheet contains preliminary information and is therefore subject to change. SP Devices reserves the right to change or discontinue this product without notice. Trademarks and registered trademarks are the property of their respective owners. Copyright 2011, SP Devices. All rights reserved.

2 THEORY OF OPERATION In an ideal case, the resolution of a time-interleaved ADC system is equal to that of each individual converter. However, there is a significant problem associated with time-interleaved ADCs. Besides the non-ideal performance characteristics common to all ADCs, new errors arise from the parallelization itself and are introduced by the differences between the individual ADCs used in the time-interleaved ADC system. These errors are referred to as channel mismatch errors, and give rise to non-linear distortion that degrades the resolution. Therefore, in order to reach ideal performance, a timeinterleaved ADC system would require all subconverters to behave identically. If not, the system will not be equivalent to one single ADC working at N times higher sampling frequency. For the example below, f s is the sampling frequency, and f in is the input single-tone frequency. One of the most severe channel mismatch errors occurring in a time-interleaved ADC system is aperture delay mismatch. The aperture delay of an ADC is the time difference between when a sample is supposed to be taken and when the sample is actually taken. In the frequency domain, aperture delay mismatch of two time-interleaved ADCs causes image spurs at f s/2 - f IN as shown in Figure 3 below. The spurs originating from aperture delay mismatch coincide with gain error spurs. The offset mismatch produces spurs that are located at f s/2. The frequency dependent gain mismatch causes image spurs at f s/2 - f IN. As illustrated in Figure 4 the interleaving IP-core typically suppresses the spurs with over 60 db, resulting in a dynamic range which is no longer limited by the spurs introduced by interleaving. Figure 3. Large mismatch spurs occur without correction. Figure 4. By using ADX216, mismatch errors no longer limit the dynamic range. 2 Copyright 2011, SP Devices. All rights reserved.

3 SIGNAL ASSIGNMENTS Name Input D0_A D15_A OVR_A D0_B D15_B OVR_B RESET CONTROL Output D0... D15 OVR DRY Description Data from ADC channel A Overflow signal from ADC channel A Data from ADC channel B Overflow signal from ADC channel B Sample clock Reset Control ports (estimation, bypass and register access) Data output Overflow output Data ready FPGA IP CHARACTERISTICS Parameter Virtex-5 SX Series Unit Sample Rate [f s] Max 2200 MSPS Latency 13 Clock Cycles Startup Estimation Time Seconds Nyquist zones supported No limit N/A IP Protection 2 Yes N/A FPGA IP RESOURCE UTILIZATION Parameter Virtex-5 SX Series Unit DSP48 69 slices Block RAM 37 blocks DCM 1 blocks PLL 1 blocks BUFGCTRL 10 blocks Slice registers < Slice LUTs < Time count starts after FPGA has been programmed and is activated. [Typical value] 2 For FPGAs, the IP-core is license protected through a supplied Secure EEPROM which has to be connected directly to the core 3 Copyright 2011, SP Devices. All rights reserved.

4 PERFORMANCE CHARACTERISTICS Parameter Max Unit Resolution 16 bits Bandwidth 90% of Nyquist frequency ENOB* 13.0 bits SNDR* 80 db SFDR* 80 dbc RELATIVE PERFORMANCE CHARACTERISTICS ** Parameter Max Unit ENOB loss (*)(**) 0.1 bits SNDR loss (*)(**) 0.6 db SFDR loss (*)(**) 1.0 db * All performance characteristics guaranteed after specified estimation. ** All losses are defined as deterioration of the performance of the individual ADCs 4 Copyright 2011, SP Devices. All rights reserved.

5 ESTIMATION The estimation of the ADC mismatch is activated when the average signal power is high enough in the estimation active band. For estimation to occur data bursts of more than samples that complies with the average signal power requirement must be detected. Given that the input data fulfils the requirements needed for estimation, specification performance will be guaranteed within 1200 milliseconds from system start up. In Figure 5 and Figure 6, the estimation and reconstruction frequency windows for an IP-core configured for the first Nyquist zone are illustrated. Required average signal power Band Note -46dB 0.05f s f s except energy at 0.25f s Blind estimation window 0.05fs 0.25fs Frequency 0.45fs 0.5fs Figure 5. Blind estimation window Reconstruction window 0.25fs Frequency 0.45fs 0.5fs Figure 6. Reconstruction window 5 Copyright 2011, SP Devices. All rights reserved.

6 TYPICAL CHARACTERISTICS Figure 7. Before and after correction for a 70.2 MHz input signal (Interleaved f s = 800 MHz) Figure 8. Before and after correction for a 1-carrier 90 MHz WCDMA input signal (Interleaved f s = 400 MHz) 6 Copyright 2011, SP Devices. All rights reserved.

7 NOTES ESTIMATION Single-tone input If the input signal is a pure sinusoidal in the estimation band, the system will adapt to this signal content and provide an output according to specification. However, the system may only observe a local optimum as the errors may be frequency dependent. If the tone is changed rapidly, or other signals are input later, and there is substantial frequency dependence of the channel mismatch the system needs time for a recalibration, which is performed automatically. This is only necessary when provided with a single sinusoid or other extremely narrow-band signal; any other signal content will provide the algorithm with full information necessary for estimating the full specification band. PERFORMANCE The system properties are inherited from the ADCs used, for instance 12 bits ENOB for the individual ADCs give essentially 12 bits ENOB output for the interleaved system. The maximum performance figures are defined as the maximum possible performance the IP core can guarantee for the interleaved system. The IP core will preserve the effective resolution of the individual ADCs up to an ADC individual ENOB figure of Max_ENOB + Max_ENOB_Loss (for this version bits), at twice the sampling rate. Signal content only in prohibited calibration bands If the signal content is only in the prohibited estimation bands, the system cannot estimate the ADC channel mismatch. The system will in these cases be in hold mode, and start estimation immediately when signal content is provided in the defined calibration band. An example of such a signal is a stationary sinusoid in 0.25f s. 7 Copyright 2011, SP Devices. All rights reserved.

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