DDSWG: Direct Digital Synthesis Waveform Generator

Transcription

1 DDSWG: Direct Digital Synthesis Waveform Generator M. J. Bright 1 and Y. Li 2 School of Engineering Christchurch Polytechnic Institute of Technology PO Box 540, Christchurch 8140, NEW ZEALAND. 1 matt1003@gmail.com and 2 liy@cpit.ac.nz Abstract: This paper discusses the development of a direct digital synthesis waveform generator as a forty week project, contributing to over thirty percent of a BEngTech student s final year grades. The waveform generator uses a numerically controlled oscillator to digitally synthesize standard and arbitrary waveforms up to a frequency of 5MHz, with adjustable output voltage ranging from 5mV (p-p) to 10V (p-p) and DC offset between 5V DC. The 32-bit phase accumulator and the 8-bit phase to amplitude converter were implemented within programmable logic Xilinx s Spartan-IIE FPGA. With the success of implementing the digital section of the DDS waveform generator and the design flexibility of VHDL and FPGAs, four DDS waveform generators have been synthesized within the FPGA, each with independent wave shape, frequency, and phase control. Keywords Direct Digital Synthesis, Waveform Generator, Function Generator, Arbitrary Waveform, Phase Accumulator, Phase to Amplitude Converter, Numerically Controller Oscillator, Frequency Control Word, Phase Control Word, BEngTech, Final Year Project. 1. INTRODUCTION The Direct Digital Synthesis (DDS) Waveform Generator is one of the many projects being carried out by final year BEngTech students at Christchurch Polytechnic Institute of Technology (CPIT). These projects span forty weeks, each with a five hundred dollar budget. Students are expected to commit four hundred hours to the project, over the forty week period, with the project results contributing to over thirty percent of their final year grades. Students are required to complete the entire design process, including development, simulation, construction, and testing; producing a working prototype of their final design. The DDS waveform generator project is being carried out by a single BEngTech student, reporting to a project supervisor weekly. This includes development of embedded software designs, embedded digital designs, and analogue and PCB designs. The final prototype will be capable of producing standard waveforms, such sinusoidal, square, and triangle, as well as arbitrary waveforms, with frequency ranging from 0.01Hz to 5.0MHz. Additional controls include adjustable output voltage ranging from 5mV (p-p) to 10V (p-p) and DC offset between 5V DC. Due to the current success of implementing the digital section of the DDS waveform generator, multiple waveform generators have been incorporated into the project, allowing for phase control to be introduced, ranging between DIRECT DIGITAL SYNTHESIS Direct digital synthesis uses digital techniques to produce standard and/or arbitrary waveforms within a range of frequencies [1]. The desired waveform is obtained by sampling the instantaneous amplitude values which are stored in memory. This memory is known as the Phase to Amplitude Converter (PAC). The frequency of the waveform is determined by the number of clock cycles that are taken for the subsequent amplitude value to be sampled and then output to the digital to analogue converter (DAC). This is achieved by using a numerically controlled oscillator (NCO) to address the memory. A constant value, the frequency control word (FCW), is added to the current PAC address once per clock cycle. This numeric feedback causes the NCO to increment through the waveform amplitude samples at a rate determined by the FCW. Phase can also be controlled by adding a constant value, the phase control word (PCW), after the NCO, causing a constant number of amplitude waveform samples to be skipped. The operation described above, simply constructed from two adders and a latch, forms the heart of DDS, known as the Phase Accumulator (PA) [2]. Additional features such as frequency shift keying (FSK) and phase shift keying (PSK) can easily be added by multiplexing several FCWs/PCWs; the multiplexer being controlled by an internal timer or external trigger. DDS waveform generators are becoming more cost effective and can produce higher frequencies as digital technology continue to advance. Advantages

2 of direct digital synthesis over conventional analogue techniques include: High accuracy and stability of frequency. High control of frequency resolution. Low phase noise and distortion. Ability to perform very wide frequency sweeps. Ability to produce unique/non-standard/user defined (arbitrary) waveforms. Ability to control each parameter of a waveform; including frequency, phase, symmetry, and amplitude. The greatest limitation of DDS is Jitter. Jitter is caused when the FCW is not a multiple of the total number of amplitude samples within the PAC. When the FCW is greater than the Natural Frequency (the maximum frequency at which the waveform is not sampled), sharp 1-clock edges, in waveforms such as square waves, will full within a small rage samples for a repeatedly sampled waveform. This causes the sharp rises and falls within a waveform to appear to shift left and right at the same rate as the output frequency. Jitter is often avoided by limiting waveforms with sharp 1-clock edges to the natural frequency of the DDS system. 3. PROJECT BACKGROUND 3.1 Project Description The project was chosen to be undertaken based on the following project description, which outlines the initial scope of the project. Develop a numerically controlled oscillator (NCO) driven function and arbitrary waveform generator. The waveform generator will be able to digitally synthesise standard waveforms of the sine, triangle (also sawtooth), square wave types and arbitrary waveforms up to or greater than 1MHz, with an output impedance of 50 and an output voltage of up to 20V. The hardware used will either be a FPGA or DSP Microcontroller. The system will have an interface enabling the user to easily specify the wave shape. [3] Upon further negotiation, it was decided that the scope be reduced to a 10V (p-p) output signal and have arbitrary waveform generation as an optional extra, to reduce the workload of the project. 3.2 Professional DDS Designs It was recommended that Thurlby Thandar Instruments TG1010 Programmable 10MHz DDS Function Generator [2] be used as a base line for this project; the same DDS waveform generator commonly used in CPIT laboratories. The TG1010 stores one complete period of each waveform in the PAC, each defined as bit instantaneous amplitude samples. The samples are then reconstructed using a 10-bit DAC. The phase accumulator is 38-bits wide, although only the ten MSB address the PAC. This provides a frequency resolution of up to 0.1mHz from a ~27.5MHz clock by producing incremental steps less than the addressed section of the PA bus. A digitally controlled seven stage elliptical low-pass filter after the DAC allows sine waves to be sampled very close to Nyquest s sampling theorem; a maximum output frequency of 10MHz. This filter is bypassed for all other waveforms. The problem of jitter has been avoided by limiting non-sinusoidal waveforms to the natural frequency (~27kHz) with exception to the square wave, which above the natural frequency is produced by applying a sine wave to a comparator. 3.3 DDS Design Options The most important part of the DDS waveform generator project was the development of the phase accumulator and phase to amplitude converter. Several alternatives were developed for implementing a 32-bit PA and 8-bit PAC, both intended to operate at 50MHz, these include: Discrete Logic. This included constructing the digital design from discrete ICs, including latch, adder, RAM and ROM components. The downside was this would make PCB design very difficult with multiple high speed buses running between components Programmable Logic. This eliminates noise and crosstalk issues associated with using discrete logic, makes PCB design much simpler, and also allows for greater design flexibility [4]. The downside of using programmable logic would be the time required to learn a hardware description language such as VHDL or Verilog Microcontroller. Used by many amateur designs, a PA is very simple to construct using assembly language, and internal program memory is often used as the PAC. On the other hand, limitations of using a microcontroller include: I. Unlike digital systems which take a single clock cycle to output an amplitude sample, software takes a number of clock cycles; thus reducing the maximum output frequency. II. If the same microcontroller is used for both DDS and human interface, the software must stop sampling/generating the waveform each time the human interface is used ASICs. Analog Devices have developed a range of integrated complete DDS ICs, each including an internal DAC and serial interface. The AD9850, one of Analog Device s midrange DDS ICs, has a maximum output frequency of 62.3MHz with a resolution of 0.029Hz; and also includes 360 phase control [5]. Its 10-bit DAC produces a differential current output. The major limitation is that the entire range is limited to producing only the sinusoidal

3 waveform, which cannot be changed as the PAC is an internal ROM. 3.4 DDS Design Selection Programmable logic has advantages in implementing direct digital synthesis as discussed in previous section. Use of FPGA has been proved to be popular in electronics design. Examples include designing transmitter and receiver for a digital radio system [6] and implementing MAC [7] in FPGA. Due to personal interest in learning more about programmable logic, it was decided that the Spartan- IIE FPGA would be used to implement the digital design. 4. WORKED DESIGN The worked design of the DDS waveform generator can be broken down into three key sections, the digital design, analogue design, and software design. 4.1 Digital Design The digital design has been developed in Xilinx s Spartan-IIE FPGA, using the Spartan-IIE project board developed by BurchedED Australia [8]. This design is responsible for implementing the phase accumulator and phase to amplitude converter, as well as the command decoder. The block diagram of the digital design is shown in Figure 1. The frequency control word, phase control word, and phase accumulator buses are all 32-bits wide. Therefore, for the smallest FCW, it will take 16,777,216 clock cycles before the PA addresses the next amplitude sample within the phase to amplitude converter. This provides a minimum output frequency and frequency resolution of 0.01Hz, for a system clock of MHz; this clock provided by the Spartan-IIE board. Independent of this clock the PCW provides a maximum output phase shift ranging between 360 with a resolution of 8.38x10-8 ; however this resolution has been limited to within the software design for practical reasons. The eight MSBs of the PA are used to address the PAC, providing a maximum number of 256 instantaneous amplitude samples (phase increments). With the ~42.9MHz system clock, this produces a natural frequency of approximately 168kHz. Each amplitude sample is represented by an 8-bit word with a value between 0 and 255. This provides a simple structure to encode in both the microcontroller and FPGA, as the former is an 8-bit system, and the latter has limited sized RAM blocks. Due to the lack of read only memory (ROM) within the FPGA, the 256 amplitude samples for each waveform have been stored within the program memory (flash memory) of the microcontroller. Upon waveform selection, these amplitude values will be loaded into the PAC through the 8-bit parallel Data Bus between it and the microcontroller. User defined waveforms (for optional extra arbitrary waveform design) can be stored in the E 2 PROM within the microcontroller. Finally, upon each positive edge of the system clock, the amplitude value within the PAC, pointed to by the PA, is loaded into the DAC to be converted into a 20mA (p-p) differential output current. This is achieved using Burr Brown s DAC904, a 160MSps 14-bit parallel input, differential current output, DAC. It is important to note that only the top eight MSBs of the DAC are currently used in this design. The lower six bits can be incorporated at a later stage, to produce a higher quality output, by updating the FPGA design. The FCW and PCW latches provide two important functions. Firstly, along with the de-multiplexer, it allows the FCW, PCW, and waveform amplitude samples to be transferred and loaded through the single 8-bit Data Bus. Secondly it provides an interface between the 8-bit microcontroller and 32-bit Microcontroller ATmega128 FPGA Spartan-IIE DAC DAC904 Data Bus Interface Control Control Bus From Human Interface 8-Bit 8-Bit FCW Latch PCW Latch Command Decoder 32-bit Adder/ Subtracter Frequency control Result Latch Phase Accumulator 32-Bit 32-bit Adder/ Subtracter Phase control 8-bit wide 256kB RAM Wave Shape control Phase to Amplitude Converter 8-Bit Digital to Analogue Conversion To Analogue Design Figure 1: The block diagram of the digital design

4 phase accumulator. This is achieved by controlling four 8-bit latches in parallel. The phase accumulator result latch stores the previous result from the phase accumulator. This allows the phase accumulator to determine the new result without interfering with the PAC address bus and its own numeric feedback. What about the maximum output frequency? This is dictated alone by Nyquist s Sampling Theorem. For the digital design, it is intended that the maximum sample rate be samples per period of the sine wave (note: a sample rate of this accuracy is easily obtainable, due to the size of the FCW). At the system clock of MHz, this maximum sample rate will produce a maximum frequency of exactly 5.00MHz. The maximum sample rate, and therefore the maximum frequency, will be regulated by the software design. The command decoder has been implemented using a small ROM block. The lower 5-bits of the 8-bit parallel Command Bus are used to address this ROM, providing up to thirty-two different commands. The remaining three bits make up command enable, and command decoder enable, which allows for up to four command decoders (i.e. DDS waveform generators) to be controlled from the single Command Bus. 4.3 Analogue Design The analogue design is responsible for output voltage control and output DC offset control, as well as filtering and buffering the output signal. The analogue design can be broken up into four key parts, as shown in Figure 2. The differential amplifier provides a current to voltage converter, converting the 20mA (p-p) differential current signal from the DAC to a single 4.5V (p-p) voltage signal. This is achieved using Texas Instruments THS3091, a 210MHz 7.3kV/µs current feedback Op-Amp. To maximize the bandwidth the differential amplifier has a fixed gain of only (V/V). Any noise inducted into the 20mA (p-p) signal between the DAC and the first analogue stage will be significantly reduced by From Human Interface THS3091 Differential Current to Voltage Converter From Digital Design Gain and Offset Control Switchable Low Pass Filter THS3091 Gain and Offset Controlled Amplifier BUF mA Output Buffer To Output Figure 2: The block diagram of the analogue design the common mode rejection ratio of the differential amplifier. The low pass filter provides filtering of quantisation noise caused by the DAC and also sampling noise/distortion caused by the PA sampling the waveform within the PAC. Currently, this is a basic passive RC filter which can be manually switched out. This switching will prove useful when producing waveforms such as square waves, where filtering limits the shape of the square wave by removing odd harmonics. At this stage in the project it has been decided to keep the filter design as simple as possible due to complexities elsewhere in the DDS waveform generator design. The next amplifier provides voltage control and DC offset control of the output waveform, using another THS3091. The DC offset, controlled through a potentiometer, can be adjusted between -5V DC and +5V DC. To maximize the bandwidth the inverting amplifier has a maximum gain of (V/V), but can be adjusted through a potentiometer down to approximately (V/V). This provides an output waveform with voltage fully adjustable from 5mV (p-p) to 10V (p-p). The final amplifier provides a buffered output of upto 250mA, using Burr-Brown s BUF634, a 180MHz 2.0kV/µs 250mA Op-Amp buffer. The BUF634 also provides current limiting, with a short circuit current of 400mA, and thermal shutdown; making it a very tough amplifier. Its TO-220 packing allows for the required heat sinking. Bandwidth is also maximized, with a unity gain of +1 (V/V). It is important to note that the overall gain of the analogue design is non-inverting; making the programming of waveforms into the microcontroller and phase to amplitude converter a lot simpler. 4.3 Software Design The software design has been developed in Atmel s ATmega128 8-bit RISC microcontroller, using the ATmega128 CPU module developed in house by CPIT [9]. The software is responsible for control of both the human interface and digital design. Communication between the microcontroller and FPGA is through the 8-bit Command Bus and 8-bit Data Bus. A driver has been developed allowing the microcontroller to control the PA and PAC through the Command Decoder. The lower level of this driver, responsible for communication between the two systems has been written in assembly language, and the higher level, responsible for determining the FCW, PCW and amplitude samples has been written in C language. Drivers for an LCD and keypad module have already been developed in CPIT s BCEN342: Computer

5 Engineering IIB, and will most likely be used for the human interface. 5. CURRENT PROGRESS Due to the design flexibility of VHDL and FPGAs, and the inclusion of the command decoder, the digital design has been synthesized four times within the FPGA. Thus the digital design now has four independent channels/outputs, each with wave shape, frequency, and phase independently controllable. To eliminate random phase/timing errors, associated with controlling multiple channels, a synchronize command has been incorporated into the command decoder. When used, this command resets the NCO latch within each PA at the same point in time. This causes each channel to jump back to the first waveform amplitude sample plus the set phase offset. This removes random phase/timing errors while maintaining set phase relationships between channels, as within the PA the phase shift is inserted after the NCO latch. At this stage in this project, the digital design has been fully implemented using VHDL within the Spartan-IIE FPGA, and found to be functioning as intended by means of Xilinx ISE computer simulation. Also the software driver to control the PA and PAC has been fully implemented for the ATmega128 microcontroller. The completed software has been downloaded into both the microcontroller and FPGA, and the two project boards connected together, as can be seen in Figure 3. To complete verification of both designs a LED module has been connected to the output of the PAC to simulate the waveform output from the FPGA. This test has successfully confirmed the operation of both designs, and minor tweaks have been made where required. Changing both waveform and frequency can be clearly seen on the LED model, although one s imagination must be stretched when looking the numeric output for waveforms such as a sine wave. ATmega128 CPU Module ATmega128 Microcontroller Project Board Spartan-IIE FPGA Project Board LED Output Module (for testing) Figure 3: Photo of testing the completed software and digital design 6. FUTURE IMPROVEMENTS 6.1 Gain and Offset Control There is currently concern about POTs being used for gain and voltage control. These POTs will be mounted to the front of the casing, with leads running back to their connections into the PCB. The concern is that these leads will induct a large amount of noise and crosstalk, greatly reducing the quality of the output signal. Current potential improvements include: Shielding using some form of shield along the POTs leads to minimize noise and crosstalk. Mechanical mounting the POTs to the PCB and using mechanical methods to extent the control to the user interface. Digital using digital method replace the POTs. This may be a digital attenuator for gain control and a small DAC for offset control. 6.2 Filter Design A better filter may be developed for the analogue design. This is not to only to remove quantisation noise, but to also to better reconstruct sinusoidal waveforms with little amplitude information, such as when the FCW is greater than the natural frequency. It is intended that a digitally controllable filter will be incorporated into the analogue design at a later stage in the project. The current concept is to switch capacitors in and out of a low pass RC filter by using an analogue switch IC. 7. FUTURE PROGRESS The project is currently on track to be completed by the due date, the end of October. Now that the digital section of the DDS waveform generator has been completed attention will be focused on the analogue section, as well as PCB design and human interface. The previously mentioned improvements require to be added to the analogue design; and several changes need to be made to the already developed PCB design, in terms of reducing crosstalk and other related problems. As for the optional extra design goal of arbitrary waveform generation, custom wave shapes can be stored in the E 2 PROM of the microcontroller and loaded into the PAC. The problem is developing a human interface which allows the user to easily program the waveform amplitude samples into the E 2 PROM. It was hoped that there would be extra time at the end of the project to develop such an interface; but this remains unlikely. 8. CONCLUSIONS The Direct Digital Synthesis Waveform Generator has be constructed using a 32-bit phase accumulator

6 and a 8-bit phase to amplitude converter, allowing it to produce standard and arbitrary waveforms defined as 256 instantaneous amplitude samples, frequency control ranging from 0.01Hz to 5.0MHz with a resolution of 0.01Hz, and phase control ranging between 360 with a resolution of Within the Spartan-IIE FPGA, four DDS waveform generators have been synthesized, each with independent wave shape, frequency, and phase control. Now the digital section of the DDS waveform generator has been completed attention will be focused on the analogue section, as well as PCB design and human interface. This will include adjustable output voltage ranging from 5mV (p-p) to 10V (p-p) and DC offset between 5V DC, as well as output filtering and buffering. 9. ACKNOWLEDGMENTS The student of this project would like to acknowledge the following CPIT staff for advice and guidance throughout the DDS waveform generator project: Rob Blair, the project supervisor, for overall guidance and analogue design, Tom Cronje, for PCB and analogue design, Caillyn Benbow, for VHDL and FPGA design, and Karl Dodds, for digital calculations and conceptual simulation. 10. REFERENCES [1] N. Kularatna, Modern Electronic Test and Measuring Instruments, London: The Institution of Electrical Engineering (1996). [2] Thurbly Thandar Instruments Ltd, TG1010 Programmable 10 MHz DDS Function Generator, Cambridgeshire: Thurbly Thandar Instruments Ltd (1994). [3] T. Cronjé, BDPR301: Design Project A & B: 2008 Project Topics List, Christchurch Polytechnic Institute of Technology, Christchurch, New Zealand (2008). [4] S. Yalamanchili, Introductory VHDL: from simulation to synthesis, New Jersey: Prentice Hall (2001). [5] Analog Devices, AD9850: CMOS, 125 MHz Complete DDS Synthesizer (datasheet), (June 2008). [6] H. P. Bakkum, Z. Wu, T. C. A. Molteno and J. L. Bahr, A Transmitter and Receiver Design Using FPGA, Proceedings of the Fourteenth Electronics New Zealand Conference (ENZCon 07), pp (2007). [7] Y. Zhang and P. Komisarczuk, Implementing a Simplified MAC using FPGA on WAG, Proceedings of the Fourteenth Electronics New Zealand Conference (ENZCon 07), pp (2007). [8] BurchED, (Sept 2008). [9] Y. Li and C. Benbow, An Educational AVR Microcontroller Training Kit, Proceedings of the Thirteenth Electronics New Zealand Conference (ENZCon 06), pp (2006).