Digital Power: Consider The Possibilities

Transcription

1 Power: Consider The Possibilities Joseph G Renauer Michael G. Amaro David Figoli Texas Instruments 1

2 The Promise of Power Accuracy and precision No drift Unit to unit uniformity Programmable performance parameters Voltage, current limit, temperature limits Sequencing parameters Enhanced monitoring capability communication - PMBus Fault management Reporting Reconfiguration Fault prediction 2

3 The Real World Solutions already exist Analog add-ons provide parametric adjustments µc assisted sequencing, monitoring, and communication They use proven technology Easy to design Moderate cost 3

4 The Quest Demonstrate that Power can do better Performance Flexibility Fault recovery Fault prediction Ease of use Lower overall system cost 4

5 The Power Concept Car Create a platform that allows software and hardware designers to explore the possibilities. Combine a high-performance DSP engine with a multiple power trains. Test Power concepts Efficiency optimization Non-linear control Fault detection Fault prediction Dynamic reconfiguration Demonstrate to customers Get user feedback 5

6 The Engine TMS320F MIPS Single cycle 32 x32-bit MAC 6 Enhanced PWMs Up to 150ps resolution Fast 12 bit ADC Very Fast Interrupt Response ezdsp Board from Spectrum Off-the-shelf Supports JTAG debug/monitoring Code security 64Kw Flash + Emulated EE XINTF 32-bit Timers (3) Real-Time JTAG 10Kw RAM Memory Bus Interrupt Management 100 MIPs C28x TM 32-bit DSP 32x32-bit Multiplier R M W Atomic ALU 32-bit Register File F2808 4Kw Boot ROM Peripheral Bus EPWM x 6 ECAP x 4 EQEP x 2 ADC (12b) GPIO SCI x 2 CAN x 2 SPI x 4 I2C 6

7 The Advantage of HiRes PWMs Buck regulator example: f CLK = 100 MHz f PWM = 1 MHz V IN = 8 V V OUT = 1.3 V HiRes PWM time steps 150 ps Regular PWM 10 ns steps No visible limit cycle Limit cycle issue 7

8 The Drive Train Vout1 8A Sync Buck Stage Vin1 PWM In1 CLF Top FET Bias Generator Vout2 8A Sync Buck Stage Vin1 PWM In2 CLF Bottom FET Bias Generator Vout3 8A Sync Buck Stage Vin1 PWM In3 CLF Interface Logic Vout4 8A Sync Buck Stage Vin1 PWM In4 CLF Stimulus DAC Vout5 8A Sync Buck Stage Vin2 PWM In5 Vout6 8A Sync Buck Stage CLF Vin2 PWM In6 ADC MUX CLF 8

9 Power Stage Diagram 8A Synchronous Buck Power Stage 5V - 12V VIN CLF Top Bias Bottom Bias Circuit Breaker Logic VDD PWM In UCD7230 Control Gate Driver VSW_NODE VOUT 8A max VRET VTEMP Diff Amp VFB 9

10 The Fusion Test Platform 10

11 Features Independent current limit flag Electronic circuit breaker Temperature sensing Differential remote sensing Precision voltage measurement Input voltage High-side Vdd Switching node Output voltage Independently adjustable FET drive supplies High-side Low-side 11

12 Configurations I VOUT 1 VIN 1 Triple output 4-phase multi-phase Two single phase Single Vin VOUT 2 VOUT 3 12

13 Configurations II VIN 2 VOUT 1 VIN 1 Triple output Two Vin rails 5V to 12V range Vin 1 to four stages Vin 2 to two stages VOUT 2 VOUT 3 13

14 Configurations III VIN 2 VOUT 1 VOUT 2 VOUT 3 VIN 1 Six output voltages Independent control loops Individual monitoring Adjustable interleaving Single or dual Vin capable VOUT 4 VOUT 5 VOUT 6 14

15 Possibilities Non-Linear loop control Adaptive loop control Efficiency optimization Adjusting FET gate drive voltages Dynamic synchronous rectification enable/disable Phase shedding at light load Fault prediction Temperature monitoring Efficiency degradation Fault tolerance Disable faulty power stages Dynamic reconfiguration 15

16 Fault Detection and Reconfiguration VIN 1 VOUT 1 Detect a faulty phase Disable it VOUT 2 VOUT 3 16

17 Fault Detection and Reconfiguration VIN 1 VOUT 1 Reconfigure remaining phases Do it on-the-fly VOUT 2 VOUT 3 17

18 Experiments Multi-Phase dynamic reconfiguration Detect and disable faulty phase Reconfigure remaining phases Maintain regulation Auto-calibration on power-up/soft start Determine Rds(on) of FETs Compensate for offsets and gain errors Learn amount of output capacitance present Efficiency optimization 18

19 Know Your Limits Is 100 MIPS enough? How many phases can you really handle? Can faults be detected fast enough? Is a 12 bit ADC sufficient? How much hardware assistance is required? Is it robust? 19

20 Roadmap Develop software to verify basic functionality Single phase Multi-phase Explore the possibilities Fault detection Fault recovery Fault prediction Performance optimization Demonstrate to key users Obtain feedback Refine the features Refine the hardware & software 20

21 Summary A Power test platform is here A development tool for: Software evaluation and refinement Hardware verification Proof of concepts Algorithm development Goals: Better understanding of limits Customer requirements Costs 21