PAPER A 12 b 200 ks/s 0.52 ma 0.47 mm 2 Algorithmic A/D Converter for MEMS Applications

Transcription

1 206 PAPER A 12 b 200 ks/s 0.52 ma 0.47 mm 2 Algorithmic A/D Converter for MEMS Applications Young-Ju KIM, Hee-Cheol CHOI, Members, Seung-Hoon LEE a), and Dongil Dan CHO, Nonmembers SUMMARY This work describes a 12 b 200 ks/s 0.52 ma 0.47 mm 2 ADC for sensor applications such as motor control, 3-phase power control, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with a recycling signal path to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels employs a folded-cascode amplifier to achieve a required DC gain and a high phase margin. A 3-D fully symmetric layout with critical signal lines shielded reduces the capacitor and device mismatch of the multiplying D/A converter while switched-bias power-reduction circuits minimize the power consumption of analog amplifiers. Current and voltage references are integrated on chip with optional off-chip voltage references for low glitch noise. The down-sampling clock signal selects the sampling rate of 200 ks/s and 10 ks/s with a further reduced power depending on applications. The prototype ADC in a 0.18 µm n-well 1P6M CMOS process demonstrates a maximum measured DNL and INL within 0.40 LSB and 1.97 LSB and shows a maximum SNDR and SFDR of 55 db and 70 db at all sampling frequencies up to 200 ks/s, respectively. The ADC occupies an active die area of 0.47 mm 2 and consumes 0.94 mw at 200 ks/sand 0.63 mw at 10 ks/s with a 1.8 V supply. key words: algorithmic, low power, MEMS, ADC, CMOS 1. Introduction Many analog integrated circuits are still used as a discrete component, while most digital integrated circuits based on various logic, memories, and micro-processors are implemented on a single chip. Recently large-scale mixedsignal system-on-a-chip (SoC) design techniques have been rapidly developed to integrate a lot of analog and digital circuits and functions on the same chip. Correspondingly high-performance A/D converters (ADCs) for such SoC applications as high-definition video systems, personal mobile communication equipment, high-speed digital networks, and medical devices have been in high demand. Particularly, low-power and small-size ADCs with a resolution exceeding 12 b and a sampling clock rate of several hundreds of ks/s are required for sensor applications such as motor control, 3-phase power control, and CMOS image sensors and communication system applications such as portable multimedia image processing, data acquisition systems, optical networks, and high-speed modems. A variety of circuit design and layout techniques need to be applied to the ADCs to achieve a low-power and small chip-size performance at a 12 b level. The conventional ADCs with a 12 b resolution and a sampling rate of ks/s to MS/s have commonly employed over-sampling architectures, successive approximation register (SAR) types, and algorithmic architectures [1] [9]. Although over-sampling ADCs can realize a high resolution, a relatively high over-sampling input clock is needed and the circuits are too complex to be integrated with digital circuits in a small die area for SoC applications. SAR type ADCs based on a relatively simple circuit architecture are difficult to be implemented in a small area simultaneously with high accuracy since the number of integrated capacitors are exponentially increased with a required resolution. On the other hand, algorithmic ADCs employ a simple architecture, occupy a small chip size, achieve a considerably high resolution, and dissipate a low power based on the small number of required capacitors. This work proposes a low-power algorithmic ADC repeatedly recycling one stage of the conventional pipeline architecture. Recently reported CMOS ADCs with a 12 b resolution and a sampling clock speed of several hundreds of ks/s to several MS/s are compared with the proposed ADC in Table 1 [1] [9]. Most of the ADCs in Table 1 are implemented without on-chip voltage references, occupying a chip area exceeding 1 mm 2 and dissipating a power of several mw to several tens of mw. If the ADCs are integrated with onchip voltage references, larger area and more power consumption than reported may be needed. The ADCs based on a two-stage (1.5 b/stage) algorithmic architecture [1], [9] show good integral non-linearities (INL), but those ADCs Table 1 Conventional 12 b ks/s toms/s CMOS ADCs. Manuscript received March 5, Manuscript revised August 19, The authors are with the Dept. of Electronic Engineering, Sogang University, Seoul , Korea. The author is with the School of Electrical Engineering and Computer Science, Seoul National University, Seoul , Korea. a) hoonlee@sogang.ac.kr DOI: /ietele/e91 c Copyright c 2008 The Institute of Electronics, Information and Communication Engineers

2 KIM et al.: A 12 B 200 KS/S 0.52 MA 0.47 MM 2 ALGORITHMIC A/D CONVERTER FOR MEMS APPLICATIONS 207 with extra calibration techniques show a high power dissipation and large chip area. Although an algorithmic ADC in Table 1 shows a properly optimized area and power consumption [4], the ADC has a high INL problem of 4 LSB. The over-sampling ADC with a chip area of 0.65 mm 2 in Table 1 shows a good performance [7] while the chip area does not include the required digital signal processing block and the ADC consumes 41 mw. The proposed ADC with on-chip voltage references is suitable for SoC applications based on a small chip size of 0.47 mm 2 and a low power consumption of 0.94 mw at 1.8 V. The proposed 12 b 200 ks/s 0.52 ma 0.47 mm µm CMOS ADC employs (1) an algorithmic architecture to optimize power consumption and chip area, (2) a switched-bias power-reduction technique to minimize the power consumption of the sample-and-hold amplifier (SHA) with eight input channels for efficient system interface, (3) a three-dimensional (3-D) fully symmetric capacitor layout for a high capacitor matching accuracy and a switched-bias power-reduction technique similar to the SHA in the multiplying D/A converter (MDAC), and (4) on-chip current and voltage (I/V) references with optional off-chip voltage references and a down-sampling clock (DNCK) signal for a minimum power consumption at a reduced sampling clock of 10 ks/s. 2. Proposed ADC Architecture As shown in Fig. 1, the proposed 12b 200kS/s algorithmic ADC consists of an input SHA, a 2 b MDAC, a 2 b flash ADC, digital correction logic (DCL), on-chip I/V references, and on-chip timing circuits. The non-overlapping clock phases and recycling control phases are internally generated from a single master input clock and the proposed ADC takes 11 master clock cycles to produce a 12 b binary output from an analog input sample. During the first cycle, only one analog input out of eight different inputs connected to eight independent channels is selected by the input MUX with 3 b channel selection pins. The very analog input is sampled on the SHA sampling capacitors for further signal processing. During the next 10 cycles, the SHA repeatedly samples recycled output signals from the MDAC. The flash ADC transmits 2 b digital data to the DCL during each cycle and nonlinear errors such as offsets and clock feed-through in the SHA, the MDAC, and the flash ADC are digitally corrected in the DCL [1], [10]. By using 11 clock cycles from a 2.2 MHz input system clock, the ADC operates at a 200 ks/s conversion rate. The supply- and temperature-insensitive I/V references generate accurate and stable internal currents and voltages and the on-chip timing generator is designed in a module form easily to expand the resolution if needed. 3. ADC Circuit Implementation 3.1 SHA Based on a Switched-Bias Power-Reduction Technique Amplifiers typically use most of the power dissipated in analog or mixed-signal integrated circuits and low-power amplifiers are very critical for low-power system applications. When an input signal is being sampled in the openloop manner during a half clock cycle, amplifiers can be fully or partially turned off to reduce the power consumption. The proposed SHA employs a switched-bias powerreduction technique, which fully cuts off bias currents during a half clock cycle of the open-loop sampling mode and resumes the bias currents in the pre-defined sequence during the next half clock cycle of the holding mode. The folded-cascode op amp and the bias circuit in the SHA using a switched-bias power-reduction technique are shown in Fig. 2. The SHA bias circuit is implemented independently to prevent the interference from other functional circuits. In the conventional power reduction techniques [11], [12], a part of bias currents are supplied to amplifiers during the sampling mode. However the proposed switched-bias power-reduction technique minimizes the power consumption by fully turning off the bias currents for BIAS1, BIAS2, and BIAS4 during the sampling mode as shown in Fig. 2. During the next holding mode, the bias currents of the op amp are resumed in the sequence of BIAS4 followed by BIAS1 and BIAS2 with the help of a current delay cell composed of MN3 and MP3. Although the resumed sequence Fig. 1 Proposed 12 b 200 ks/s algorithmic ADC. Fig. 2 SHA based on a switched-bias power-reduction technique.

3 208 Fig. 3 MDAC based on a switched-bias power-reduction technique. Fig. 4 Proposed 3-D fully symmetric MDAC capacitors for high matching accuracy. may affect the signal settling performance in the holding or amplifying mode, the increased pole-splitting effect between non-dominant pole and unit-gain frequencies due to the proposed sequential biasing improves a phase margin for better signal processing in the next stage MDAC [11]. It is noted the MDAC common-mode voltage can change a little during mode transition, but returns quickly in the original fixed bias voltage. Consequently, the SHA consumes less power by 30% than that without the proposed powerreduction technique while the DC gain and the phase margin of the proposed SHA are 72.7 db and 88.7 at a 200 khz sampling clock, respectively. The proposed SHA has 8 input channels and a 3 b decoder circuit to select a specific input channel for this MEMS application which needs to handle consecutive input signals. The SHA based on a single-stage amplifier employs the conventional two-capacitor flip-around architecture to minimize the power consumption and chip area at a 12 b accuracy and a 200 khz sampling rate. The sampling capacitor of the SHA is designed to be 1 pf considering the 12 b-level thermal noise and accuracy of 1 Vp-p input signals. 3.2 Low-Power MDAC Based on a 3-D Fully Symmetric Capacitor Layout The MDAC is one of the most critical parts in the proposed ADC and employs a two-stage amplifier with foldedand unfolded-cascode architectures based on a switchedbias power-reduction technique similar to the SHA, as illustrated in Fig. 3. The sequence turning off and resuming the bias currents is the same as the SHA and the MDAC consumes less power by 40% including the bias circuit than that without the proposed power-reduction technique. The MDAC capacitor mismatch is very critical to the differential non-linearity (DNL) and integral non-linearity (INL) performance of the ADC. The capacitor mismatch comes from two sources. One is the random error, which is caused primarily by process variations including inappropriate etching and random oxide thickness. The other is the systematic error from parasitic capacitances between capacitors and neighboring signal metal lines. A variety of analog- and digital-domain calibration techniques have been widely invented to overcome the capacitor mismatch errors of high-resolution ADCs [1], [9], [13] [19]. However, the complicated calibration techniques tend to increase the ADC chip area and power consumption. As a consequence, it may not be appropriate for large-scale embedded system applications requiring a small chip area and a lowpower dissipation. The effect of the capacitor mismatch can be reduced by a careful layout technique. The proposed 3-D fully symmetric capacitor layout technique for high matching accuracy is shown in Fig. 4. In Fig. 4, all symmetric unit capacitors are enclosed by all other interconnection metals except the metals for routing the top and bottom plates of capacitors, while both of the unit capacitors and bottom plate signal lines are enclosed by all the employed metal lines in the conventional layout technique [20]. Although the conventional layout technique makes capacitors surrounded physically in the same environment, some signal lines pass through neighboring capacitors and unit capacitors may have functionally different parasitic capacitances each other. On the other hand, the proposed layout technique minimizes the capacitor mismatch physically and functionally by isolating unit capacitors from all the neighboring signal lines. The unit capacitors in the MDAC are designed to be 250 ff considering the kt/c noise, power consumption, and 12 b matching. 3.3 On-Chip CMOS Current and Voltage References A lot of commercially available ADC products still employ off-chip reference voltages, even though on-chip I/V references are in high demand for low-power SoC applications. Moreover, the ADCs operating at a several hundreds of ks/s rarely employ on-chip I/V referencesto minimize the power consumption. The proposed ADC employs on-chip lowpower I/V references for versatile SoC applications. As shown in Fig. 5, the current reference block (IREF) generates internal reference currents and voltages insensitive to supply voltage and temperature variations. The current mismatch within 40% can be calibrated in the digital domain by 3 b IVCN control pins [21]. The power dissipation of the prototype ADC is reduced to a 1 µw level when the power-

4 KIM et al.: A 12 B 200 KS/S 0.52 MA 0.47 MM 2 ALGORITHMIC A/D CONVERTER FOR MEMS APPLICATIONS 209 Fig. 5 mode. On-chip current and voltage references with a low-power DNCK Fig. 6 Die photograph of the prototype 12 b 200 ks/s algorithmic ADC (0.60 mm 0.78 mm). off control (POFF) signal is set to high for portable applications. The external reference (EXTRF) decides to use either on-chip or off-chip reference voltages. Recently, MOS transistors in the weak inversion region rather than the strong inversion region have become one of the important research and development issues for ultra lowpower systems [22] [25]. The proposed ADC is designed to operate in both strong and weak inversion regions to optimize the power consumption with a DNCK signal enabled. The DNCK signal controls the currents of the SHA and the MDAC. With the DNCK low, the ADC operates at a nominal 200kS/s mode in the strong inversion region. On the other hand, with the DNCK high, the ADC operates at a low-power 10 ks/s DNCK mode in the weak inversion region. Although the conventional ADCs tend to use internal or external bypass capacitors at the output nodes of voltage references to reduce switching noise, the proposed reference circuit reduces the noise without any internal and external bypass capacitors. 4. Prototype ADC Measurements Fig. 7 Measured DNL and INL of the prototype ADC. The prototype 12 b 200 ks/s algorithmic ADC is implemented in a 0.18 µm n-well 1P6M CMOS process as shown in Fig. 6. The proposed ADC only employs the limited number of external pins such as inputs, outputs, and power supplies for the use as a core IP block of various mixed-signal integrated systems. The ADC occupies an active die area of 0.47 mm 2 (0.60 mm 0.78 mm). The blocks indicated by bold lines represent on-chip PMOS decoupling capacitors. The prototype ADC nominally works at a power supply from 1.6 V to 2.0 V. With the DNCK low, the ADC operates at a nominal 200 ks/s mode and dissipates 0.94 mw at 1.8 V. The ADC with the DNCK high operates at a low-power 10 ks/s DNCK mode and dissipates a power of 0.63 mw at 1.8 V. The measured maximum DNL and INL of the prototype ADC are 0.40 LSB and 1.97 LSB, respectively, as illustrated in Fig. 7. Figure 8(a) and Fig. 8(b) illustrate the typical signal spectrum measured with a 10 khz input sine wave at a nominal 200 ks/s mode and with a 1 khz input sine wave at a Fig. 8 Signal spectrum measured with analog inputs and sampling clocks at (a) a nominal 200 ks/s mode and (b) a low-power 10 ks/s DNCK mode. low-power 10 ks/s DNCK mode, respectively. The signal-to-noise-and-distortion-ratio (SNDR) and the spurious-free dynamic-range (SFDR) in Fig. 9(a) are measured at different sampling rates up to 200 ks/s with a 10 khz input. With the sampling rates increased to 200 ks/s, the SNDR and the SFDR are maintained above 55 db and 70 db, respectively. The SNDR and the SFDR in Fig. 9(b) are measured with increased input frequencies at a sampling rate of 200 ks/s. With input frequencies increased to 100 khz, the SNDR and the SFDR are maintained over

5 210 Table 2 Measured performance of the prototype ADC. 5. Conclusion Fig. 9 Measured dynamic performance of the prototype ADC at a nominal 200 ks/s mode: SFDR and SNDR versus (a) fs and (b) fin. Fig. 10 Measured dynamic performance of the prototype ADC at a lowpower 10 ks/s DNCK mode : SFDR and SNDR versus (a) fs and (b) fin. 55 db and 68 db, respectively. The prototype ADC is also evaluated at a low-power DNCK mode of 10 ks/s. The SNDR and the SFDR in Fig. 10(a) are measured at different sampling rates up to 10 ks/s with a 1 khz input. With the sampling rates increased to the 10 ks/s, the SNDR and the SFDR are maintained above 55 db and 70 db, respectively. The SNDR and the SFDR in Fig. 10(b) are measured with increased input frequencies at a sampling rate of 10 ks/s. With the input frequencies increased to the 5 khz, the SNDR and the SFDR are maintained over 55 db and 70 db, respectively. The measured performance of the proposed prototype ADC is summarized in Table 2. This work describes a 12 b 200 ks/s 0.52mA 0.47mm 2 algorithmic ADC for sensor and communication system applications such as motor control, 3-phase power control, optical networks, and high speed modems simultaneously requiring ultra low-power and small chip area. The following circuit design techniques are considered to obtain the required target performance. First, the proposed ADC employs the conventional algorithmic architecture which consists of a SHA, an MDAC, and a flash ADC to optimize resolution and power consumption. Second, the input SHA has 8 input channels for diverse system applications and a simple decoder to select each input channel. Third, the proposed MDAC employs 3-D fully symmetric layout techniques for high capacitor matching accuracy by isolating unit capacitors physically and functionally from all neighboring signal lines. Fourth, the switched-bias power-reduction technique in the SHA and the MDAC reduces the power dissipation properly by switching bias currents during the sampling and holding phases. Fifth, the proposed ADC integrates on-chip lowpower I/V references with optional off-chip voltage references and a DNCK signal for minimizing the power consumption at 10 ks/s in the weak inversion region. On-chip PMOS decoupling capacitors suppress the coupling noise and EMI problems of the ADC. The prototype ADC in a 0.18 µm n-well1p6mcmos technology demonstrates the measured maximum DNL and INL of 0.40 LSB and 1.97 LSB, respectively. The ADC shows the maximum SNDR and SFDR of 55 db and 70 db at all sampling frequencies up to 200 ks/s, respectively. The active die area is 0.47 mm 2 and the chip consumes 0.94 mw at a nominal 200 ks/s mode and 0.63 mw at a low-power 10 ks/s DNCK mode at a 1.8 V supply. Acknowledgement This work was partly supported by the Nano IP/SoC Promotion Group of Seoul R&BD Program 2007 and the IDEC of KAIST.

6 KIM et al.: A 12 B 200 KS/S 0.52 MA 0.47 MM 2 ALGORITHMIC A/D CONVERTER FOR MEMS APPLICATIONS 211 References [1] H.S. Lee, A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC, IEEE J. Solid-State Circuits, vol.29, no.4, pp , April [2] J.S. Wang and C.L. Wey, A 12-bit 100-ns/bit 1.9-mW CMOS switched-current cyclic A/D converter, IEEE Trans. Circuits Syst. II, vol.46, no.5, pp , May [3] K. Satou, R. Tsuji, M. Sahoda, H. Otsuka, K. Mori, and T. Iida, A 12 bit 1 MHz ACD with 1 mw power consumption, Proc. IEEE CICC, pp , May [4] M. Furuta, S. Kawahito, T. Inoue, and Y. Nishikawa, A cyclic A/D converter with pixel noise and column-wise offset cancellation for CMOS image sensors, 7H1, Proc. European Solid-State Circuits Conf., pp , Sept [5] G. Promitzer, 12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s, IEEE J. Solid-State Circuits, vol.36, no.7, pp , July [6] L. Cong and W.C. Black, A new charge redistribution D/A and A/D converter technique pseudo C-2C ladder, IEEE Midwest Symposium, vol.1, pp , Aug [7] J. Doyle, K. Gallagher, and C. Lyden, A low power 12-bit ADC for systems applications, IEE Colloquium, pp.17/1 17/4, Sept [8] B.P. Brandt and B.A. Wooley, A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion, IEEE J. Solid-State Circuits, vol.26, no.12, pp , Dec [9] J. Li, G.C. Ahn, D.Y. Chang, and U.K. Moon, A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR, IEEE J. Solid-State Circuits, vol.40, no.4, pp , April [10] C. Mangelsdorf, S.H. Lee, M. Martin, H. Malik, T. Fukuda, and H. Matsumoto, Design for testability in digitally-corrected ADC s, ISSCC Dig. Tech. Papers, pp.70 71, Feb [11] D.Y. Chang and S.H. Lee, Design techniques for a low-power lowcost CMOS A/D converter, IEEE J. Solid-State Circuits, vol.33, no.8, pp , Aug [12] B.L. Jeon and S.H. Lee, A 10 b 50 MHz 320 MW CMOS A/D converter for video applications, Trans. Consumer Electronics, vol.45, no.1, pp , Feb [13] S.T. Ryu, S. Ray, B.S. Song, G.H. Cho, and K. Bacrania, A 14 b- linear capacitor self-trimming pipelined ADC, ISSCC Dig. Tech. Papers, pp , Feb [14] S.Y. Chuang and T.L. Sculley, A digitally self-calibrating 14-bit 10- MHz CMOS pipelined A/D converter, IEEE J. Solid-State Circuits, vol.37, no.6, pp , June [15] J. Guilherme, P. Figueiredo, P. Azevedo, G. Minderico, A. Leal, J. Vital, and J. Franca, A pipeline 15-b 10-Msample/s analog-todigital converter for ADSL applications, IEEE International Symposium on Circuits and Systems, pp , May [16] H.C. Liu, Z.M. Lee, and J.T. Wu, A 15 b 20 MS/s CMOS pipelined ADC with digital background calibration, ISSCC Dig. Tech. Papers, pp , Feb [17] E. Siragusa and I. Galton, A digitally enhanced 1.8 V 15 b 40 MS/s CMOS pipelined ADC, ISSCC Dig. Tech. Papers, pp , Feb [18] H.C. Liu, Z.M. Lee, and J.T. Wu, A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration, IEEE J. Solid-State Circuits, vol.40, no.5, pp , May [19] S. Hisano and S.E. Sapp, A 16-bit, 20 MSPS CMOS pipeline ADC with direct INL detection algorithm, Proc. IEEE CICC, pp , Sept [20] H.C. Choi, S.B. You, H.Y. Lee, H.J. Park, and J.W. Kim, A calibration-free 3 V 16 b 500 ks/s6mw0.5mm 2 ADC with 0.13 µm CMOS, Symp. VLSI Circuits Dig. Tech. Papers, pp.76 77, June [21] Y.J. Cho and S.H. Lee, An 11 b 70-MHz 1.2-mm 2 49-mW 0.18-µm CMOS ADC with on-chip current/voltage references, IEEE Trans. Circuits Syst. I, vol.52, no.10, pp , Oct [22] D.J. Comer and D.T. Comer, Using the weak inversion region to optimize input stage design of CMOS op amp, IEEE Trans. Circuits Syst. II, vol.51, no.1, pp.8 14, Jan [23] C. Popa and D. Coada, A new linearization technique for a CMOS differential amplifier using bulk-driven weak inversion MOS transistors, Symp. Signals Circuits and Systems, vol.2, no.1, pp , July [24] E. Seevinck, E.A. Vittoz, M. du Plessis, T. Joubert, and W. Beetge, CMOS translinear circuits for minimum supply voltage, IEEE Trans. Circuits Syst. II, vol.47, no.12, pp , Dec [25] C.C. Enz and E.A. Vittoz, CMOS low-power analog circuit design, IEEE International Symposium on Circuits and Systems, Chapter 1.2 of Tutorials, pp , May Young-Ju Kim received the B.S. and M.S. degrees in Electronic Engineering from Sogang University, Seoul, Korea, in 2005 and 2007, where he is currently pursuing the Ph.D. degree. His current interests are in the design of high-resolution low-power CMOS data converters and very high-speed mixed-mode integrated systems. Hee-Cheol Choi was born in Seoul, Korea. He received the B.S. and M.S. degrees in Electronic Engineering from Sogang University, Seoul, Korea, in 1994 and From 1996 to 2006, He worked as a senior engineer at Samsung Electronics. He has been in the Ph.D. program at Sogang University since His research interests are high-resolution low-power CMOS data converters and analog front ends for video signal processing. Seung-Hoon Lee received the B.S. and M.S. degrees with honors in Electronics Engineering from Seoul National University, Seoul, Korea, in 1984 and in 1986, respectively, and the Ph.D. degree in Electrical and Computer Engineering from the University of Illinois, Urbana- Champaign, in From 1990 to 1993, he was with Analog Devices Semiconductor, Wilmington, MA, as a Senior Design Engineer. Since 1993, he has been with the Department of Electronic Engineering, Sogang University, Seoul, Korea, where he is now a Professor. He has published hundreds of international and domestic journal and conference papers, IPs, books, technical reports, and patents, while he has been serving as the editor of the IEEK Journal of Semiconductor Devices, Circuits, and Systems and a TPC member of many international and domestic conferences including the IEEE Symposium on VLSI Circuits. His current interest is in the design and testing of high-resolution high-speed CMOS data converters, CMOS communication circuits, integrated sensors, and mixed- mode integrated systems.

7 212 Dongil Dan Cho received the BSME degree from Carnegie-Mellon University, Pittsburgh, PA, in 1980, and the M.S. degree and Ph.D. degrees from Massachusetts Institute of Technology, Cambridge, in 1984 and 1987, respectively. From 1987 to 1993, he was assistant professor in the Mechanical and Aerospace Engineering Department, Princeton University, Princeton, NJ. In 1993, he joined the Department of Control and Instrumentation Engineering, Seoul National University, Seoul, South Korea, where he is currently professor in the School of Electrical Engineering and Computer Science. He was the director of Microsystem Technology Center for , President of Korean MEMS Research Association for His research interests include silicon micro and nano processes, silicon micro inertial sensors, bio MEMS and RF MEMS. From 1992 to 1997, he was Editor for the IEEE/ASME Journal of MEMS and Associate Editor for the IOP Journal of Micromechanics and Microengineering. He also served as Acting Associate Editor for the ASME Transactions Journal of Dynamic Systems, Measurement, and Control in He is an Associate Editor for VSP Journal of Micromechatronics since 1999, Editor for the IEEE/ASME Journal of MEMS since 2000, Editorial board member for Sensors and Materials since 2003, and International Editorial Board for International Journal of Advanced Robotics since 2003.