A Low-Ripple Poly-Si TFT Charge Pump for Driver-Integrated LCD Panel

Transcription

1 606 EEE Transactions on Consumer Electronics, ol. 51, No. 2, MAY 2005 A Low-Ripple Poly-Si TFT Charge Pump for Driver-ntegrated LCD Panel Changsik Yoo, Member, EEE and Kyun-Lyeol Lee Abstract A low-ripple charge pump for voltage upconversion is described which was implemented in a poly-si thin-film-transistor (TFT) technology for driver-integrated liquid-crystal-display (LCD) panels. The ripple voltage of the charge pump is reduced by employing a multi-phase clocking method. The charge pump was implemented in a poly-si TFT technology. For output current of 100µA, filtering capacitor of 100pF and pumping clock frequency of 1MHz, the measured ripple voltage of the proposed charge pump is 135m while that of conventional Dickson charge pump is 590m. The measured pumping efficiencies of the Dickson and proposed 4-phase clocking charge pump are 59% and 65%, respectively. 1. ndex Terms Charge pump, oltage up-conversion, Dickson, Multi-phase clocking, Poly-Si TFT, LCD. NTRODUCTON Due to the much higher performance of poly-si TFT than amorphous-si (a-si) TFT, poly-si TFT has a great chance to integrate driver circuits on the same glass substrate as pixel array. The ultimate goal of poly-si TFT LCD might be a system-on-glass (SoG) where all the display electronics are on the same glass substrate as pixel array as shown in Fig. 1 [1-2]. Recently, several research results towards SoG have been announced [2-5]. Analog circuits such as data line driver, however, either show poor performance or have been found to require complicated circuits to have acceptable performance because of the poor matching and large variation in the characteristics of poly-si TFTs [1]. On the other hand, gate driver in poly-si TFT shows reasonably good performance. Therefore, it is thought that poly-si TFT LCD panel with integrated gate driver on the same panel is a reasonable halfway from display system with a number of external driver chips to SoG. n order to supply higher voltage than external supply to the integrated gate driver, it is desirable to implement a voltage up-conversion circuit on the same glass substrate with poly-si TFT. Charge pump is the most widely used circuit to boost the internal supply voltage while the DC level of the output voltage is stabilized by a feedback scheme as shown in Fig. 2. The voltage level of the charge pump output, however, has finite ripple due to the charge pumping. The magnitude of this Fig. 1. Conceptual block diagram of system-on-glass. ripple is of course desired to be as small as possible. Usually, the ripple on the output voltage can be reduced by either a low-pass filtering capacitor or high pumping frequency because the ripple voltage has the following relationship ; RPPLE f With poly-si TFT, the pumping frequency cannot be increased higher than several MHz because of the much lower mobility than that of single-crystal transistors [1]. Therefore, a larger low-pass filtering capacitor is the only viable solution to reduce ripple voltage which results in larger area. However, for driver-integrated LCD panel, the area consumed by integrated driver circuitry should be kept minimum to have cost competitiveness and high yield. n this paper, a poly-si TFT voltage up-conversion charge pump is described whose output has small ripple by employing a newly proposed multi-phase clocking method. Thus, the lowpass filtering capacitor can be smaller than in a conventional charge pump circuit and the panel area of integrated driver in poly-si TFT LCD panel can be kept small. n Section, the proposed multi-phase clocking poly-si TFT charge pump is described and the measured result of the charge pump is given in Section. Finally, Section gives a summary and conclusion of this paper. (1) This work was supported in part by the grant M1-02-KR K from nformation Display R&D Center, the 21st Century Frontier R&D Program funded by the Ministry of Science and Technology of Korea. Changsik Yoo is with Department of Electronics and Computer Eng., Hanyang University, Seoul, Korea ( csyoo@hanyang.ac.kr). Kyun-Lyeol Lee is with Department of Electronics and Computer Eng., Hanyang University, Seoul, Korea. Contributed Paper Manuscript received November 15, /05/$ EEE. LOW-RPPLE POLY-S TFT CHARGE PUMP WTH MULT-PHASE CLOCKNG A. Conventional charge pump The Dickson charge pump circuit in Fig. 2 has been widely used for voltage up-conversion. Since the filtering capacitor is

2 C. Yoo and K.-L. Lee: A Low-Ripple Poly-Si TFT Charge Pump for Driver-ntegrated LCD Panel Fig. 2. Conventional Dickson charge pump and its timing. 3 4 Fig. 4. Proposed charge pump with 4-phase clocking. Fig. 3. Cross-coupled charge pump and its timing. charged every clock cycle while is high, the ripple on the output voltage depends on the clock frequency. f all parasitic capacitances are ignored, ripple voltage is expressed as ; RPPLE = f The pumping efficiency of the Dickson charge pump is reduced by threshold voltage drop of the NTFT devices and the reverse charge sharing. For higher efficiency, crosscoupled structure shown in Fig. 3 has been proposed where the problem of threshold voltage drop is greatly mitigated. Another advantage of the cross-coupled charge pump is halved ripple on the output voltage because the output capacitor is charged twice per clock cycle and thus the ripple voltage is given as ; (2) = RPPLE 2 f (3) From this, we can see the ripple of the output voltage can be decreased if the output capacitor is charged more frequently for a given clock frequency. This is the basic concept of the multi-phase clocking charge pump. B. Multi-phase clocking poly-si TFT charge pump By adding one and two more stages to the conventional cross-coupled charge pump in Fig. 3, 4-phase and 6-phase clocking charge pump can be implemented as shown in Fig. 4 and Fig. 5, respectively. f more stages with different clock phases are added to the last stage for the same output voltage, the voltage ripple on the output can be further reduced. f all Fig. 5. Proposed charge pump with 6-phase clocking. parasitic capacitances are ignored, the ripple on the output voltage is expressed as ; RPPLE = N f where N is the number of clock phases. With the 4-phase clocking shown in Fig. 4, the output capacitor is charged 4 times per clock cycle and thus the ripple of the output voltage will be half and 1/4 of the cross-coupled charge pump and Dickson charge pump, respectively. Therefore, by applying this multi-phase clocking method, the ripple voltage can be greatly reduced without increasing neither clock frequency nor filtering capacitor, which are required feature for cost effective implementation of a driverintegrated LCD panel. Although the number of stages is increased in multi-phase clocking, the area of DC-DC converter does not increase because pumping capacitor is usually much smaller than filtering capacitor.. EXPERMENTAL RESULTS n order to verify the usefulness of the proposed multi-phase clocking charge pump, test chip was fabricated using a poly-si TFT process. For comparison, Dickson and cross-coupled charge pump were implemented on the same die as a 4-phase (4)

3 608 EEE Transactions on Consumer Electronics, ol. 51, No. 2, MAY um 590m 1170um (a) um 215m 1190um (b) um 135m 1690um (c) Fig. 6. Microphotograph and measured waveforms of (a) Dickson charge pump, (b) cross-coupled charge pump, and (c) proposed 4-phase clocking charge pump clocking charge pump. The load current is 100µA which is the sufficient to supply an integrated gate driver for PDA. The frequency of pumping clock is 1MHz while the filtering capacitance is 100pF. The microphotograph and measured waveforms are shown in Fig. 6 for each type of charge pump circuit. As indicated in the figure, the ripple of the output voltage gets reduced as more clock phases are used. f we compare the proposed 4-

4 C. Yoo and K.-L. Lee: A Low-Ripple Poly-Si TFT Charge Pump for Driver-ntegrated LCD Panel 609 TABLE PERFORMANCE COMPARSON (LOAD CURRENT = 100UA, FLTERNG CAPACTANCE = 100PF, PUMPNG FREQUENCY = 1MHZ) Type Output voltage [] Magnitude of ripple [m] Efficiency [%] Simulation Dickson Measurement Cross-coupled 4-phase clcoking Simulation Measurement Simulation Measurement phase clocking Simulation Delay Circuit Charge pumping circuit Delay Circuit phase clocking charge pump with the conventional Dickson charge pump, the ripple of the 4-phase clocking charge pump is about 1/4 of the Dickson charge pump. The magnitude of the ripple is different from the value predicted by the equations (2)-(4) because of the various parasitic capacitance. Of course, the ripple would be smallest for 6-phase clocking charge pump but it could not be implemented due to the limitation of allowed area in a test chip. The absolute level of the output voltage does not contain much meaning because it will be regulated to the desired value with some kind of feedback scheme in a practical DC-DC converter as illustrated in Fig. 7. ref Buffer Out Comparator Osillator Fig. 7. DC-DC converter composed of a charge pump and feedback network to regulate the level of output voltage. Ripple oltage m Dickson 2-phase 4-phase 6-phase Output Capacitor pf Fig. 8. Filtering capacitor vs. the ripple of the output voltage The occupied area is largest for 4-phase clocking charge pump because it has more stages than Dickson and crosscoupled charge pump while all three charge pumps were implemented with the same size of filtering capacitor. f the filtering capacitance was scaled to have same magnitude of ripple voltage, the area would be largest for Dickson charge pump. n order to see the effect of multi-phase clocking, the magnitude of the ripple of output voltage was simulated for several values of filtering capacitor, whose result is given in Fig. 8. For 50m ripple of the output voltage, the required value of filtering capacitor is 1nF, 575pF, 290pF, and 157pF for Dickson, cross-coupled, 4-phase clocking, and 6-phase clocking charge pump, respectively. The pumping efficiency is also compared for each type of charge pump and the result is summarized in Table with other performance parameters. The pumping efficiency of the proposed multi-phase clocking charge pump is almost the same as that of cross-coupled charge pump and larger than Dickson charge pump. This is because both the cross-coupled and multi-phase clocking charge pump remove the efficiency degradation problem due to the threshold voltage drop which is critical in Dickson charge pump.. CONCLUSON A low-ripple charge pump for voltage up-conversion is described which was implemented in a poly-si TFT technology for driver-integrated LCD panels. The ripple voltage of the charge pump is reduced by employing a multiphase clocking method. The charge pump was implemented in a poly-si TFT technology. For output current of 100µA, filtering capacitor of 100pF and pumping clock frequency of 1MHz, the measured ripple voltage of the proposed charge pump is 135m while that of conventional Dickson charge pump is 590m. The measured pumping efficiencies of the Dickson and proposed 4-phase clocking charge pump are 59% and 65%, respectively. ACKNOWLEDGMENT The authors would like to thank Samsung SD for the chip fabrication. The CAD tools were supported by DEC.

5 610 REFERENCES [1] D.-J. Kim, K.-L. Lee, and C. Yoo, Required characteristics of poly-si TFTs for analog circuits of system-on-glass, J. nformation Display, to be published. [2] B.-D. Choi, H. Jang, O.-K. Kwon, H.-G. Kim, M.-J. Soh, Design of poly-si TFT-LCD panel with integrated driver circuits for an HDT/XGA projection system, EEE Trans. Consumer Electronics, ol. 46, No. 1, pp , Feb [3] Y. Nonaka, H. Tsushi, H. Haga, H. Asada, H. Hayama, N. Takada, K. Sera, A DC-DC converter circuit integrated into a poly-si TFT LCD containing a 6-bit DAC, Dig. Tech. Papers, SD nternational Symposium, pp , [4] C. W. Kim, et al., Recent trend of low temperature poly silicon technologies in TFT-LCD, Dig. Tech. Papers, nt. Meeting on nformation Display, pp , [5] K. Yeneda, et al., Future Application Potential of Low Temperature p- Si TFT LCD Displays, Dig. Tech. Papers, SD nternational Symposium, pp , [6] John F. Dickson, et al., On-Chip High-oltage Generation in MNOS ntegrated Circuits Using an mproved oltage Multiplier Technique, EEE Journal of solid-state circuits, OL. SC-11, NO.3, June [7] Pierre Favrat, et al., A High-Efficiency CMOS oltage Doubler, EEE Journal of Solid-State Circuits, OL. 33, No.3, March EEE Transactions on Consumer Electronics, ol. 51, No. 2, MAY 2005 Changsik Yoo (S 92-M 00) was born in Daejon, Korea, on December 15, He received the B.S. (with the highest honor), M.S., and Ph.D. degrees from Seoul National University, Seoul, Korea, in 1992, 1994, and 1998, respectively, all in electronics engineering. After receiving the Ph.D. degree, he worked at Samsung Electronics for five months, developing a delay locked loop for DDR SDRAM. From 1998 to 1999, he was with ntegrated Systems Laboratory (S), Swiss Federal nstitute of Technology (ETH), Zurich, Switzerland, as a Member of Research Staff working on CMOS RF circuits. From 1999 to 2002, he was with Samsung Electronics, Hwasung, Korea working on high speed interface circuit design and next generation DRAM. Since 2002, he has been an assistant professor of Hanyang University, Seoul, Korea. He received a silver prize of the C design contest held by LG Semicon (now Hynix Semiconductor) in 1996, a bronze prize of mathematics contest held by POSTECH in 1987, and a golden prize for research achievement in next generation DRAM design from Samsung Electronics in His main research interests include CMOS RF transceiver design, mixed mode CMOS circuit design, and high speed interface circuit design. Kyun-Lyeol Lee received the B.S. degree from Dong-A University Pusan, Korea, in 2002 in electronics engineering and has been with Hanyang University, Seoul, Korea, pursuing M. S. degree since He is now receiving full scholarship from LG Electronics and going to join the same company in His main research interests are driver circuits for flat panel display system such as TFT LCD.