A Common-Gate Switched 0.9-W Class-E Power Amplifier with 41% PAE in 0.25-m CMOS

Transcription

1 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 5, MAY A Common-Gate Switched 0.9-W Class-E Power Amplifier with 41% PAE in 0.25-m CMOS Changsik Yoo, Member, IEEE, and Qiuting Huang, Senior Member, IEEE Abstract A power amplifier for wireless applications has been implemented in a standard m CMOS technology. The power amplifier employs class-e topology to exploit its soft-switching property for high efficiency. The finite dc-feed inductance in the class-e load network allows the load resistance to be larger for the same output power and supply voltage than that for an RF choke. The common-gate switching scheme increases the maximum allowable supply voltage by almost twice from the value for a simple switching scheme. By employing these design techniques, the power amplifier can deliver 0.9-W output power to 50- load at 900 MHz with 41% power-added efficiency (PAE) from a 1.8-V supply without stressing the active devices. Index Terms Class-E, CMOS, common-gate switching, power amplifier, wireless communication. I. INTRODUCTION PROGRESS in the last five years has shown that CMOS, traditionally confined to the digital and baseband part of radio transceiver, is also a competitive technology for RF front-end. At the research level, the CMOS RF transceiver is already expanding its application area to radio systems with stringent requirements such as cellular telephony, as shown in Table I [1] [5]. For compact low-cost and low-power portable radio devices, the prospect of a single-chip CMOS radio has been arousing considerable interest, even though it remains to be researched whether it is either feasible or advantageous to put the RF front-end on the same die as the rest of the mobile terminal. Even the less ambitious objective of implementing the mobile terminal in a set of separate chips in the same CMOS technology may bring considerable economic benefits, however, as it enables a company to rationalize the number of different technologies that have to be maintained for a given product. In this spirit, the feasibility of realizing efficient power amplifiers in regular CMOS technology is also beginning to receive increased attention. Power consumption considerations dictated by standby time require that the RF receiver front-end for wireless applications be realized in a deep-submicron CMOS technology [6], and recent studies have shown that a m CMOS GSM receiver is capable of 20-mA performance [5]. Therefore, for a CMOS power amplifier to be Manuscript received August 1, 2000; revised December 1, C. Yoo was with Integrated Systems Laboratory (IIS), Swiss Federal Institute of Technology (ETH), CH-8092 Zurich, Switzerland. He is now with Samsung Electronics, Kiheung, Kyong-Ki-Do, Korea ( csyoo@sec.samsung.com). Q. Huang is with Integrated Systems Laboratory (IIS), Swiss Federal Institute of Technology (ETH), CH-8092 Zurich, Switzerland ( huang@iis.ee.ethz.ch). Publisher Item Identifier S (01) compatible with the objective of either a single-chip radio or a chip set in the same technology, it is important that it also be realized in the same deep-submicron CMOS technology. Recent papers have reported 1-W power amplifiers with higher than 40% power added efficiency (PAE) using 0.8- and m CMOS technology, respectively [7], [8]. In [7], the power amplifier implemented in 0.8- m CMOS technology used a 1.0- m-long nmos transistor as a power device instead of a minimum channel length device to make the power transistor more robust to the voltage stress. Although the relatively high breakdown voltages of 0.8- m CMOS technology are desirable for the power amplifier, the power consumption of the receiver RF front-end and baseband circuits tends to be large if implemented in the same technology. Thus, the power amplifier in 0.8- m CMOS is not suitable for the goal of either a single-chip CMOS radio or a chip set in the same CMOS technology. For the full-scale integration in the future, the efficiency of a deep-submicron CMOS power amplifier was maintained by combining positive feedback with the class-e configuration to form an injection-locked oscillator whose oscillation frequency is locked to that of the input signal [8]. The injection-locked oscillator used as power amplifier, however, is prone to locking onto interfering signals picked up by antenna from adjacent mobile users in the same transmit band [9]. On reliability grounds, it would also be more prudent to limit the voltage stress on a transistor to the recommended supply voltage (3.3 V for 0.35 m and 2.5 V for 0.25 m) rather than the maximum voltage ratings. Therefore, delivering RF power as high as 1 W still remains a challenge for a deep-submicron CMOS power amplifier. This paper describes a 900-MHz power amplifier in a m CMOS technology with 0.9-W output power employing the class-e topology to exploit its soft-switching property. In the class-e load network, a finite dc-feed inductor is used instead of an RF choke for high output power and efficiency. With the finite dc-feed inductor, the optimum load resistance can be greatly increased for the same output power and supply voltage. The voltage stress on the power transistor is further reduced by the common-gate switching scheme, increasing the allowable supply voltage. In Section II, the effect of scaling on the design of the CMOS power amplifier is described, revealing the difficulties of deepsubmicron CMOS power amplifier with high output power and efficiency. The design techniques used in this work to alleviate these difficulties are explained in Section III and the experimental results are shown in Section IV, followed by a conclusion in Section V /01$ IEEE

2 824 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 5, MAY 2001 TABLE I PERFORMANCE SUMMARY OF CMOS RF TRANSCEIVERS II. EFFECT OF SCALING ON THE SIGN OF CMOS POWER AMPLIFIER As the minimum channel length of the MOS transistor scales down, the safe operating voltage decreases and the supply voltage of the power amplifier should be reduced accordingly in order not to stress the active devices. Therefore, the quadratic dependence of the output power on the supply voltage ( ) requires the load resistance seen by the power amplifier to be reduced rapidly for a given output power. With lower supply voltage and load resistance, it becomes increasingly hard to realize a good power amplifier, as will be described in the following. The following description is focused on switching-mode class-e power amplifier because we have used class-e configuration in this work, but the general conclusions derived here can be applied to the other classes of both linear and switching-mode power amplifiers as well. The impedance matching network between the power amplifier and the antenna transforms the input impedance of the antenna, usually 50, to the optimum load resistance of the power amplifier. The power loss due to the finite quality factor of the reactive components of the impedance matching network is proportional to the impedance transformation ratio defined as. If a simple low-pass L-section matching network is used, the power lost in the matching network is given as where is the quality factor of the reactive components [10]. Therefore, the smaller load resistance required for a downscaled CMOS technology results in larger power loss in the impedance matching network and thus lower efficiency. The efficiency reduction by the finite switch on-resistance of a switching power amplifier becomes also more profound as technology scales down. Although decreasing channel length and increasing transconductance coefficient ( ) enable the on-resistance of the switch to improve, this improvement (offset also by the reduction in gate drive) is slower than the decrease of the required load resistance for the given supply voltage and output power. The maximum possible supply voltage for a class-e power amplifier with an RF choke is shown in Fig. 1(a) versus the minimum channel length. With this value, the load resistance for 1.0-W output power can be calculated from [11] (1) (2) Fig. 1. (a) Maximum possible supply voltage and the load resistance R for 1.0-W class-e power amplifier with RF choke. (b) On-resistance r of an nmos switch per unit channel width, the load resistance R, and r =R versus minimum channel length L. The maximum possible supply voltage is calculated as the maximum voltage ratings divided by 3.57 (voltage stress of an ideal class-e power amplifier is 3:57 2 V ) for a given technology. and the result is also shown in Fig. 1(a). In Fig. 1(b), the load resistance, the on-resistance of an nmos switch per unit channel width, and the ratio are shown against the minimum channel length. The on-resistance is obtained by simulating a transistor with the minimum channel length and the gate overdrive voltage equal to the nominal supply voltage for a given technology and then normalizing to the value per unit channel width. From the figure, it is evident that the ratio increases as the technology scales down because of the faster decrease of the load resistance than the switch on-resistance. Since the drain efficiency () of a class-e power amplifier is inversely proportional to the ratio as derived in the Appendix (3)

3 YOO AND HUANG: COMMON-GATE SWITCHED POWER AMPLIFIER 825 Fig. 2. Waveform of a switching-mode power amplifier with hard switching. the slower improvement of the on-resistance of the switch than the load resistance results in reduced efficiency. To alleviate this problem, the switch transistor should be wide enough so the ratio is negligibly small. The switch transistor, however, cannot be made arbitrarily wide because it could render too large parasitic capacitance to be absorbed into the shunt capacitance of the load network. The power loss by the parasitic resistance of the reactive components of the load network is also proportional to the ratio of the parasitic resistance to the load resistance. Therefore, the increase of the inductor and capacitor loss relative to also decreases achievable efficiency as the technology scales down. In this work, the above-mentioned problems are solved by employing the class-e configuration with finite dc-feed inductance and common-gate switching scheme as described in Section III. III. COMMON-GATE SWITCHED CLASS-E POWER AMPLIFIER WITH FINITE DC-FEED INDUCTANCE As explained in Section II, the design of a high-efficiency CMOS power amplifier becomes far more difficult as technology scales down due to the reduction of the supply voltage and the load resistance. Therefore, our focus in the design of a m CMOS power amplifier is on finding ways to relieve the pressure on the supply voltage and the load resistance. In this section, two design techniques for this are explained: the class-e configuration with finite dc-feed inductance and the common-gate switching scheme. A. Class-E Power Amplifier with Finite DC-Feed Inductance Switching-mode power amplifiers such as class D, E, and F generally have higher efficiency than linear power amplifiers because an ideal switch does not have an overlapped period of nonzero switch voltage and nonzero switch current. In practice, however, the transition between the ON and OFF state of a switch takes finite time, during which substantial amount of power can be dissipated as shown in Fig. 2. This kind of switching is called hard switching and is one of the main reasons for efficiency reduction in switching-mode power amplifiers such as class D and class F. On the contrary, the load network of a class-e power amplifier in Fig. 3(a) is synthesized so the switch voltage returns to zero with zero slope right before the switch turns on, ensuring no overlap of nonzero switch voltage and nonzero switch current, as shown in Fig. 3(b) [11]. This soft-switching property Fig. 3. (a) Class-E power amplifier. (b) Its voltage and current waveforms. of the class-e power amplifier minimizes the power loss in the switch and thus highly efficient power amplification is possible for constant-envelope modulated signals such as Gaussian minimum shift keying (GMSK) used in Global System for Mobile (GSM). In a class-e load network ensuring soft switching, the dc-feed inductor can be either an RF choke or a finite inductor. One way to provide the relief on the supply voltage and the load resistance is to use a finite inductance instead of an RF choke for the dc feed [12]. If the dc-feed inductance is finite, we have one more degree of freedom the value of dc-feed inductance in choosing the element values for a given output power than with an RF choke. The load resistance is now a function of the output power, supply voltage, and the dc-feed inductance while it is determined only by the output power and supply voltage in case of implementing with an RF choke. Therefore, the load resistance could be larger than that with an RF choke if the optimum value of finite dc-feed inductance is used. While we have analytic solutions to the element values of a class-e load network with an RF choke, the element values for finite dc-feed inductance should be obtained by solving a set of differential equations with iterative numerical methods [11], [13]. Fig. 4 shows the optimal values of the shunt capacitance ( ) and the load resistance in the class-e load network of Fig. 3(a) for 1-W output power with V versus the dc-feed inductance ( ). The element values are independent of the operation frequency if denoted as impedance. For comparison, the load resistance values of other classes (class A, D, and F) of power amplifiers are also shown in the figure. As can be seen in the figure, if the dc-feed inductor is chosen to be finite in the shaded re-

4 826 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 5, MAY 2001 Fig. 4. Element values of class-e load network shown in Fig. 3(a) for 1.0-W output power with V =1:8 V(B =!C, X =!L ). Fig. 5. Simulated waveforms of the class-e power amplifier in Fig. 6. gion, the load resistance and the shunt capacitance are larger than those of class-e power amplifier with an RF choke and the other classes of power amplifiers. With the dc-feed inductance nh at 900 MHz, the optimum load resistance reaches a peak of 4.4, which is more than twice that for an RF choke. Compared to other classes of both linear and switching-mode power amplifiers, the load resistance is also 2 3 times higher than for class A and for class D and F, as shown in Fig. 4. The required shunt capacitance is now 60% larger than that for an RF choke, which can absorb 60% larger parasitic capacitance of wider switching transistors therefore, the switch on-resistance can be smaller whereas is small enough to be implemented by bonding wire. Therefore, for the same output power and supply voltage, higher efficiency can be achieved in a class-e power amplifier with finite dc-feed inductance. One further advantage is that the additional degree of freedom provided by finite dc-feed inductance enables the shunt capacitance and the load resistance to be set in such a way that, for a constant output power, the peak voltage stress on the switch is no longer, as is the case for an ideal class-e power amplifier with an RF choke. At a limited efficiency of 50% 60% or less for practical class-e power amplifiers, the peak voltage stress can be as low as, as illustrated in the simulated waveforms in Fig. 5, which is obtained from SpectreRF simulation of the circuit in Fig. 6 with V and V [14]. B. Common-Gate Switching It was shown that the class-e configuration with finite dc-feed inductance increases the load resistance for a given output power and supply voltage by exploiting the property that the load resistance is a complex function of the dc-feed inductance. For further increase of the load resistance, it is desirable to find the way to allow higher supply voltage for a given technology without stressing the transistors because the load resistance is basically proportional to the square of the supply voltage. Usually, the power transistor is switched from the gate as shown in Fig. 7(a), but the maximum voltage stress on the Fig. 6. Common-gate switched class-e power amplifier with finite dc-feed inductance. transistor is which can be as high as for an ideal class-e power amplifier, resulting in low supply voltage and in turn small load resistance and lower efficiency. On the contrary, if the power transistor is switched from the source instead of the gate as shown in Fig.7(b), the maximum voltage stress is reduced to because the source of the switching transistor swings up with the input voltage [15]. Therefore, the maximum allowable supply voltage is times larger for common-gate switch than that for a simple common-source switch. In order to avoid presenting the input driving stage with a low impedance node, a common-source stage is combined with the common-gate switch into a cascode as shown in Fig. 7(c). During the OFF state, the drain voltage of the common-source switch transistor rises to, which in a m technology is roughly 2 V if is 2.5 V. Since the common-gate switch can safely sustain another 2.5 V, the allowable maximum voltage stress on the combined switch is 4.5 V for a m technology. This allows the supply voltage to be as high as about 1.8 V, which is almost twice the value allowed for a single common-source switch. The additional benefit of the common-gate switching is the reduced output input coupling that is problematic at high frequency [16].

5 YOO AND HUANG: COMMON-GATE SWITCHED POWER AMPLIFIER 827 Fig. 7. (a) Common-source. (b) Common-gate switch. (c) Common-gate switch combined with common-source stage into a cascode in order not to provide low-impedance load to the driving stage. (d) Maximum voltage stress is shown for each case assuming the input signal V swings from 0 V to V. Since a cascode switch has higher switch on-resistance per unit channel width than a single common-source switch during the ON state, wider transistors (15 mm) have been used so that the resulting loss due to the switch on-resistance is sufficiently small compared to the loss in the reactive components of the load network. The large junction capacitances associated with the output node of the wide cascode switch can still be absorbed by the shunt capacitance, which is increased by 60% due to the finite dc-feed inductance as explained in the previous section. The gate capacitance of the 15-mm-wide cascode switch, on the other hand, is as high as 26 pf. To mitigate its loading on the preceding driver stage, a 2-nH bondwire inductance is used to resonate out the gate capacitance, as shown in the single-ended version of the common-gate switched class-e power amplifier in Fig. 6. An external series capacitor is also included in the LC network to allow some fine tuning of the resonant frequency. The push pull input stage operates in class-c mode. By employing these two design techniques, class-e configuration with finite dc-feed inductance and the common-gate switching scheme, high output power can now be delivered without forcing the load resistance value. to an unrealistically low IV. EXPERIMENTAL RESULTS Fig. 8 is the photograph of the power amplifier fabricated in a 1-poly 6-metal m CMOS technology whose active area is 2.0 mm 2.0 mm. During test, a bare die has been attached directly to the ground plane of the printed circuit board to minimize the length of the bonding wires and help heat dissipation. Since the quality factor of the inductors is critical in high-efficiency power amplifiers, on-chip spiral inductors in a typical CMOS technology cannot be used because of the large loss in the silicon substrate and metal layers. Instead, bonding wires have been successfully used as high- inductor in power amplifier [8] and it has recently been shown that the machine-bonded bonding wires have less than 5% inductance Fig. 8. Microphotograph of the power amplifier. variation and less than 6% quality-factor variation [17]. For these, aluminum bonding wires of 25- m diameter are used in this work for inductor realization. The inductance of the impedance matching network is merged with that of the class-e load network, so that the complete passive network of the output stage of the power amplifier consists of two aluminum bonding wire inductors and one on-chip (37 pf) and two off-chip capacitors (20 and 14 pf). The implemented power amplifier is differential and baluns are used at both the input and the output to combine the two single-ended paths. The measured output power, drain efficiency, and PAE of the power amplifier at 900 MHz are shown against the supply voltage in Fig. 9. At the designed supply voltage of 1.8 V, the power amplifier delivers 0.9-W power to the 50- load. The drain efficiency is roughly constant, reaching 46% at 0.9 W, where the PAE reaches 41%. Measurements shown in Fig. 10 confirm that output power, drain efficiency, and PAE are fairly constant over a 60-MHz frequency range. In order to verify the operation of the power amplifier with a constant-envelope modulated signal, a GMSK signal with has been applied, and the amplified output spectrum of the power amplifier is shown in Fig. 11 together with the GSM spectral emission

6 828 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 5, MAY 2001 TABLE II PERFORMANCE SUMMARY OF CMOS POWER AMPLIFIERS Fig. 9. Measured output power, drain efficiency, and PAE as a function of the supply voltage. Fig. 11. Amplified output spectrum of GMSK signal with BT =0:3. Fig. 12. Class-E power amplifier while the switch is turned on. The switch on-resistance is r and it is assumed there is no flow through the shunt capacitor C. Fig. 10. Output power, drain efficiency, and PAE as a function of the operation frequency. mask. The output spectrum of the power amplifier is confined in the GSM spectral emission mask for the whole output power range. As summarized in Table II, this power amplifier has achieved comparable performance to the other CMOS power amplifiers despite the much lower breakdown voltages of the m CMOS technology. If the supply voltage is allowed to increase up to 1.9 V, the power amplifier can deliver 1.0 W with 41.4% power added efficiency while the maximum voltage stress on the power transistor is still within 10% of the recommended supply voltage 2.5 V of the m CMOS technology.

7 YOO AND HUANG: COMMON-GATE SWITCHED POWER AMPLIFIER 829 V. CONCLUSION For compact low-cost and low-power portable radio devices, highly integrated CMOS RF transceiver has been arousing considerable interests for the last few years. In this paper, a power amplifier, one of the most challenging circuits for CMOS RF transceiver, implemented in a standard m CMOS technology is described. In order to achieve high efficiency at high power level, the class-e topology with finite dc-feed inductance is used and the common-gate switching scheme is employed to avoid stressing the active devices. The experimental results show the power amplifier can deliver 0.9-W output power to 50- load at 900 MHz with 41% PAE from a 1.8-V supply. With the trend moving toward lower power class (20 24 dbm) transmitters in next generation wireless standards, the results achieved in this design present another step forward toward showing that CMOS power amplifiers with good efficiencies are realistic despite steadily declining field-effect transistor breakdown voltages. APPENDIX RIVATION OF (3) During the ON state ( ), where is the dc current through RF choke we have only dc current through an RF choke and and are the current through the switch and the load resistor, respectively, as shown in Fig. 12. It is assumed there is no current flow through the shunt capacitor because the switch voltage would not change much during the ON state. Since the current through the load resistor is given as [11] (A-1) where is the voltage swing across the load resistor and is radian, the current through the switch is Thus, the power can be calculated as and the output power is given as From (A-2) and (A-3) (A-2) dissipated by the switch on-resistance (A-3) (A-4) where equal to Thus is the output power and dc power supplied by. From (A-5) and (A-7) (A-8) (A-9) From (A-4) and (A-6), the voltage swing across the load resistor is thus In [11], it was found that Substituting (A-11) and (A-12) into (A-9) gives and rearranging the terms in (A-13) Since is radian (A-10) (A-11) (A-12) (A-13) (A-14) (A-15) The drain efficiency () is given as (A-5) (A-6) (A-7) REFERENCES [1] A. Abidi, A. Rofougaran, G. Chang, J. Rael, M. Rofougaran, and P. Chang, The future of CMOS wireless transceivers, in Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1997, pp [2] J. C. Rudell, O. Jia-Jiunn, T. B. Cho, G. Chien, F. Brianti, J. A. Weldon, and P. R. Gray, A 1.9-GHz wide-band IF double conversion CMOS integrated receiver for cordless telephone applications, in Int. Solid- State Circuits Conf. Dig. Tech. Papers, Feb. 1997, pp [3] M. Steyaert, M. Borremans, J. Janssens, B. de Muer, I. Itoh, J. Craninckx, J. Crols, E. Morifuji, S. Momose, and W. Sansen, A single-chip CMOS transceiver for DCS-1800 wireless communications, in Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1998, pp

8 830 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 5, MAY 2001 [4] S. Wu and B. Razavi, A 900-MHz/1.8-GHz CMOS receiver for dual-band applications, in Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1998, pp [5] P. Orsatti, F. Piazza, Q. Huang, and T. Morimoto, A 20-mA-receive 55-mA-transmit GSM transceiver in 0.25-m CMOS, in Int. Solid- State Circuits Conf. Dig. Tech. Papers, Feb. 1999, pp [6] Q. Huang, F. Piazza, P. Orsatti, and T. Ohguro, The impact of scaling down to deep-submicron on CMOS RF circuits, IEEE J. Solid-State Circuits, vol. 33, pp , July [7] D. Su and W. McFarland, A 2.5-V 1-W monolithic CMOS RF power amplifier, in Proc. Custom Integrated Circuits Conf., May 1997, pp [8] K.-C. Tsai and P. R. Gray, A 1.9-GHz 1-W CMOS class-e power amplifier for wireless communications, IEEE J. Solid-State Circuits, vol. 34, pp , July [9] B. Razavi, RF transmitter architectures and circuits, in Proc. Custom Integrated Circuits Conf., May 1999, pp [10] P. L. D. Abrie, Design of Impedance-Matching Networks for Radio- Frequency and Microwave Amplifiers. Norwood, MA: Artech House, [11] N. O. Sokal and A. D. Sokal, Class-E, a new class of high-efficiency tuned single-ended power amplifiers, IEEE J. Solid-State Circuits, vol. SC-10, pp , June [12] R. E. Zulinski and J. W. Steadman, Class-E power amplifiers and frequency multipliers with finite dc feed inductance, IEEE Trans. Circuits Syst., vol. CAS-34, pp , Sep [13] T. Sowlati, C. A. T. Salama, J. Sitch, G. Rabjohn, and D. Smith, Low-voltage high-efficiency GaAs class-e power amplifiers for wireless transmitters, IEEE J. Solid-State Circuits, vol. 30, pp , Oct [14] Analog Artist Users Guide SpectreRF. San Jose, CA: Cadence Design Systems, [15] C. Yoo and Q. Huang, A common-gate switched 0.9-W class-e power amplifier with 41% PAE in 0.25-m CMOS, in Symp. VLSI Circuits Dig. Tech. Papers, June 2000, pp [16] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. New York: Wiley, [17] Y.-G. Lee, S.-K. Yun, and H.-Y. Lee, Novel high-q bondwire inductor for MMIC, in Int. Electron Devices Meeting Dig. Tech. Papers, 1998, pp Changsik Yoo (S 92 M 00) was born in Daejon, Korea, in He received the B.S. (with the highest honor), M.S., and Ph.D. degrees from Seoul National University, Seoul, Korea, in 1992, 1994, and 1998, respectively, all in electronics engineering. After receiving the Ph.D. degree, he worked at Samsung Electronics for five months, developing high-speed interface circuits. From 1998 to 1999, he was with the Integrated Systems Laboratory, Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, as a Member of Research Staff working on CMOS RF circuits. He has been with Samsung Electronics, Kiheung, Korea, since Dr. Yoo received the Silver Prize in the IC design contest held by LG Semicon (now Hyundai Electronics) in 1996 and the Bronze Prize in the mathematics contest held by Postech in Qiuting Huang (S 86 M 88 SM 96) graduated from the Department of Precision Instruments, Harbin Institute of Technology, in He received the Ph.D. degree from Katholieke Universiteit Leuven, Departement Elektrotechniek, ESAT Laboratories, Heverlee, Belgium, in Between 1987 and 1992 he was a Lecturer at the University of East Anglia, Norwich, U.K. Since 1993, he has been with the Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zurich, where he is a Professor in electronics. His general field of research is in analog and mixed analog-digital integrated circuits and systems. His current research projects include RF front-end, as well as baseband integrated circuits for wireless communications, interface circuits to sensors and actuators and low noise, low power ICs for biomedical applications.