A 200-MHz Sub-mA RF Front End for Wireless Hearing Aid Applications

Transcription

1 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY A 200-MHz Sub-mA RF Front End for Wireless Hearing Aid Applications Armin Deiss, Student Member, IEEE, Dirk Pfaff, Student Member, IEEE, and Qiuting Huang, Senior Member, IEEE Abstract A hearing-aid system with RF connection between both ear-pieces is described and its transceiver is introduced. A suitable 200-MHz RF front end has been implemented in a 0.8- m BiCMOS technology. Low power consumption and area constraint were key requirements. The chip comprises a low noise amplifier (LNA), a single balanced mixer, a varactor tuned LC local oscillator with buffer and a 16/17 dual-modulus prescaler. The LNA has a measured gain of 17.5 db at 200 MHz. The conversion of the mixer is 1.88 ms. The overall voltage gain and noise figure are 26 db and 5.2 db, respectively. The voltage-controlled oscillator s (VCO s) phase noise is dbc/hz at an offset of 24 khz. Index Terms Hearing aid system, RF front end, low power. I. INTRODUCTION IN recent years, digital signal processing has become widespread in hearing aid devices. Research has also suggested that further improvement in hearing quality could be achieved by having an ear-piece in each ear and processing the signals in both jointly [1]. This contribution reports part of a feasibility study of the low-power implementation of bi-aural hearing aids. In a noisy environment, hearing-impaired people face the problem that they have difficulties distinguishing between desired and surrounding, disturbing signals. No matter how good and strong the amplification is, the signal-to-noise ratio won t be increased because the system is unable to separate wanted and unwanted signals. One approach to tackle this drawback is to recognize that the desired signal source normally is right in front of the listener while the interferers might come from any direction. This signal correlation can be exploited with a system with two earpieces as shown in Fig. 1. Microphones and record the acoustic environment consisting of the source equidistant from and and a disturbance signal reaching a time delay after From the two received signals two new signals can be derived, namely Manuscript received November 16, 1999; revised January 31, The authors are with the Integrated Systems Laboratory, Swiss Federal Institute of Technology (ETH), Zurich CH-8092 Switzerland. Publisher Item Identifier S (00) (1) (2) and is independent of but correlated to By estimating with a guess of the desired signal can be calculated and fed to the loudspeakers and II. SYSTEM OVERVIEW In order to perform the operations described above, the two microphones have to be connected, for example, by means of RF links. One idea might be to connect the two ear-pieces with a direct RF link mainly through the head as depicted in Fig. 2(a). This configuration has at least one severe drawback. All signal processing has to be done in the ear-pieces themselves, which consumes a considerable amount of power. To limit the size of the earpiece, an alternative configuration, see Fig. 2(b), can be used. An additional signal processing unit is attached to the body and establishes the exchange of information between the ear-pieces. Sound signals received by the ear-pieces are transmitted to the body unit after a minimum amount of signal conditioning using two RF links. The processing of the bi-aural signals mainly takes place in the body unit, where space and battery power is less critical. Although the limited distance of about 1 m between body unit and ear-pieces makes a low-power transmitter possible, signals received by the RF receiver in both the earpieces and the body-unit remain weak and the external radio environment is complex, so that the design of a physically small low-power receiver remains a strong challenge. III. SYSTEM DESIGN AND TRANSCEIVER ARCHITECTURE The most notable obstacle to adding an RF link to a hearing aid is the lack of space. Of the 1 cm of space available to an ear-piece, a substantial part is already taken by the usual components of a hearing aid, such as the battery, the microphone, the speaker, and the IC implementing baseband functions. For the RF link design, the limited space strongly affects the choice of the operating frequency, which involves a trade-off between component size and power consumption. Even in a highly integrated transceiver, a small amount of off-chip components, such as the antenna, RF and possibly IF filters as well as some L, C elements for impedance matching, must be used. High frequency is thus desirable from the point of view of antenna (which is very small) efficiency and the dimensions of passive components. Considering power consumption, (3) /00$ IEEE

2 978 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000 Fig. 1. Noise reduction principle. Fig. 2. (a) (b) (a) Simple configuration. (b) Chosen configuration. The RF links to the body-unit then are switched off, and each earpiece operates as a stand-alone amplifier. To accommodate multiple users, the system is designed to be multichannel, each of which 200 khz wide. A bandwidth of at least 4.8 MHz is required for six simultaneous users, using every second channel and one for each RF link, thus four per user. An 8-ary phase-shift keying (PSK) modulation scheme is planned to support the required high data rate of 336 kbit/s. Full duplex links are intended between the body unit and the two ear-pieces through time division multiplex (TDM). The transceiver architecture is superheterodyne, as shown in Fig. 3. In the initial phase of the RF receiver development, we have implemented all of the circuit building blocks working at the highest RF frequency range, which normally account for 80% 90% of the overall power consumption. They are the low noise amplifier (LNA), mixer, voltage-controlled oscillator (VCO), and the prescaler. The target current consumption is around 1 ma for the overall receiver, from a low supply voltage of 2 V. however, lower frequencies are preferred. In the absence of dedicated usable RF frequencies for such hearing aid applications, the intended RF link can only be established within officially allocated industrial, scientific, and medical (ISM) bands, which limits the choice to a few frequency ranges such as 30, 200, 400 and 900 MHz. Although the higher end of 900 MHz is ideal in terms of component size, the power consumption can be excessive. Even the lowest power consumption reported for Global System for Mobile Communications (GSM) RF receivers at this frequency is an order of magnitude higher than what is acceptable for a hearing aid [2], while paging receivers are now reported to use 3 ma [3], [4]. The same low-power paging receiver [4] may be operated at 200 MHz as well, consuming less than 3 ma. Together with our previous studies on European Radio Messaging System (ERMES) paging receivers [5], it shows that sub-ma RF receivers are feasible with a 1.2- m BiCMOS technology with acceptably small external components. The ISM band widely used in Europe, MHz, has therefore been selected for our application. This band is used for low-power services like radio microphones or tour guide systems with an effective radiated power of 2 mw for unlicensed and 10 mw or 50 mw for licensed services [6]. Besides, this band is used for terrestrial TV broadcasting, with power levels well in the 100-kW range. The system is switched to a mono mode in case of interference or of blocking signals becoming too strong. IV. LOW POWER CONSIDERATIONS With a constraint of 1 ma, the bias current available to most of the transistors in the front-end circuits is of the order of 50 A. At this level of bias, the of the transistor is small, which makes shot noise dominate. The low bias current also corresponds to a large input resistance which reduces the transistor s [5]. To achieve low-power operation without substantial reduction in performance, the matching from the LNA to the antenna must be optimized to provide a fair amount of voltage gain and keep the impedance seen by the LNA input moderate. The LNA must also have sufficient gain to minimize the noise contribution of the mixer, which entails high output impedance for the LNA and some concession in linearity. The emitter coupled logic (ECL) flip-flops in the prescaler must be optimized to achieve a clock speed/current ratio significantly higher than present commercial devices and the VCO must rely on a good quality resonator made of off-chip surface mount device (SMD) inductor and varactors. V. DESIGN The block diagram of the front end is shown in Fig. 4, where RF and inter-stage filtering is achieved by an SMD inductor resonating with the effective capacitance combining that of the

3 DEISS et al.: A 200-MHz Sub-mA RF FRONT END FOR WIRELESS HEARING AID APPLICATIONS 979 Fig. 3. Transceiver architecture. antenna, an external capacitor and the on- and off-chip parasitics. The RF resonator is high which may require trimming, whereas the inter-stage filter is low where no trimming is required. Where necessary, an on-chip proportional to absolute temperature (PTAT) current source is used to derive bias for the active circuits and maintain temperature independence of gain. A. Low Noise Amplifier A two-stage amplifier, shown in Fig. 5, has been used to achieve around 18 db of voltage gain for the LNA. The design is discussed together with antenna and RF filter, starting at the input. Commercially available RF filters are optimized for 50 termination and are therefore not usable for this design. Another approach to realize the required characteristics has to be pursued. The very small distance between components relative to the signal wave length and the decision to allow the input capacitor to be trimmed enable us to couple the LNA input to the antenna as shown in Fig. 5. The equivalent circuit of an electrically small monopole antenna is a capacitance in series with a small radiation resistance The latter reflects the antenna efficiency, whose theoretical value can be calculated with [7] and is 70 m valid for an ideal ground plane. However, it can be considerably lower in practice. The antenna capacitance can be estimated as [7]: (4) (5) Fig. 4. Block diagram. This gives a typical value of 0.3 pf for an antenna with length = 2 cm, diameter = 1 mm and wavelength 1.5 m at 200 MHz. The input resistance of a transistor with a bias current of 50 A and a forward current gain of 100 is 52 k Power matching of the antenna resistance to this impedance would result in a! Directly connecting the antenna to the input transistor, on the other hand, is not feasible either due to the high and poorly controlled input impedance. Additionally, the antenna capacitance and the parasitic capacitances at the input (from the board, pad, and transistor) form an unwanted capacitive divider for the antenna signal These arguments

4 980 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000 Fig. 5. Schematic of antenna and LNA. Fig. 6. Transfer function A (f ): already preclude power matching as well as directly connecting the antenna to the LNA, without even taking into account the required RF filtering. These shortcomings can be overcome by adding just one external inductance and possibly a parallel capacitance. The input impedance of the LNA can be defined internally. is the resulting capacitance of the PCB board, pad, of the LNA and trimmer capacitance (if needed). The inductor forms a parallel resonance circuit with The resonance frequency is given by (6) Fig. 7. Noise behavior of the matching network. The inductor also provides a dc-path from the antenna to ground to prevent the antenna from being charged by statics. For low-frequency interferers, the antenna capacitance and the inductor form a high pass filter. High-frequency interferers are attenuated by the factor. The passive voltage gain from the antenna voltage source to the LNA input at the resonance frequency is given by with is the input resistance of the LNA (see also Fig. 7). We have chosen unity gain for the passive amplification, therefore (7) with being the input resistance resulting from the feedback resistor is the load of the first stage; and is determined by A. The chosen = 25.2 k together with and the final quality of the inductor determine In order to gain some insight into the matching circuit, we calculate the signal-to-noise ratio determined by the equivalent noise generators of the first transistor at the input of the circuit as a function of the input resistance see Fig. 7. The total input resistance is the parallel combination of and. The latter represents the equivalent shunt resistance resulting from. The passive voltage amplification is depicted by (7), and is the gain of the LNA. The output referred noise power spectral density at is k (8) The illustration of a possible RF filter characteristic is shown in Fig. 6. The components have to be chosen according to the desired center frequency and the necessary A quality factor of up to about 50 is feasible if trimming is allowed. The use of external components is beneficial since the antenna parameters are still subject to change. They can be adjusted to some extent without changing the IC. Defining the input resistance of the LNA with a parallel resistor to ground must be avoided for noise reasons. The feedback resistor in Miller configuration is used instead. (9) (10) The noise power spectral density at the input of the circuit is (11) (12) with (13)

5 DEISS et al.: A 200-MHz Sub-mA RF FRONT END FOR WIRELESS HEARING AID APPLICATIONS 981 The input referred signal-to-noise ratio follows immediately as (14) The above formula shows that the optimal in respect to signal-to-noise ratio is In practice, however, this is not feasible for different reasons. was introduced in order to determine the input resistance of the LNA and therefore has to be much smaller than and since the voltage gain of the passive network is linearly dependent on, the signal level might be raised too much for the amplifier s linearity. The effective noise contribution of the antenna, matching network and LNA together is expected to be = 4.4 nv/ Hz at the antenna input. The LNA noise was lowered to a value where the matching network dominates the noise. The main noise contribution,, follows from the final inductor of around 55, which corresponds to an equivalent parallel resistance of about 15 k The next contributors are the shot noise from the base-emitter junction of,, and its feedback resistor, These three noise sources account for more than 80% of The remaining noise generators are summarized as in (15) (17). (15) (16) nv Hz Hz nv (17) Hz Simulations by spectre agree with the calculations. The benefit of using the feedback resistor, instead of a shunt resistor to ground, can be illustrated by calculating the noise contribution of the shunt resistor of required value at the input of the LNA, which would dominate the input referred noise power spectral density with 6 7 nv/ Hz To reserve a flexibility to use the same LNA at 30 MHz, where a necklace type of induction loop could be used if acceptable by the user, ac coupling between the two stages is sacrificed. Since the bias level of the dc coupling point is defined from stage 1 by as well as from stage 2 by extra attention has been paid to relative match of the bias currents and of the two stages as well as of the two transistors themselves. The emitter size of the first transistor was chosen as = 10, meaning 10 times the unit size of 1.0 m 0.8 m, to lower the noise contribution of the base resistance yet not to reduce its significantly. The area of the second-stage transistor is derived from and gives an of 4 for a bias current of =50 A. (18) Fig. 8. Mixer schematic with external components. The image-reject filter between LNA and mixer consists of another parallel resonance circuit, which does not define the load for the LNA precisely, nor does the input impedance of the mixer. A second feedback resistor, = 5k, is used therefore, which enables the gain of the LNA to be effectively independent of the output inductor and the mixer input impedance. The gain of the LNA can be estimated using the following formula: (19) and are the loads of the first and the second stage, respectively. The mixer represents a load of = 8.2 k The load of the first stage is determined by the feedback resistor of the second stage, (20) This results in 19-dB gain for the LNA. Taking into account all nonidealities, a gain of around db is expected. The total current consumption is 110 A. The feedback resistors and as well as the gain of the first stage affect the compression of the LNA. For this circuit, a 1-dB compression point of 37 dbm was predicted by simulation, which is within the range anticipated by the application. B. Mixer With careful production and accurate components, a maximal of 10 is feasible without trimming for the image-reject LC resonator (Fig. 4) and yields an image rejection of 7 db for an IF of 10.7 MHz. Other filter types or a higher IF must be considered if stronger image rejection is required. Since LO feedthrough will be suppressed by the IF filter, a single balanced mixer, shown in Fig. 8, is used to achieve a given conversion with the least current and only one pair of switching transistors. With perfect switching, Due to nonideal switching, is normally assumed.

6 982 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000 The external IF filter requires a single ended signal and a specific and relatively low matching impedance of = 600 It is power-matched by an LC network to an integrated resistor of 15.6 k at the mixer output, to achieve 9.4 db conversion gain despite a low of 1.9 ms at = 200 A bias current. The of the matching network is 5 and was kept low to avoid the use of trimmers. The overall mixer gain to the input of the IF filter is given by (21) Since higher mixer amplification is needed in this application than in [5], and thus also its current consumption is higher. In a differential output configuration, the load is normally split into two equal parts and connected between and the collectors of the switching transistors. If a single-ended signal is required, one collector may be connected directly to The load of the other is doubled in order to maintain the amplification. In contrast to the differential configuration, 3 db more noise is generated [9]. This can be tolerated since the gain of the LNA is rather high. Therefore, the mixer doesn t contribute too much to the overall noise. If that s not tolerable, the signal can be taken differentially and converted to single end at the expense of additional external components. The amplifying transistor is biased with a replica circuit that is five times smaller. The size of the latter is minimal. Although beneficial for power consumption and noise, the division ratio between the active transistor and the replica can not be increased arbitrarily because of matching uncertainties and an increased In Fig. 8, = 46 A, which is slightly larger than to account for the base currents of both the replica and the active transistor. The nonlinearity behavior of the mixer is determined by The of a bipolar transistor without base and emitter degeneration resistors is 8.2 dbm, independent of its bias current [10]. The overall compression point of the RF front end is limited by the LNA. C. VCO and VCO-Buffer Low power and high phase noise requirement preclude ring oscillators and fully integrated oscillators. A high- LC-tank oscillator with an external inductor and a hyperabrupt junction varactor D1 D2 is used in this design, as shown in Fig. 9. The equivalent loss resistance in parallel with the tank, where represents all series resistance in the tank loop), has to be maximized for low power. Therefore, a large inductor and a small capacitor are preferred. The lower limit for the varactor capacitance is given by the parasitic capacitance of the circuit. The of the transistors and must be sufficiently high to compensate for the tank loss. The of the pmos current sources should be kept moderate to avoid adding too much noise. A conservative estimate of the steady state amplitude is (22) Fig. 9. Fig. 10. VCO and buffer schematic. Prescaler logic diagram. with the bias current of the pmos current sources. This formula is valid assuming a square wave current flowing through the tank. An upper limit can be calculated assuming the current through and to be impulses, in which case. The inductance of the coil is 220 nh and the bias current was set to 20 A. This results in a final VCO current consumption of 40 A. A differential buffer, consuming another 50 A, isolates the VCO from its loading circuits. Its amplification is The coupling capacitance causes a high-pass transfer characteristic and has to be large enough to prevent signal attenuation. A value of 3.4 pf was chosen, which is feasible due to the availability of poly poly capacitors. D. Prescaler The prescaler is a critical part of the full receiver in terms of power consumption. Indeed, commercial dual modulus prescalers in the 200 MHz range consume 1 2 ma, more than the overall power budget [8]. The prescaler has to operate at input frequencies between and for a mixer with the local oscillator frequency above the RF frequency, with [174; 223] MHz and = 10.7 MHz. Therefore MHz (23) A dual modulus prescaler has been chosen which divides by and The reference frequency

7 DEISS et al.: A 200-MHz Sub-mA RF FRONT END FOR WIRELESS HEARING AID APPLICATIONS 983 Fig. 11. Prescaler flip-flop with level shifter. Fig. 12. Biasing circuit. is equal to the channel width of 200 khz. The minimal input frequency of the prescaler is (24) Therefore, a maximal of has to be chosen, resulting in = 48 MHz. Fig. 10 shows a block diagram of the implemented prescaler. This topology, consisting of a synchronous part dividing by 4 or 5 and an asynchronous divider chain, is widely used in prescaler design. The prescaler can be driven directly with a 0-dBm signal from the VCO-buffer without any clock amplification. As an example, Fig. 11 shows flip-flop 4, including a level shifter. All flip-flops are ECL and must be sized properly to minimize current. The switching transistors have minimum emitter size (3 m 0.8 m) for small parasitic capacitance and the load is realized with high-ohmic poly resistors. A small load resistor speeds up the flip-flops due to a higher pole frequency but requires more tail current to maintain the logic swing. With the help of simulation, a very low current consumption of 60 A was found for flip-flop 1 3 by setting the load resistance to 6.7 k and logic swing to 400 mv. The voltage swing is proportional to its load resistor and the reference current, which is inverse proportional to a reference resistor (see description of the bias circuit). Since both resistors are matched, the voltage swing is independent of resistor spread. To save current further, logic gates have been merged into the flip-flops. Operating at lower speed, flip-flops 4 and 5 consume 38 A and 24 A, with loads of 13.4 k and 28.6 k respectively. The overall current consumption of the prescaler, 330 A, includes an ECL to CMOS level converter. E. Biasing The schematic of the biasing circuit is shown in Fig. 12. It needs to be PTAT to compensate for the negative temperature coefficient of the bipolar transistors s In order to generate a the current densities in and have to be different, which can be generated either by different sizes of and or and The transistor sizes in Fig. 12 are relative. (25)

8 984 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000 TABLE I CURRENT CONSUMPTION AND SIZE Fig. 14. LNA 1 dbcp and IIP : Fig. 13. Noise figure and gain of the LNA. An emitter area ratio of was chosen to achieve a and for reasons of a symmetrical layout. = 7.5 A with an k Start-up circuitry is provided to prevent the PTAT source from settling to the undesired stable point, = 0A. VI. MEASUREMENT RESULTS The dies were bonded directly on printed circuit boards. The measured current consumption of each block is listed in Table I together with the chip area. The overall chip area also includes pads with ESD protection. Using a spectrum analyzer, the LNA has been measured to have a minimal NF = 3.7 db at 197 MHz with input and output matched to 50 and a maximal gain of 17.6 db at 194 MHz (Fig. 13). Both are close to the designed values. For verification purposes, the LNA voltage gain was also calculated back from the measurements of the whole system and of the mixer alone. The result turned out to be virtually the same (17.5 db). The 1-dB compression point and were measured to be 37 and 20 dbm, respectively, as shown in Fig. 14. A = 1.88 ms was measured for the mixer, compared to the calculated 1.92 ms. Its output as a function of the oscillator level is shown in Fig. 15. It can be seen that above 70 mv of LO amplitude, the mixer gain is constant. The 1-dB compression point and were measured to be 17.6 and 7.1 dbm, respectively. These values are close to the expected values of 18 and 8 dbm. With the output matched to the IF filter impedance of 600 the voltage gain of the mixer, is measured to be 8.5 db. The set-up for the noise measurement is shown in Fig. 16. Input matching to 50 as well as image rejection is provided by while and match the output resistor of the mixer to the image filter and from there further to 50 Image rejection was 9 db (at MHz). The measured single sideband (SSB) noise figure translates to about 17 nv/ Hz of noise voltage at the input of the mixer. Fig. 15. Fig. 16. Mixer gain as a function of oscillator level. Noise figure measurement of the mixer. TABLE II GAIN AND LINEARITY PARAMETERS The measurement results of LNA and mixer are summarized in Table II. The phase noise of the VCO was measured indirectly at the prescaler output with the modulus set to 16. An offset of 1.5 khz at the prescaler output corresponds to an offset of 24 khz from the carrier of the oscillator. Figs. 17 and 18 show the prescaler output spectrum which corresponds to an oscillator frequency of 180 MHz. Phase noise was measured as low as dbc/hz

9 DEISS et al.: A 200-MHz Sub-mA RF FRONT END FOR WIRELESS HEARING AID APPLICATIONS 985 Fig. 17. Oscillator spectrum. Fig. 19. Oscillator tuning range. Fig. 20. Prescaler test set-up. Fig. 18. Oscillator phase noise. at an offset of 24 khz, which fulfills the requirements ( 100 dbc/hz at an offset of 100 khz, worst case) by a substantial margin and even meets the requirements for ERMES pagers. Fig. 19 shows the VCO tuning range, which is about 50 MHz, using a hyperabrupt junction varactor. Linearity is good, even for low tuning voltages. The prescaler input is driven directly from a signal generator to have full control of frequency and amplitude. See Fig. 20 for the test setup. The maximum operating frequency for both division ratios is 240 MHz while the circuit consumes 315 A. These values agree closely with simulations. Fig. 21 shows the required input amplitude versus input frequency. The prescaler shows a self-oscillation at around 190 MHz if the input remains open. This is an inherent property of the synchronous 4/5 divider. All measurements were performed with the modulus set to 17. The prescaler dividing by 16 and 17 is shown in Fig. 22. The overall measured voltage gain of LNA and mixer is 26.0 db with mixer output matched to 600 The 1-dB compression point and were measured to be 37 dbm and 24 dbm, respectively. In worst case conditions, the receiver will withstand in-band blockers of 2 mw till a distance of 8 Fig. 21. Prescaler input sensitivity. m, those of 10 and 50 mw until 17 and 37 m, respectively. Out-of-band blockers are partially filtered out by the RF filter. Even with a rather low- filter of just 20-dB out-of-band attenuation for high frequencies, typical TV stations of 10 kw in the frequency range of MHz interferring with stations at MHz cause the system to switch off the RF links at distances shorter than 1.6 km. With a filter of = 40, this distance is lowered to 500 m.

10 986 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000 Fig. 22. Prescaler dividing by 16 and 17. REFERENCES [1] B. Widrow and S. D. Stearns, Adaptive Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, [2] P. Orsatti, F. Piazza, Q. Huang, and T. Morimoto, A 20 ma-receive 55 ma-transmit GSM transceiver in 0.25 m CMOS, IEEE ISSCC Dig. Tech. Papers, pp , Feb [3] H. Darabi and A. A. Abidi, An ultralow power single-chip CMOS 990 MHz receiver for wireless paging, IEEE CICC Dig. Tech. Papers, pp , [4] UAA2080, advanced pager receiver, Philips Semiconductors, [5] F. Piazza and Q. Huang, A 170 MHz RF front-end for ERMES pager applications, IEEE J. Solid-State Circuits, vol. 30, pp , Dec [6] I-ETS , ETSI, Dec [7] G. Jansen, Kurze Antennen, Franckh, 1986, p. 20. [8] Datasheet MB15F05L, Fujitsu Microelectronics, Inc. [9] K. L. Fong and R. G. Meyer, Monolithic RF active mixer design, IEEE Trans. Circuits and Syst. II, vol. 46, pp , Mar [10] R. G. Meyer and A. K. Wong, Blocking and desensitization in RF amplifiers, IEEE J. Solid-State Circuits, vol. 30, pp , Aug Armin Deiss (S 98) was born in Altstätten, Switzerland, on August 15, He received the M.S. degree in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, in In 1997, he joined the Integrated Systems Laboratory of ETH, where he is currently working toward the Ph.D. degree. His main interests are low-power circuits for telecommunication applications. Fig. 23. Chip photograph. The overall SSB noise figure at 200 MHz is 5.2 db. All measurements were performed at nominal bias currents. A chip micrograph of the front end is shown in Fig. 23. VII. CONCLUSIONS Bi-aural signal processing is a potential way of improving hearing aid quality. The realization of full duplex RF links in such hearing-aid systems requires highly integrated IC s consuming very little power. With the integration of an LNA, a mixer, a VCO with buffer, and a dual-modulus prescaler, the most power-hungry parts of the receiver have been implemented in a commercial 0.8- m BiCMOS technology. Excellent characteristics measured in the MHz band at the low current consumption of 903 A demonstrate that in terms of power and size, it is feasible to realize miniaturized wireless hearing aids. ACKNOWLEDGMENT The authors would like to thank H. Kaufmann and R. Rheiner for their valuable contributions to this paper. Dirk Pfaff (S 98) was born in Switzerland in He received the Master s degree in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, in He is currently working toward the Ph.D. degree in the Integrated Systems Laboratory, ETH, Zurich. From 1995 to 1997 he was with Microswiss as a design engineer, where he was involved in mixed signal IC design. In 1997 he joined the Integrated Systems Laboratory, ETH, Zurich, as a Research Assistant. His research interests are in RF IC design with focus on frequency synthesis. Qiuting Huang (S 86 M 88 SM 96) graduated from the Department of Precision Instruments, Harbin Institute of Technology, in He received the Ph.D. degree from Katholieke Universiteit Leuven, Departement Elektrotechniek, ESAT Laboratories, Heverlee, Belgium, in Between 1987 and 1992, he was a lecturer at the University of East Anglia, Norwich, U.K. Since January 1993, he has been with the Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zurich, Switzerland, where he is an Associate Professor. His general field of research is in analog and mixed analog digital integrated circuits and systems. His current research projects include RF front end, as well as baseband integrated circuits for wireless communications, interface circuits to sensors and actuators and low-noise low-power IC s for biomedical applications.