Multi-Channel Audio CODEC with Channel Interference Suppression

Transcription

1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.6, DECEMBER, 2015 ISSN(Print) ISSN(Online) Multi-Channel Audio CODEC with Channel Interference Suppression Moo-Yeol Choi 1,2, Sung-No Lee 2, Myung-Jin Lee 2, Yong-Hee Lee 2, Ho-Jin Park 2, and Bai-Sun Kong 1 Abstract A multi-channel audio CODEC with interchannel interference suppression is proposed, in which channel switching noise-referred sampling error is significantly reduced. It also supports a coarse/fine mode operation for fast frequency tracking with good harmonic performance. The proposed multi-channel audio CODEC was designed in a 65 nm CMOS process. Measured results indicated that SNR and SNDR of ADC were 93 db and 84dB, respectively, with SNDR improved by 43 db. Those of DAC were 96 db and 87 db, respectively, with SNDR improved by 45 db when all the channels are running independently. Index Terms Multi-channel audio CODEC, deltasigma modulator, ADC, DAC, channel interference Manuscript received Feb. 17, 2015; accepted Jul. 28, 2015 This work was supported by Samsung Electronics 1 Sungkyunkwan University, Suwon, Gyeonggi-do, Korea 2 Samsung Electronics, Yongin, Gyeonggi-do, Korea bskong@skku.edu I. INTRODUCTION Recent audio CODECs for digital TVs and mobile phones are required to have multiple channels since audio applications for these systems may need to process various media sources and multiple concurrent user functions at the same time [1]. These channels may be operated with separate independent clocks coming from different clock sources for different applications. For example, an audio CODEC for a digital TV may communicate with external digital audio sources such as a DVD player, a game console and a home-theater, whose clock sources are different and independent [2, 3]. As the number of channels increases in an audio CODEC, a larger amount of switching noise will be generated by the channels operating concurrently. Especially in an IC implementation where all the channels of an audio CODEC are integrated on a single-die, each channel may have a high chance of being affected by increased switching noise of other channels due to proximity effects. For example, the switching operation of a channel may result in a noise voltage on critical nets in another channel through the substrate. The analog sampling circuit of a channel, which has to drive a capacitive load, may cause interference to adjacent channels through shared supply voltage and/or reference voltage. Increased switching noise in a multi-channel audio CODEC may invoke input-dependent harmonic components with increased noise floor in frequency spectrum, resulting in system performance degradation [4-6]. Especially, the sampled values of the sampling circuits in channels having different clock frequencies are mutually affected by channel interference due to audible inter-modulated tone noises, which cannot be avoided by a simple phase adjustment. As an example, let us assume that the oscillation frequencies of two clocks governing associated channels happen to be slightly different from each other (say, MHz and MHz, respectively). Then, the inter-modulated frequency will be a multiple of 5.12 khz that is in the audible in-band range, resulting in a severe degradation of SNDR. Using separate independent clock sources for controlling these channels worsens the situation since the switching noises generated in independent channels have no correlation, making switching noise behavior

2 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.6, DECEMBER, unpredictable. Therefore, suppressing the inter-channel interference noise in a multi-channel audio CODEC operated by independent channel clocks is emerging as a very important design issue. However, unfortunately, techniques for suppressing the total inter-channel interference noises in a multi-channel CODEC with independent clock sources have not been studied in the literature. Design techniques to just handle a single type of interference noise coupled through the substrate [4], shared supply voltage, or reference voltage have only been studied, [7-9]. An active substrate noise shaping [4] was used to minimize the switching noise by sensing and cancelling the switching signals coupled into the substrate. This technique can actively minimize the performance degradation due to substrate noise but incur an overhead in terms of power and area. For an improved power supply rejection characteristic, techniques for reducing the noise induced by shared supply voltage have been proposed [7, 8]. [7] adopted the dedicated lowdrop-out (LDO) regulator and [8] proposed the PSRRenhanced output stage with feedback amplifier to sense and track the current fluctuation by the supply noise. However, these techniques consume additional power for compensation and limit the maximum output range of the DAC. A reference voltage buffer with lower output impedance has been proposed to separate the reference of each channel from the shared voltage reference [9], but consumes large power. Since each of these techniques can handle just a single type of interference noise, they are not suitable for multi-channel configuration where noise situation is far more diverse and complex. To address this issue, a novel inter-channel interference suppression scheme is proposed and applied to the design of a multi-channel audio CODEC, where the channel switching noise-induced sampling error has been reduced. The rest of the paper is organized as follows. Section 2 presents the proposed multi-channel audio CODEC with detailed description on our interchannel interference suppression scheme. Section 3 provides the experimental measurement and comparison results. The conclusions are given in Section 4. II. PROPOSED MULTI-CHANNEL AUDIO CODEC Fig. 1 illustrates the multi-channel audio CODEC Fig. 1. Architecture of the multi-channel audio CODEC. adopting the proposed inter-channel interference suppression scheme. It is composed of one stereo ADC channel, three stereo DAC channels, a voltage/current reference generator, and an inter-channel interference suppressor. Four stereo channels implemented in a single-die are controlled by four independent channel master clocks (MCK1-MCK4) coming from different clock sources since our CODEC design is targeting for use in digital TVs receiving audio data from multiple external sources such as DVD players, game consoles, digital camera, and home-theaters, simultaneously [3]. The activation of each channel master clock and the onoff control of each channel are determined by the control SoC based on application scenarios. Four audio clocks (LRCK1-LRCK4) are used for audio data communication with audio DSP. The power supply and voltage reference pins are shared by all channels for the reduction of external components and packaging costs. Usually, the sampling circuits are sensitive to switching noise occurring at the vicinity of sampling time points [6]. This implies that performance degradation due to switching noise can be reduced by letting sampling operations be done at a time period where there is a minimum switching noise. For this to be done, the switching noise behavior during channel operation must be predictable. But, unfortunately in our case, since the frequencies of the clocks governing the channels may be different from each other and timevarying, it is not possible to predict the switching noise behavior accurately. To overcome this problem, a novel inter-channel interference suppression scheme, in which

3 610 MOO-YEOL CHOI et al : MULTI-CHANNEL AUDIO CODEC WITH CHANNEL INTERFERENCE SUPPRESSION Fig. 2. Channel interference suppressor. one of the four channel master clocks is selected as a channel reference clock to let all channels operate in a single clock domain, is proposed. With this approach, the switching operations of the channels can be made to occur at predefined time points, letting their noise behavior thus be predictable. The channel sampling operations can now be scheduled at time points where the switching noise is relatively small for having less noise incurred to sampled values. After that, to bring the sample rate of each channel data back to its original, a sample rate restoration is done using a time-varying digital interpolation filter. In here, a dual-mode operation has been adopted to speed up the process retaining good accuracy. Fig. 2 shows a detailed block diagram of the interchannel interference suppressor, composed of a reference clock selector and four sample rate restorers. As mentioned before, the reference clock selector selects one of the four channel master clocks (MCK1-MCK4) as the channel reference clock (R_MCK) for use as the master clock for all channels. Here, the channel master clock having the minimum jitter characteristic for each possible scenario is selected as the channel reference clock. The priority for master clock selection is preevaluated for each application scenario, and stored in a look-up table managed by the control SoC. The reference clock selector also selects by the same rule one audio clock associated with the selected R_MCK as the reference audio clock (R_LRCK). A sample rate restorer is composed of a clock period detector, a coarse/fine mode selector, an edge position finder, a multiplyaccumulate unit (MAC), and a data FIFO. The period of the input audio clock is identified by the period counter in the clock period detector, which is done by counting the number of R_MCK cycles during an audio clock cycle. Then, the difference between the period counter output and the accumulator output is scaled down by some factor, whose resulting value is added to the accumulator. The process of continuous accumulation for the difference after scaling down enhances the accuracy of detected audio clock period. The coarse/fine mode selector is used to select a proper scaling factor for speeding up the operation as described later. The edge position finder then identifies the position of the audio clock edge relative to that of R_LRCK. After that, the coefficients of the time-varying digital interpolation filter are calculated by MAC using the accurately detected period and relative edge positions of the audio clock. The channel sample values at required sample points are then interpolated using the input data in the FIFO and the coefficients determined by the MAC. The inter-channel interference suppressor is also capable of handling inputs with time-varying frequencies and supports a coarse/fine mode operation for fast frequency tracking with good harmonic performance. When the operation is initially started or the frequency difference between input and reference audio clocks is large, the coarse tracking mode is first selected, in which the frequency tracking step is relatively large to minimize the time required for tracking. After that, if the frequency difference becomes small, the fine tracking mode is selected, in which the tracking step becomes small to get a very fine frequency resolution for good harmonic performance. A suitable tracking mode is adaptively selected by a control signal generated using the frequency difference in time. The ADC having two sub-channels for stereo recording consists of 6-to-1 analog MUXs, programmable gain amplifiers (PGAs), analog deltasigma modulators (DSMs), and digital decimation filters, as shown in Fig. 1. The digital decimation filter is composed of a cascaded integrator-comb (CIC) filter and a two-stage half-band filter. The analog DSM has a thirdorder architecture with 128-oversampling ratio (OSR) and 5-level internal quantization, whose structure is depicted in Fig. 3. It has a cascaded integrator feedforward (CIFF) structure based on discrete-time switched-capacitor (SC) integrators, in which the use of single-stage telescopic op-amp for integrators reduces the

4 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.6, DECEMBER, Fig. 3. Analog delta-sigma modulator for ADC. power consumption of the DSM [10]. The summing amplifier in the CIFF DSM is eliminated by the capacitive passive summing to quantizer input. Each DAC in the audio CODEC consists of an interpolation filter, a digital DSM, a SC DAC and a second-order analog low-pass filter (LPF) with output stage [11]. The digital DSM has a second-order architecture with 128-OSR and 15-level quantization. Fig. 4 shows the analog circuit diagram of the audio DAC. The second-order analog smoothing filter with 2-stage op-amp after the 15-level SC DAC attenuates the shaped out-of-band noise and image. The SC DAC (left half of Fig. 4) has a fully differential structure for maximizing the immunity to common-mode noise and the smoothing filter (right half of Fig. 4) performs a differential-tosingle-ended conversion for providing a single-ended audio output. Fig. 4. SC-DAC and smoothing filter. III. PERFORMANCE EVALUATION Fig. 5. Die photograph of test chip. The proposed multi-channel audio CODEC was fabricated in a 65-nm 6-metal CMOS process, which occupies 2.18 mm2 as shown in the die photograph in Fig. 5. The deep N-well, which was used in conventional CODECs to block the switching noise coupling through the substrate, was not adopted in our design in order to reduce mask cost since the switching noise coupling was effectively eliminated by the proposed channel interference suppressor. Supply voltages, AVDD (3.3V) and DVDD (1.2V), are used as power supplies for the analog and digital blocks, respectively. Fig. 6 shows the measured results of ADC and DAC applied with 1-kHz input frequency, which include FFT plot for -3dBFS input and SNDR versus input level. In Fig. 6(a), for the conventional design where no measures for suppressing the inter-channel interference is applied, tone noises, which are inter-modulated by out-of-band harmonics of independent clocks, are folded into in-band, resulting in higher noise floor. For the proposed design, the in-band noise floor is drastically reduced by the use of the channel interference suppressor. The SNR and SNDR of the ADC in the proposed CODEC are measured to be 93dB and 84dB, respectively, with SNDR improved by up to 43dB, as indicated in Fig. 6(b). Fig. 6(c) also shows that the channel interference suppressor effectively lowers the inter-modulated switching tone noise and total noise floor for the DAC. The measured SNR and SNDR of the DAC are 96 db and 87 db,

5 612 MOO-YEOL CHOI et al : MULTI-CHANNEL AUDIO CODEC WITH CHANNEL INTERFERENCE SUPPRESSION (a) (b) (c) (d) Fig. 6. Measured results: ADC (a) FFT plot for -3dBFS input and its, (b) SNDR vs. input level; DAC, (c) FFT plot for -3dBFS input and its, (d) SNDR vs. input level. Table 1. Measured performance SNR (20-20 khz) ADC (Stereo) 93 db SNDR (-3 dbfs) 84 db Power consumption 11.9 mw 0.45 mm2 SNR (20-20 khz) 96 db SNDR (-3 dbfs) 87 db Power consumption 12.2 mw 0.32 mm2 Channel Interference Suppressor Power consumption 0.3 mw 0.2 mm2 Total (analog+digital) 2.18 mm2 DAC (1ch Stereo) respectively. Fig. 6(d) also shows that the proposed architecture improves SNDR by up to 45 db. The measured performance of the multi-channel audio CODEC is summarized in Table 1. Power data for ADC and DAC include the power consumption of extra circuits such as BGRs, PGAs, MUXs (for ADC), LPFs and drivers (for DAC). The channel interference suppressor occupies 0.2 mm2 and consumes 0.3 mw power, which is 9% and 3% overheads in terms of area and power, respectively. As compared to the conventional substrate noise shaping [4] and PSRR enhancement [8] techniques showing 10 db and 22 db improvements, respectively, the proposed multi-channel audio CODEC with novel interference suppression can provide far better performance (43 db in terms of SNR and 45 db in terms of SNDR) for minimizing the total interference noise, and is very suitable for multi-channel configuration. IV. CONCLUSIONS This paper presents a multi-channel audio CODEC with suppressed inter-channel interference. It also supports a dual-mode operation for fast frequency tracking with good harmonic performance. Experimental results in a 65-nm CMOS process indicated a substantial performance improvement in terms of SNR and SNDR with small area and power overhead. REFERENCES [1] K. Nguyen, et al., A 106-dB SNR Hybrid Oversampling Analog-to-Digital Converter for Digital Audio, Solid-State Circuits, IEEE Journal of, Vol.40, No.12, pp , Dec., 2005.

6 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.6, DECEMBER, [2] S. H. Rhee, et al., A System-on-a-Chip Design for Digital TV, Journal of Semiconductor Technology and Science, Vol.5, No.4, pp , [3] P. Wallich, Digital hubbub, IEEE Spectrum Magazine, Vol.39, No.7, pp.26-31, July, [4] M. S. Peng and H. S. Lee, Study of Substrate Noise and Techniques for Minimization, Solid- State Circuits, IEEE Journal of, Vol.39, No.11, pp , Nov., [5] G. Boselli, G. Trucco and V. Liberali, Effects of Digital Switching Noise on Analog Circuits Performance, Circuit Theory and Design, ECCTD th European Conference on, pp , [6] T. Blalack and B. A. Wooley, The Effects of Switching Noise on an Oversampling A/D Converter, Solid-State Circuits Conference, ISSCC Digest of Technical Papers. IEEE International, pp , Feb., [7] T. Christen, A 15-bit 140-uW Scalable-Bandwidth Inverter-Based DS Modulator for a MEMS Microphone with Digital Output, Solid-State Circuits, IEEE Journal of, Vol.48, No.7, pp , July, [8] S. H. Wen and C. C. Yang, A 5.2mW, % THD up to 20kHz, Ground-Referenced Audio Decoder with PSRR-enhanced Class-AB 16W Headphone Amplifiers, VLSI Circuits, 2012 Symposium on, pp.20-21, [9] Y. Geerts, et al., A High-Performance Multibit DS CMOS ADC, Solid-State Circuits, IEEE Journal of, Vol.35, No.12, pp , Nov., [10] L. Yao, et al., A 1-V 140-uW 88-dB Audio Sigma-Delta Modulator in 90-nm CMOS, Solid- State Circuits, IEEE Journal of, Vol.39, No.11, pp , Nov., [11] Y. H. Lee, et al., A 4mW per-channel 101dB-DR Stereo Audio DAC with Transformed Quantization Structure, Custom Integrated Circuits Conference, CICC 06. IEEE, pp , Moo-Yeol Choi received the B.S., M.S. degrees in electrical engineering from Kyungpook National University, Daegu, Korea, in 2001 and 2003, respectively. He has been with Samsung Electronics Co., Ltd., Hwaseong, Korea, since 2003, where he is a senior engineer of the Mixed Signal Core Design Team. He is currently a Ph.D. student in department of semiconductor and display engineering, Sungkyunkwan University, Suwon, Korea, from the Samsung Electronics scholar program. His research interests include high-resolution delta-sigma modulators, lowpower data converters, and analog front-end of audio ADC and DAC. Sung-No Lee received the B.S. in electronic engineering from Ajou University, Suwon, Korea, in He has been with Samsung Electronics Co., Ltd., Hwaseong, Korea, since 2005, where he is a senior engineer of the Mixed Signal Core Design Team. His research interests include oversampled data converters, analog mixed-signal architectures, and digital signal processing for audio application. Myung-Jin Lee received the B.S., M.S. degrees in electronic engineering from Sogang University, Seoul, Korea, in 2003, and 2005, respecttively. He has been with Samsung Electronics Co., Ltd., Hwaseong, Korea, since 2005, where he is a senior engineer of the Mixed Signal Core Design Team. His research interests include analog mixed-signal circuits, high-speed delta-sigma modulators, and analog front-end of audio ADC and DAC.

7 614 MOO-YEOL CHOI et al : MULTI-CHANNEL AUDIO CODEC WITH CHANNEL INTERFERENCE SUPPRESSION Yong-Hee Lee received the M.S. degree in electronics engineering from the SungKyunKwan University, South Korea. Since 1993, he has been engaged in the design of the mixed signal circuits within Samsung Electronics. He has a variety of experiences as a designer of audio converters. His technical interests include delta-sigma converters and digital filter system with low power consumption. Ho-Jin Park received the B.S. in electrical engineering from Hanyang University, Seoul, Korea, in He has been with Samsung Electronics Co., Ltd., Hwaseong, Korea, since 1989, where he is a Vice President and is in charge of the Mixed Signal Core Design Team. He was engaged in the research and development of analog and mixed circuits for digital TV and mobile devices. His research interests are in the field of high-speed data converters, highresolution sigma-delta modulators, ultra-low power analog circuits, low-jitter phase-locked loops, all-digital phase-locked loops, power management circuits, sensors, and analog baseband/rf front-end circuits for wireless communi- cations. Bai-Sun Kong received the B.S. degree in electronics engineering from Yonsei University, Seoul, Korea, in 1990, and the M.S. and the Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Taejon, Korea, in 1992 and 1996, respectively. From 1996 to 1999 he was with LG Semicon (currently SK- Hynix Semiconductor), Seoul, Korea, as a senior design engineer, where he was working on the design of highdensity and high-bandwidth DRAMs. In 2000, he joined the faculty of Korea Aerospace University, Goyang, Korea, as an assistant professor at the School of Electronics Telecommunication and Computer Engineering. In 2005, he moved to Sungkyunkwan University, Suwon, Korea, where he is currently a professor at the College of Information and Communication Engineering. His research interests include highperformance microprocessor/memory architecture and circuit designs, high-speed I/O interface design, and IC designs for low-power/high-speed applications.