Two op-amps third-order sigma delta modulator with 61-dB SNDR, 6-MHz bandwidth and 6-mW power consumption

Transcription

1 Analog Integr Circ Sig Process (20) 66: DOI 0.007/s Two op-amps third-order sigma delta modulator with 6-dB SNDR, 6-MHz bandwidth and 6-mW power consumption Edoardo Bonizzoni Aldo Peña Perez Franco Maloberti Miguel A. Garcia-Andrade Received: 7 March 200 / Revised: 25 May 200 / Accepted: 7 September 200 / Published online: 9 September 200 Ó Springer ScienceBusiness Media, LLC 200 Abstract This low-power RD modulator targets the DVB- H reuirements and achieves about 0 bit with 6-MHz signal band. Suitable topological modifications enable the realization of a third order modulator with two op-amps. Moreover, a techniue for swing reduction of the last op-amp strongly reduces the number of comparators in the uantizer. The power reduction techniues limit the consumption to 6.8 mw, thus yielding a FoM of 0.58 pj/ conversion. The area of the circuit, fabricated with a 0.8-lm analog CMOS technology, is 0.32 mm 2. Experimental measurements confirm the behavioral study made accounting for the op-amps limitations. Keywords Introduction Sigma delta modulator Low power Sigma delta modulators for portable telecom applications reuire minimum analog accuracy to enable their implementation in digital technologies, relatively low oversampling ratio (OSR) to obtain medium-high resolution and high power effectiveness (or low figure of merit, FoM) to meet the low power reuirements. Accordingly, data converter specifications for digital video broadcast for handhelds (DVB-H) call for signal bands of 4 8 MHz, E. Bonizzoni (&) A. P. Perez F. Maloberti Department of Electronics, University of Pavia, Via Ferrata,, 2700 Pavia, Italy edoardo.bonizzoni@unipv.it M. A. Garcia-Andrade Universidad Autonoma de Baja California, Mexicali, Baja California, Mexico resolutions in the 60-dB range and foresee very limited power, typically less than 0 mw [ 3]. This paper addresses the above-mentioned specifications, namely 6-MHz band and 60-dB SNR, with the goal of power consumption well below 0 mw. A third order sigma delta architecture, a proper oversampling ratio and a relatively high number of uantization steps are the basis of this solution. Also, the design uses a techniue that achieves the third order function with two op-amps. The proposed circuit does not use Dynamic Element Matching (DEM) [4] because the expected linearity of resistor-based DACs is adeuate for the application. The circuit has been integrated in 0.8 lm analog CMOS technology. Experimental results show 9.8 bit of accuracy at 96-MHz clock and 6-MHz signal bandwidth. The total power consumption is 6.8 mw with.8-v supply voltage, resulting in a FoM of 0.58 pj/conversion [5]. The paper is organized as follows. Section 2 discusses possible strategies to reduce power consumption in sigma delta modulators leading to architectural choices for the designed converter. Sections 3 and 4 describe the modulator circuital implementations and the achieved measurement results. Section 5 gives some conclusions. 2 Design for minimum power consumption A defined full scale input and a given resolution establish the amount of noise budget that must be divided between various noise sources: predominantly, uantization noise, kt/c noise, interference noise and noise coming from references. Since, for low power applications, kt/c is the major concern, the uantization noise must be a fraction of the total budget. For this design, the power budget is assigned as follows. 23

2 382 Analog Integr Circ Sig Process (20) 66: P kt=c ¼ 0:5P N;tot P Q ¼ 0:25P N;tot P Int ¼ 0:5P N;tot P Ref ¼ 0:0P N;tot ðþ where P N,tot, P kt/c, P Q, P Int and P Ref are the total, kt/c, uantization, interference and reference noise power, respectively. Therefore, noise shaping must be able to bring the uantization noise below specification by 2 db. This provides room to the more power hungry kt/c term. Design parameters controlling power consumption of sigma delta modulators are the supply voltage, the oversampling ratio, the order of the modulator and the number of bit of uantization. Lowering the supply voltage at constant current reduces power. However, a reduced supply voltage diminishes the full scale of the converter, V FS, and, in turn, increases the relevance of the kt/c noise. For kt/c limited design, the SNR is OSRV 2 FS C/(6 kt). Therefore, a reduction of V FS reuires to increase the sampling capacitance. A given OSR, accuracy and input band determines the f T of the op-amp. In turn, the f T is proportional to g m /C. If transistors are in sub-threshold, g m is I D /(nv T ), while for transistors in saturation region g m depends on bias current as ci =2 D. Therefore, SNR becomes V 2 FS I D SNRj sub treshold ¼ OSRk f T V 2 FS I =2 D SNRj saturation ¼ OSRk 2 f T ð2þ where k and k 2 are design constants. Euation 2 shows that reducing by a factor a the supply voltage, that reduces by the same factor V FS, asks for compensation with an increased current in the transistor pair granting the transconductance gain. The current increase is by a 2 for transistors in sub-threshold and a 4 in saturation. Therefore, reducing the supply voltage is detrimental to power effectiveness: the designer should use the nominal voltage allowed by technology and not less. A second design option is to increase the oversampling ratio. As known, it improves SNR by an extent that depends on the order of the modulator. To secure one more bit, OSR should increase by.32 for a second order and by.2 for a third order modulator. However, higher sampling freuency reuires an eually augmented bandwidth of op-amps. It is proportional to the bias current of the input pair in sub-threshold and to the suare root of bias current with transistors in saturation. Therefore, one more bit in a second or third order modulator demands for an augmented current by 32 or 2% in the input pair in sub-threshold and 74 or 46% when in saturation. Therefore, increasing oversampling to augment SNR must be carefully considered in low-power applications. The number of op-amps euals the order of the modulator. Supposing to use same power in op-amps, the ones of a third order modulator consume.5 times more than a second order, but the modulator obtains higher SNR because of more effective noise shaping. The benefit on SNR depends on the OSR. Since there is a fixed cost p 2L / (2L? ) (L is the modulator order) eual to 2.9 db (2. bit) for second order and 2.4 db (3.5 bit) for third order, the advantage, in bit, is [log 2 (OSR) -.4]. With OSR = 8, the use of a third order instead than a second one gives.6 more bit and with OSR = 6, 2.6 bit. The figure is more power effective than increasing the OSR of a second order modulator, even at OSR =8. Another design option is the number of uantization levels that, obviously, costs an euivalent power. To ensure one extra bit, it would be necessary to double the power of the flash. This, for relatively low resolution, leads to an affordable cost because power consumed by a comparator is a small fraction of the op-amp power. For set of specifications in the video range (i.e., bandwidth higher than 5 MHz), a comparator consumes the 2 3% of an op-amp. Therefore, increasing the flash resolution from 3 to 5 bits, that means using 24 more comparators, costs 24 34% op-amps power with second order modulators and 6 24% with third order. Since accuracy increases by 2 bit, the power benefit is evident. However, many bits in the flash and, hence, in the DAC can be problematic when DEM becomes necessary. The points discussed above provide the guidelines for this design. Since SNR and SNDR reuirements are relatively low, the first choice is to use 5 bit uantization that, with OSR = 2 and second order noise shaping, grants a maximum theoretical SNR eual to 72.6 db. The same resolution, OSR = 8 and third order noise shaping lead to an SNR eual to 73.4 db. Since both expected SNRs allocate the reuired margin, the choice between two options depends on power. As discussed above, with transistors in sub-threshold region, the power consumption would be the same for both solutions, but, for transistors in saturation, as actually needed to satisfy our speed reuirements, the third order solution is the right choice because it consumes less. 2. Reduction of the number of op-amps Power is further reduced using only two op-amps to obtain third order noise shaping. The method used is described in this sub-section. Figure shows the selected third order sigma delta scheme [6]. It is based on a cascade of two integrators without delay and one with delay. The input feed-forward path limits the voltage swing of the first op-amp to the uantization noise level. Feedback coefficients necessary to make the noise transfer function (NTF) 23

3 Analog Integr Circ Sig Process (20) 66: eual to ð z Þ 3 are all. Therefore, this architecture optimizes the feedback factors at the expenses of using integrators without delay. High feedback factors admit lower bandwidth; integrators without delay impose higher bandwidth. Overall, the op-amp bandwidths turn out to be lower in this architecture without delays. Starting from Fig., a number of topological modifications eliminate one of the op amps. First, the feedback at input of the third op-amp is moved at input of second integrator multiplied by ( - z - ), as shown in Fig. 2(a). The feedback of the second integrator, that becomes (2 - z - ) as shown in Fig. 2(b), reuires a simple processing in digital domain before the second DAC. The scheme after removing intermediate feedback includes a double integrator, Fig. 2(c), which can be realized by one op-amp capable to implement the overall transfer function H 2 ¼ ð z Þ 2 ¼ ð z Þ z þ z 2 ð3þ The implementation of a double integrator, as shown in Fig. 3, consists in a conventional integrator with two extra feedback terms, one with single (P-path) and another with double delay (Q-path). The circuit, realized in the sampled data domain, reuires a limited increase of the op-amp power consumption (about 30%). Therefore, the solution saves 70% of power burnt by a single op-amp. st Integrator -z - 2nd Integrator -z - 3rd Integrator z - -z - Fig. Conventional third order sigma delta modulator (a) (b) st Integrator -z - _ st Integrator -z - _ -z - 2nd Integrator 2-z - -z - Moving this point 3rd Integrator (-z - ) 2 z - z - -z - z -/2 (-z - ) 2 -z - Fig. 3 Double integrator scheme 2.2 Reduction of the number of comparators In To further reduce power consumption, this design uses a second strategy for limiting the power of flash and, indirectly, the power of the second op-amp. The method is based on the observation that, for a given OSR, there is some correlation between two successive input samples. Moreover, with 5 bit, the uantization noise is low. Because of that, the output voltage increment of the second op-amp, eual to DV O;2 ¼½V in z þ Q ð 3z þ3z 2 z 3 ÞŠð z Þ ð4þ turns to be lower than V O,2 because the increase in the noise term is less than the reduction granted by V in ( - z - ). The feature suggests the scheme of Fig. 4, that uses as input of the flash the difference between V O,2 and its delayed and uantized version. Then, in the digital domain, the subtracted part is reestablished. Since the input swing of the flash diminishes, comparators never used can be removed. For this design, the number of comparators goes down from 3 to 8. The power reduction in the flash is therefore 40%. The flash power reduction leads to the diagram of Fig. 5(a). The subtraction node before uantization is eliminated by moving the branch back to the double integrator input, via a multiplication by ( - z - ) 2 /z -/2. Combining the result with the existing -(2 - z - ) feedback, it results -3( - z - ) - z -2, as shown in Fig. 5(b). However, since the flash output is already V out ( - z - ), its use avoids the ( - z - ) multiplication in digital domain. The result is the final scheme of Fig. 5(c). 5 bit P-path z - Q-path z -2 z -/2 Out (c) st Integrator -z - z -/2 z -/2 (-z - ) 2 V O,2 (n) z -/2 V O,2Q (n-) z - V O,2Q (n) 2-z - z -/2 Fig. 2 Topological modifications. One op-amp is eliminated Fig. 4 Five-bit uantizer with reduced input range 23

4 384 Analog Integr Circ Sig Process (20) 66: (a) st Integrator -z - (-z - ) 2 z -/2 2-z- Moving this point 5 bit z -/2 z -/2 z Input Signal Amplitude = -3 Fin = MHz Fs = 96 OSR = 8 Output without modified (b) st Integrator -z - 3(-z - )z -2 (-z - ) 2 z -/2 5 bit z -/2 z - Voltage [V] Output with modified (c) Final Architecture DAC st Integrator -z - _ DAC z -/2 (-z - ) 2 z -/2 The effectiveness of method has been verified with Matlab-Simulink. The verified swing reduction at the input of the flash decreases the number of reuired comparators from 3 to 8 but, also, relaxes the op-amp specifications, namely, linearity and slew-rate. Figure 6 shows the comparison of the output dynamic range in the second integrator with and without use of the architecture described in Fig. 4. The simulation was made by considering an input amplitude of -3 db FS and an input signal freuency very close to the Nyuist rate Op-amp power consumption z -2 Fig. 5 Topological modifications to include the uantizer with reduced input range into the two op-amps third order modulator This design points at minimum power consumption by a proper choice of number of bits, oversampling ratio and the method that reduces the dynamic range of the flash. However, since the power of op-amps critically depends on slew-rate and bandwidth, it is necessary to account for their power needs. The architecture of Fig. is not a good reference. Even if used to obtain the final scheme of Fig. 5(c), it is not practical because the single delay for the uantizer and three integrator is, from the power consumption power point of view, unaffordable. The architecture of Fig. 7 obtains suitable amplifiers output swings with proper scaling coefficients and input feedforwarding, the feedback coefficients are all eual to, and the three delays ensure suitable time for the op-amps settling. The unity capacitance of switched-capacitor schemes depends on the kt/c limit and matching reuirements. The reuested gain, slew-rate and bandwidth of the op-amps can be obtained with behavioral simulations [7]. Then, the 3 DAC V ADC ADC 5 bit z Time [μsec] Fig. 6 Output dynamic range of the second integrator /3 st Integrator /3z - -z - 2nd Integrator z - -z - 3rd Integrator 3z - -z - Fig. 7 Conventional third order modulator with delayed version integrators value of the feedback factors determines the needed gain bandwidth product (GBW). The study, with same system specifications, obtains for the schemes of Figs. 7 and 5(c) the results of Table. The reuests for slew-rate and bandwidth in the first integrator of the conventional scheme is slightly higher than what needed by the first integrator of the proposed structure. This is due to the reuested higher output swing. The specifications for the second and third integrators are relaxed because of the shaped effect of their limits. The minimum finite gain is generally low, as typical of modulators with medium resolution (less than 75 db). Likely, the slightly higher band reuest for the second op-amp of Fig. 5(c) is not very critical for power Table Behavioral specifications of the op-amps Integrator parameters Proposed Conventional st 2nd st 2nd 3rd Av (db) SR (V/ls) GBW (MHz) Swing (mv p p )

5 Analog Integr Circ Sig Process (20) 66: consumption. It is higher than the conventional counterpart, but the slew-rate is however affordable. For a uantitative assessment, we have designed a folded cascode op-amp that, changing the bias current, meets the specifications of Table. Since a change in the current varies slew-rate and bandwidth, the more demanding between GBW and slew-rate determines the needed power. Table 2 shows the results. The proposed solution obtains an overall power consumption for the op-amps that is about 5% less than the scheme with three op-amps of Fig. 7. The second op-amp of Fig. 5(c) needs more power than the first one because of its higher input loads. The powers of the op-amps of Fig. 7 diminish along the architecture, as expected. 3 Circuit implementation The switched capacitor (SC) integrated circuit used to implement Fig. 5(c) reduces to 2 the multiplication of the uantized feedback. This is obtained by augmenting by.5 the DAC uantization step, made possible by a reduced dynamic range of the flash. As shown in Fig. 8, the circuit uses two DACs controlled by V ADC and z -2 V out. Moreover, a unity capacitance obtains the addition of the two analog signals. The DACs charges are injected during / 2 to relieve the feedback factor at /. The latch strobe occurs just before the end of / to allow flash and logic to drive the DAC during / 2. The double integrator reuires the two feedbacks: the P-path and Q path of Fig. 3. Both inject during /. Since the sampling of the second integrator output can be done at / because during / 2 we have a new injection, the SC networks implementing the P-path and Q-path use two and three unity capacitors, as shown in Fig. 9. The scheme is similar to the one proposed in [8] to realize double sampling, which, however, is not used in this design. Notice that a possible mismatch in the P and Q paths splits the two poles (ideally coincident in the origin) around the unity circle. The 3% matching between capacitors causes a negligible split. The two op-amps are fully-differential folded cascode with sampled-data common mode feedback. They use different bias currents to meet the slew-rate and bandwidth reuirements. Input and integrator capacitors of the first integrator are both 80 ff to meet the noise budget reuests as specified by E.. The value includes the parasitic of wire metal lines matched with a careful layout. The total voltage noise budget with V FS = V is about 220 lv, pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi while 2kT=ðC OSRÞ gives 3.74 lv. Figure 0 shows the schematic of the voltage comparator. It is a two stage fully differential scheme with a preamplifier with gain 9.3 db, continuous time common mode feedback and regenerative latch. The response time is about 2 ns with 2 mv at input. The bias current of the ø ø 3 4 ø ø 3 4 ø 4 Cu ø 3 Table 2 Op-amps power consumption z - V CM ø 3 ø 4 Op-amps Fig. 5(c) (mw) Fig. 7 (mw) ø 3 ø 4 st nd rd.3 Total Positive Charge Injection _ Cu OPAMP Fully-Differential Folded-Cascode _ ø 4 Cu ø 3 P-path Implementation Discrete-Time CMFB V OUT Negative Charge Injection ø ø ø ø ø ø Vref z -2 Cu ø 7 Cu ø 5 Latch 2 Vref 2.5 Vref- Resistive Divider 32 V ADC DAC 3 Levels Array of Capacitors - Cu 2 2 Cu 2 2 Charge Injection TIME EVENT ø ø 2 z -2 V CM ø 5 ø 7 ø 5 ø 7 ø 7 Cu ø 5 Q-path Implementation Resistive Divider 2 DAC 2 9 Levels Array of Capacitors 2 Cu 2 2 ø 3 ø 4 ø 5 ø 6 ø 7 Vref- Fig. 8 Input switched capacitor network of the double integrator Fig. 9 Sample data implementation of the double integrator and driving phases 23

6 386 Analog Integr Circ Sig Process (20) 66: VDD OA M9 M7 OA- OA M8 M0 OA- M5 VbiasB VbiasB M6 OA M M2 M3 M4 Vref Vref- OA- - CAPACITORS DAC- VbiasA MB VSS VDD MB2 VbiasA PHASE GENERATOR OTA- OTA-2 FLASH Digital Logic M9 M7 M8 M0 CAPACITORS DAC-2 θ M5 - M6 θ M3 M4 OA- M M2 OA Fig. Chip microphotograph preamplifier is 25 la. The preamplifiers is used to moderately increase the signal and, much more important, to limit the kick back from the latch. A resistive divider with 32 eual resistances of 200 X makes two of the 5 bit DACs. The third DAC uses X resistances and two terminations of 500 X. The use of distinct resistive dividers increases the power consumption, but avoids interferences. The cost, however, is only the 5% of the total. 4 Experimental results VSS Fig. 0 Schematic diagram of the used comparator: preamplifier (top) and latch (bottom) The used technology is 0.8 lm, dual poly, 5 metal CMOS. Figure shows the die microphotograph with the main circuital blocks highlighted. The chip active area is 0.32 mm 2. Reference voltages are external and no internal buffers enforces the strength of references. However, multiple bonding for references moderates the effects of bonding inductances. The V DD is.8 V. Figure 2 shows the spectrum with 96-MHz clock and f in = 767 khz. Noise integrated over a 6 MHz band (OSR = 8) yields an SNDR of 60.7 db, corresponding to 9.8 bit. The spectrum shows second and third harmonic tones at 88 and 77 db FS, respectively. A small mismatch in the PSD [db] Points Fs = 96 MHz Input Signal dB SNDR = 60.7 db (ENoB = 9.8 bits) 2 nd HD -88 dbfs 3 rd HD -77 dbfs 0 Freuency [MHz] Fig. 2 Measured power spectrum density Signal Band 6 OSR 8 input differential signals causes the second harmonic tone. Non-linearity of the circuit gives rise to third order harmonic. The floor of the spectrum (larger than the expected kt/c noise) shows in the signal band, above 2 MHz, a first order shaped noise term. It is likely a white noise injected at the input of the double integrator, first order shaped by the architecture. The source is likely associated to the reference voltage of the DACs. The switching load and the bonding inductance cause small ringing that does not extinguish at the sampling times. The problem diminishes with lower clock freuencies, as verified by the measurements summarized in Fig. 3. The SNDR versus input 23

7 Analog Integr Circ Sig Process (20) 66: SNR [db] Ideal Response Simulation Result Measurement OSR=8: Peak SNDR=66.2dB Peak SNDR=63.5dB Peak SNDR=60.7dB Input Amplitude [db] Fig. 3 SNDR versus input signal amplitude performance of previously reported low-pass sigma delta modulators [8 2]. The FoM of reference [8] is better than this design being optimized for a 2 MHz signal band. 5 Conclusions This paper described a low-power third order sigma delta modulator that uses only two op-amps and propose a novel method to reduce the number of comparators in the uantizer (8 to achieve 5 bit of resolution). Measurements show 60.7 db peak SNDR at 96 MHz clock and signal bandwidth of 6 MHz. The total measured power consumption, eual to 6.8 mw, leads to a FoM of 0.58 pj/ conversion. Acknowledgments The authors would like to thank Ivano Galdi for valuable suggestions, National Semiconductor Corporation for chip fabrication, CONACyT Mexico project #J45732-Y, and FIRB, Italian National Program #RBAP06L4S5, for partial economical support. Table 3 Performance summary Feature This work [5] [8] [9] [0] [] [2] CMOS technology (nm) Supply voltage (V) Oversampling ratio Input signal amplitude (db) FS Signal bandwidth (MHz) Peak SNDR (db) Active area (mm 2 ) Power consumption (mw) Figure of merit (pj/conv-step) amplitude at low clock freuencies improves and the extra shaped noise disappears. The dashed and solid lines correspond to an ideal and a behavioral simulated result. The measured figures indicate a loss of about 0 db at full clock speed (f s = 96 MHz). The total power at 96-MHz clock is 6.8 mw, leading to an achieved FoM, defined by FoM ¼ P TOT 2 ENOB ð5þ 2BW (P TOT is the consumed power, ENOB the effective number of bits, and BW is signal bandwidth) is a remarkable 0.58 pj/conversion. Table 3 summarizes and compares References. Faria, G., Henriksson, J. A., Stare, E., & Talmola, P. (2006). DVB-H: Digital broadcast services to handled devices. Proceedings of the IEEE, 94(), Kornfeld, M., & May, G. (2007). DVB-H and IP datacast broadcast to handheld devices. IEEE Transactions on Broadcasting, 53(), Gomez-Baruero, D., Cardona, N., Bria, A., & Zander, J. (2007). Affordable mobile TV services in hybrid cellular and DVB-H systems. In IEEE Network, March/April 2007 (pp ). 4. Leung, B. H., & Sutarja, S. (992). Multibit sigma delta A/D converter incorporating a novel class of dynamic element matching techniues. IEEE Transactions on Circuits and Systems II, CAS-39, Bonizzoni, E., Perez, A., Maloberti, F., & Garcia-Andrade, M. (2008). Third-order RD modulator with 6-dB SNR and 6-MHz bandwidth consuming 6 mw. In Proceedings of the IEEE European solid-state circuits conference (ESSCIRC), September 2008 (pp ). 6. Norsworthy, S. R., Schreier, R., & Temes, G. C. (996). Delta sigma data converters. New York: IEEE Press. 7. Malcovati, P., Brigati, S., Francesconi, F., Maloberti, F., Cusinato, P., & Baschirotto, A. (2003). Behavioral modeling of switched-capacitor sigma delta modulators. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 50(3), Koh, J., Choi, Y., & Gomez, G. (2005). A 66 db DR.2 V.2 mw single-amplifier double-sampling 2nd-order DS ADC for WCDMA in 90 nm CMOS. In IEEE international solid-state circuits conference. Digest technical papers, February 2005 (pp. 70 7). 9. Nam, K. Y., Lee, S.-M., Su, D. K., & Wooley, B. A. (2005). A low-voltage low-power sigma delta modulator for broadband analog-to-digital conversion. IEEE Journal of Solid-State Circuits, 40(9),

8 388 Analog Integr Circ Sig Process (20) 66: Ranjbar, M., Mehrabi, A., & Oliaei, O. (2009). A low-power.92 MHz CT sigma delta modulator with 5-bit successive approximation uantizer. In IEEE custom integrated circuits conference (CICC), September 2009 (pp. 5 8).. Maghari, N., Kwon, S., & Moon, U.-K. (2009). 74 db SNDR multi-loop sturdy-mash delta sigma modulator using 35 db open-loop opamp gain. IEEE Journal of Solid-State Circuits, 44(8), Yang, W.-L., Hsieh, W.-H., & Hung, C.-C. (2009). Third-order continuous-time sigma delta modulator for bluetooth. In International symposium on VLSI design, automation and test (VLSI- DAT), April 2009 (pp ). Edoardo Bonizzoni was born in Pavia, Italy, in 977. He received the Laurea degree (summa cum laude) in Electronic Engineering from the University of Pavia, Italy, in From the same university, he received in 2006 the Ph.D. in Electronic, Computer, and Electrical Engineering. In 2002 he joined the Integrated Microsystems Laboratory of the University of Pavia as a Ph.D. candidate. During his Ph.D., he worked on development, design and testing of non-volatile memoires with particular regard to phasechange memories. From 2006 his research interests are mainly focused on the design and testing of DC DC and A/D converters. In this period he worked on single-inductor multiple-output DC DC buck regulator solutions and on both Nyuist-rate and oversampled A/D converters. Recently, his research activity includes the design of high precision amplifiers. He has authored or co-authored four papers in international journals, one book chapter, and more than 30 presentations at international conferences (with published proceedings). He is co-recipient of the IEEE ESSCIRC 2007 best paper award and of the IEEJ Analog VLSI Workshop 2007 best paper award. Aldo Peña Perez was born in Queretaro, Mexico, in 98. Received the B.Sc. degree on Electronics Engineering at the Technological Institute of Queretaro in 2004 and received the M.Sc. degree at the National Institute for Astrophysics, Optics and Electronics (INAOE), Puebla, Mexico in He is currently pursing Ph.D. at the Integrated Microsystems Laboratory of University of Pavia, Italy. His main research interests are mixed signal design, lowvoltage, low-power sigma delta data converters and analog amplifiers design. Franco Maloberti received the Laurea degree in Physics (summa cum laude) from the University of Parma, Parma, Italy, in 968, and the Doctorate Honoris Causa in Electronics from the Instituto Nacional de Astrofisica, Optica y Electronica (INAOE), Puebla, Mexico, in 996. He was the TI/J.Kilby Chair Professor at the A&M University, Texas and the Distinguished Microelectronic Chair Professor at the University of Texas at Dallas. He was a Visiting Professor at The Swiss Federal Institute of Technology (ETH- PEL), Zurich, Switzerland and at the EPFL, Lausanne, Switzerland. Presently he is Microelectronics Professor and Head of the Micro Integrated Systems Group, University of Pavia, Italy and Honorary Professor, University of Macau, China SAR. His professional expertise is in the design, analysis, and characterization of integrated circuits and analog digital applications, mainly in the areas of switched-capacitor circuits, data converters, interfaces for telecommunication and sensor systems, and CAD for analog and mixed A/D design. He has written more then 400 published papers on journals or conference proceedings, four books, and holds 30 patents. Dr. Maloberti was the recipient of the XII Pedriali Prize for his technical and scientific contributions to national industrial production, in 992. He was co-recipient of the 996 Fleming Premium, IEE, the best Paper award, ESSCIRC-2007, and the best paper award, IEEJ Analog Workshop He received the 999 IEEE CAS Society Meritorious Service Award, the 2000 IEEE CAS Society Golden Jubilee Medal, and the IEEE Millenium Medal. Dr. Maloberti was Vice-President, Region 8, of the IEEE Circuit and Systems Society ( ), Associate Editor of IEEE-Transaction on Circuit and System-II 998 and , President of the IEEE Sensor Council ( ), member of the BoG of the IEEE-CAS Society ( ) and Vice-President, Publications, of the IEEE CAS Society ( ). He is Distinguished Lecturer of the Solid State Circuit Society and Fellow of IEEE. Miguel A. Garcia-Andrade obtained the B.Sc. degree on Electronics Engineering at the Technological Institute of Mexicali in 993. Received the M.Sc. and the Ph.D. from the National Institute for Astrophysics, Optics and Electronics (INAOE), Puebla, Mexico in 997 and 200 respectively. His main interests are data converters, analog sigma delta modulators, analog filters and analog discrete time circuits applications. Doctor Miguel was recently in a postdoctoral position at the Integrated Microsystems laboratory in Pavia University Italy from March to December He is currently a full time professor at the University of Baja California in Mexicali, Mexico. 23