Very low- power Sampled- data Σ- Δ Architectures for wireline and wireless applications

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1 F. Maloberti: "Very lowpower ampleddata Δ Architectures for wireline and wireless applications"; Proc. of nd IEEE International ymposium on Communications, Control and ignal Processing, ICCP 006, Marrakech, March xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

2 Very lowpower ampleddata Architectures for Wireline and Wireless Applications Franco Maloberti Abstract The sigma delta technique is an attractive approach for many communication applications. The possible alternatives are the use of continuoustime or sampled data modulators. This paper discusses various circuit techniques that enable very low power with switched capacitor architectures. The target applications are WCDMA and ADL. Circuit implementations show that the use of techniques like use of a single opamp for highorder architectures, opamp sharing, timeinterleaved and minimiation of the opamp voltage swing obtain figure of merits in the order of fraction of pj/con.level. Index Terms igmadelta Modulation, WCDMA, ADL. I. INTRODUCTION The sigmadelta ( ) technique is more and more popular for lowpower mediumresolution telecom applications. The method was used for many years for obtaining highresolution, lowbandwidth analogtodigital converters. Now, the oversampling features are conveniently used for lowpower highbandwidth communication systems as they use modulators with a limited oversampling ratio (OR). ince the typical required resolution is not very high, the designer does not target accuracy but exploits the benefit of using analog components with limited accuracy and low voltage, enabling the integration of analog circuits with digital cores in a digital CMO process. The goal of many applications is to maintain the power consumption at a very low level while obtaining resolution and linearity. ince the resolution of a modulator depends on three factors: the oversampling ratio, the order of the modulator and the number of bits of the quantier, an optimum lowpower design must accounts for the following tradeoffs: For a given input bandwidth it is possible to enhance the resolution by increasing the sampling frequency; however, the increased request of bandwidth and slewrate in the OTAs augments the power consumption. Highorder modulators well exploit the noise shaping benefit but the use of highorders requires a large number of OTAs (and, consequently consumes power); also, highorder modulators have stability problems that are dealt with feedback branches and attenuation factors that limit the oversampling benefits. The use of multibit quantiers increases the resolution but the accuracy of the multibit used in the modulator feedback loop can be source of distortion. Department of Electronics, University of Pavia, Via Ferrata 1, Pavia Italy franco.maloberti@unipv.it ince the latter limit is not a real issue as DEM techniques transforms the mismatch between unity elements into noise, a first strategy is to use multibit architectures with a number of bits in the ADC that is the maximum allowed by the power consumption and possibly reduce the resolution. Another design direction coming from the above points is the minimiation of the number of OTA used in the architecture. The result is obtainded by sharing functions or, as will be shown shortly, by using a single opamp that obtains with a suitable passive network high order transfer functions. ince the reduction of the clock frequency by a factor k diminishes the power consumption of the OTA by k α, where α, the clock used for the operation of the circuit must be the lowest possible. Therefore, using time interleaving can increase the power effectiveness as the technique reduces the clock frequency in the paths. The power of the entire modulator becomes the one of a single path multiply by the number of paths but the NR improves more that that factor thanks to the order of shaping. An obvious strategy is to reduce the power consumption of the single components, namely the OTAs. The result is obtained by using techniques that limit the output voltage swings for benefiting the slewrate requirements and obtaining a reduces complexity of the OTA architectures. This paper discusses all the above mentioned design strategies by presenting recent research results obtained the author in the field. It is shown that, depending on the application, the choice of the best architecture obtains power figure of merits, defined as F om = P ower/( (NDR.76)/6.0 BW ), well below 1 pj/convlev benefiting both wireless and wireline communication applications. II. REDUCTION OF THE REOLUTION Notice that increasing the number of quantiation levels by.5 6 gives rise to the same number of bits obtained by doubling the sampling frequency of a secondorder modulator. The more levels increase the power of the flash by 6 but a doubled frequency would require more power in the OTAs and also in the lower resolution flash. In general, there is an optimum number of levels that minimies the power consumption that cam be a large number. However, since there is a practical maximum for an effective dynamic element matching (DEM) of the elements, the number of quantiation levels is typically not larger than 8. The above observation points toward more bits in the ADC than in the. The method proposed in [1] is effective only with a bynary as it cannot be associated with the

3 lev 1 1 ADC Trunc Res 3bit H 1 H H n 9lev 9level DEM k 1 k k n Fig. 3. Generic cheme of a Modulator. Fig. 1. econd order Modulator with reduced resolution. use of the DEM. On the contrary the approach proposed in [] obtains the result. Fig. 1 puts forward a technique that is based on the a modification of what discussed in []. A digital modulator reduces the number of bits of the ADC from 5.5 bits (48 levels) to 3 bit. The result is obtained by a first order sigmadelta modulator that truncates the number of bits to 3 and send back in feedback the residue, leading to a low resolution that can be easily driven by a feasible and affordable 9level DEM. The effect of the truncation is an additional noise, corresponding to the 3bit quantiation, shaped by a third order highpass function. The simulated output spectrum illustrated in Fig. shows that, since the third order shaped noise shows up at high frequencies, the NR is dominated by the quantiation with 48level. The peak NR occurs at 6 db F and is more than 60 db with OR =10. The estimated total power consumption with a signal bandwidth of f B = 1.95 MH (WCDMA specifications) is 1. mw with 1.3 V supply, giving rise to a FoM = 0.4 pj/convlevel. III. REDUCTION OF THE NUMBER OF OTA The order of a converter is given by the order of the loop filter used in the modulator. By turns, the order of the modulator is the number of OTA used by the architecture. It is possible to reduce the number of OTA by sharing the same element for multiple functions. ince a switched capacitor circuit uses half of the clock period to sample the input signal and the second half for the signal injection, there is half of the sampling period during which the OTA is inactive and this halfphase can be profitably used to perform a second PD [db] 0!0!40!60!80!100!10 PD of the proposed nd!order!" Modulator NR = OR=10 DR = OR=10 Rbit = 9.75 OR=10 function. However, since the power of the OTA must increase because of the increased slewing requirements, the power benefit is lower than 50% and is about 30%. A more effective way for reducing the number of OTA is the one proposed in [3]. The method can be applied to any modulator order and is an extension of the approach proposed in [4]. Fig. 3 shows a quite general architecture of modulator. It is the cascade of n analog blocks (typically integrator) followed by an ADC and n feedbacks from the digital output. Feedforward of the analog input are not used. The method uses the observation that the feedback path at the input of the ith stage can be moved to the input of the previous (i1)th stage by dividing its contribution by H i. ince the feedback from the digital output uses digitaltoanalog conversion, the signal processing is performed in the digital domain before the. If all the feedbacks are moved up to the first feedback position, the circuit of Fig. 3 becomes the one shown in Fig. 4 where the coefficient k T is k T = k 1 k H 1 k n n (1) 1 H i ince the cascade of analog blocks H 1,, H n has only one input and one output the structure can be realied with a minimum number of operational amplifiers. The transfer function of the cascade H T of a number of linear blocks is, obviously, the product of the transfer function of single blocks H 1,, H n. ince sigma delta modulators use integrators we will have p H T = (1 ) n () where, n is the number of cascaded integrator and p is the total delay around the loop. The circuit implementation of a third order scheme is based on the block diagram of Fig. 5. The filter P n is given by P 3 = 3 3 (3) that is a simple transversal filter with integer coefficients. ince the filter P n is achieved in a passive way (using!140!160!180 H 1 H H n! Frequency [H] k T Fig.. Output spectrum of the econd order Modulator of Fig. 1. Fig. 4. Modified cheme of a Modulator.

4 1 x p11 x p * * Q y ** y x p 1 Q1 1 1 y1 1 y Fig. 5. ingle OTA implementation of a third order. weighted capacitors for realiing analog delayed storing elements) the modulator uses only one OTA for the summing operation. As a result the key power consuming elements are the OTA and the quantier. The specification for WCDMA foresees a signal bandwidth 1.9 MH and NDR=60 db. A third order modulator with 1level ADC achieves the WCDMA specifications with an oversampling OR = 10. ince using the double sampling technique leads to a 19. MH clock frequency the estimated opamp unitygain frequency is 40 MH requiring a current consumption that can be as low as 0.4 ma. Assuming an ADC current budget equal to 0. ma and 0.1 ma for the digital part we obtain a power consumption of 0.85 mw at 1.V corresponding to FoM = 0. pj/convlevel. IV. T IME I NTERLEAVED T ECHNIQUE Timeinterleaved (TI) technique is an attractive solution for highspeed applications as the oversampling rate (OR) increases without speedingup the analog blocks. However, the recursive operation of modulators, which is not featuring the Nyquist rate interleaved converters, complicates the transformation of a into its equivalent TI structures. Various TI modulators proposed in the literature conceptually works well but their circuit implementations are limited by the so called quantier domino and channel mismatch effects. Quantier domino occurs when a certain quantier output is connected to another quantier input via an analog block without a delay. If the domino effect is not Fig. 7. Twopath TI secondorder sigmadelta modulator. eliminated it is possible to design timeinterleaved modulator only with two paths and double sampling. The method of reference [5] is able to achieve a 4path TI modulator without the above mentioned limits. The basic idea is to remove from three of the four paths the recursive signals that are not available for obtaining incomplete quantied outputs. A suitable signal processing recovers the missing parts in the digital domain and obtains the four sequential outputs. The second order modulator used OTAs for the main path. Moreover, incomplete signals are only additions of terms and require using one OTA for each of the three other paths. The number of bits of the flashes increases along the paths for accommodating the larger swing of incomplete signals; therefore, if the main uses bit the other s have 3, 4, 5bit respectively. In summary the architecture uses 5 OTA and 56 comparators that run at a quarter of the clock frequency while the single path counterpart uses OTA and 3 comparators running at the full speed. The 4path architecture, for signal bands in the 510 MH range, significantly reduces the power consumption and, perhaps, makes it possible oversampling ratios that the technology is not able to obtain. If, for example, the clock is 10 MH clock (that means an effective sampling rate of 480MH) and OR = 4 the NR of a bit modulator becomes 61 db for a signal band of 10 MH. The estimated ADC (a) 1st Integ. DEM nd Integ. Buffer Output ADC1 CLK Gen. (b) Fig. 1 econd order sigmadelta modulator. (a) Conventional singlepath. (b) Proposed 4path TI. Fig. 6. a) econd Order sigmadelta modulator. b) The 4path time and interleaved along with (3), () can be rewritten as architecture. p (n) = p (n 4) [4 p1 (n 4) 3 x (n 4) y (n ) y (n 3) 1.5 y (n 4) y (n i ) ] (5) i =1 The first and second integrator, shown in Fig. 1(b) directly implements (4) and (5). ince, the quantier processes p, it is necessary to estimate the (nr)th time slot outputs of p for r = 1,,3. This expanded into rconsecutive time slots is given by Therefore, the modulator outputs for time slot n, n1, n and n3 can be obtained by processing the quantier outputs in the digital domain. That is, y(n1) can be obtained from Q1 and y(n); y(n) from Q, y(n) and y(n1); y(n3) from Q3, y(n), y(n1) and y(n). 3. IMULATION REULT The proposed TI modulator is simulated using MATLAB. Fig. 8. Microphotograph of a TI interleaved modulator for ADL.

5 power consumption is 1.8 mw for the OTAs and 40 µw for the comparators, leading to less than 15 mw (including the power of the digital signal recovery) corresponding to FoM = 0.75 pj/convlevel which is a good number for such a large signal bandwidth. For lowvoltage applications and small signal bandwidth like the one required by ADL a twopath architecture is the best tradeoff. The optimum architecture is the one shown in Fig. 7 that with a 5level quantiers and a clock rate fs = 66M H obtains, thanks to the OR doubling, an OR=60 for a signal bandwidth of 1.1MH. The design discussed in [6], whose chip microphotograph is shown in Fig. 8, uses OTA s DC gain equal to 70dB and 50dB for the first and the second integrator and sampling capacitors equal to 1.6pF and 0.8pF. The experimental results show a peak NDR equal to 76 db and DR=85 db. The power consumption with supply voltage 1.8V is 5.4 ma giving a FoM = 0.47 pj/convlevel. V. OTA WING R EDUCTION The last discussed technique for reducing power consumption is the minimiation of the OTA output swing. An effective technique is the analog feedforward (AFF) that is effective in reducing the output swing of the OTAs. The use of AFF technique for all the OTAs would enable to utilie singlestage telescopic OTAs, thus reducing power consumption; however, since the method requires performing addition in the analog domain, obtaining the input of the quantier requires an additional OTA or a passive capacitive charge sharing at the comparators input. An effective alternative method [7] is to perform the required last addition in the digital domain after the main quantier as shown in Fig. 9. The method requires a second flash ADC but, thanks to the swing reduction the total number of comparators does not increase. As shown in Fig. 9 the output of the auxiliary flash that provides the digital feedforward (DFF) signal brings about quantiation noise which effect is cancelled out by the signal injection at the input of the second integrator. The processing of the K block cancels the contribution of the DFF is (4) that is a simple operation to be performed in the analog domain. E 1 D igital path 1 K Mbit E1 X a1 1 a 1 Nbit Quantier Nbit Fig. 9. pectrum of the modulator with OTA swing reduction. The number of bits of the two quantiers are, for the full ±Vref range, N=4 and M=3. However, the swing reduction greatly limits the operation range of the second OTA and requires only 5 comparators. As a result, the NR is the one of a 4bit modulator with total 75 comparators. imulation results show that the 3bit auxiliary flash reduces the swing of the second OTA down to ±0.3Vref limiting the number of quantiation level and significantly reducing the power needs. The swing at the output of the first OTA is also low: ±0.15Vref. The circuit implementation for meeting the ADL specifications uses a single poly 6metal 0.18µm CMO technology and consumes 5.1mW in the analog section and 8.7mW in the digital part. The relatively high digital power is due to a.5 V digital supply for having the operation of the logic properly. Therefore, the figure of merit FoM = 0.48 pj/convlevel could be possibly reduced by optimiing the digital design. Figure 10 shows the measured 65536points power spectrum for a 80kH, 4dBF differential sinusoidal input. The peak NR is 8.4dB and the peak NDR is 77.6dB fully complaining with the ADL specifications. R EFERENCE 1 K= a Mbit Quantier Fig. 10. cheme of the OTA swing reduction method. [1] Leslie, T.C., ingh, B.: igmadelta modulators with multibit quantising elements and singlebit feedback, IEE Proceedings G Circuits, Devices and ystems, Volume: 139, Issue: 3, June 199, Pages: [] u,., Maloberti, F.: A LowPower MultiBit Modulator in 90nm Digital CMO Without DEM, IEEE Journal of olidtate Circuits, 005, December, vol. 40, Pages: [3] Della Fiore, C., Maloberti, F.: Design of Modulators with Reduced Number of Operational Amplifiers ECCTD, Proceedings, 005. [4] Koh, J., Choi,., Gome, G.: A 66dB DR 1.V 1.mW ingleamplifier Doubleampling ndorder ADC for WCDMA in 90nm CMO, IEEEICC 005, 9.3, pp [5] Kyehin Lee, Choi,., Maloberti, F.: Domino Free 4path TimeInterleaved econd Order igmadelta Modulator, Analog Integrated Circuits and ignal Processing, Volume 43,005, Pages 536. [6] Kyehin Lee, unwoo Kwon, Maloberti, F.: A 1.1 MH ignalband Channel TimeInterleaved Multibit Modulator with 80dB NR 85dB DR and 5.4mW Power Consumption for ADL, IEEEICC 006. [7] unwoo Kwon, Maloberti, F.: A. MH ignal Band Multibit Modulator with 8dB NR and 86dB DR for ADL, IEEEICC 006.