A Current-Measurement Front-End with 160dB Dynamic Range and 7ppm INL
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1 A Current-Measurement Front-End with 160dB Dynamic Range and 7ppm INL Chung-Lun Hsu and Drew A. Hall University of California, San Diego, La Jolla, CA, USA International Solid-State Circuits Conference 1of 41
2 Motivation: Current Input Biosensors Patch Clamp Electrochemical Nanotube Nanopore International Solid-State Circuits Conference 2of 41
3 Motivation: Current Input Biosensors Patch Clamp Electrochemical Nanotube Nanopore Large signal range I s = 1 pa 1 µa Small signal with large offset ΔI s = 1 pa 1 na with I s = 1 na 1 µa A front-end with >120dB DR and >60dB linearity is required. International Solid-State Circuits Conference 3of 41
4 Conventional Current-Input AFE R-TIA C-TIA Х High noise: = 4 / Х Low DR:, = / О Low noise Х Periodic reset Х Low DR:, = / DR is limited by circuit noise and supply voltage. International Solid-State Circuits Conference 4of 41
5 Current-Input AFE Using C-TIA C-TIA with DC servo loop [JSSC, 2009] Σ w/ pulse modulation [TBioCAS, 2007] О Low noise О Continuous-time Improved DR О Low noise О High DR О Inherent digitization Good linearity with slow f s Challenge: Achieving >120dB DR and >60dB linearity International Solid-State Circuits Conference 5of 41
6 System Overview Input Current <1pA to 10µA Hourglass ADC Predictive DAC International Solid-State Circuits Conference 6of 41
7 C-TIA with Improved DR Conventional C-TIA C F saturates when i sig > limited DR International Solid-State Circuits Conference 7of 41
8 C-TIA with Improved DR Conventional C-TIA C-TIA w/ Hourglass Switch C F saturates when i sig > limited DR Keep amplifying w/o saturation increased DR International Solid-State Circuits Conference 8of 41
9 C-TIA with Hourglass Switch Goal: Increase DR, keep amplifying w/o saturation International Solid-State Circuits Conference 9of 41
10 C-TIA with Hourglass Switch Goal: Increase DR, keep amplifying w/o saturation Method: Flipping the input polarity asynchronously International Solid-State Circuits Conference 10 of 41
11 C-TIA with Hourglass Switch Two continuous-time comparators controls the hourglass switch small i sig large i sig C-TIA: low input-referred current noise Asynchronous Hourglass switching: i sig >> / The DR of a C-TIA is improved with an asynchronous Hourglass switch. International Solid-State Circuits Conference 11 of 41
12 Hourglass ADC The comparators work as a 1-bit quantizer small i sig large i sig, + International Solid-State Circuits Conference 12 of 41
13 Hourglass ADC The comparators work as a 1-bit quantizer small i =0 large i =1, + Analog Input Digital Output Quantization Error [ V R, +V R ] w.r.t. φ dir International Solid-State Circuits Conference 13 of 41
14 Hourglass ADC The comparators work as a 1-bit quantizer small i =0 large i =1, + Analog Input Digital Output Quantization Error Question: How to improve the resolution? Save e q for extending counting? International Solid-State Circuits Conference 14 of 41
15 Hourglass ADC with Noise-Shaping Eliminate the need for periodic reset International Solid-State Circuits Conference 15 of 41
16 Hourglass ADC with Noise-Shaping Digital differentiator: provides 1 st -order noise-shaping At each sampling instance: C F stores quantization error Digital output International Solid-State Circuits Conference 16 of 41
17 Hourglass ADC with Noise-Shaping Equivalent to a CCO-based (Current-Controlled Oscillator) ADC The Hourglass ADC is an asynchronous 1 st -order Σ with improved resolution. International Solid-State Circuits Conference 17 of 41
18 Ideal I sig -to-f φ,dir behavior Linearity in Hourglass ADC,, = 4 International Solid-State Circuits Conference 18 of 41
19 Ideal I sig -to-f φ,dir behavior Linearity in Hourglass ADC,, = 4 I-to-F conversion compressed with a non-ideal OPAMP,,,, The linearity of the I-to-F conversion in an Hourglass ADC is well-defined. International Solid-State Circuits Conference 19 of 41
20 Linearity Calibration in Hourglass ADC BW vs. Linearity 3.2 f 4bit 52 f 8bit International Solid-State Circuits Conference 20 of 41
21 Linearity Calibration in Hourglass ADC BW vs. Linearity This design: 3.2 f dir,max w/ linear 16x power reduction compared to the 8-b linearity case 3.2 f 4bit 52 f 8bit Power hungry amplifier Calibration Foreground characterize the I-to-F curve: BW loop and A loop Increase power efficiency using a lower BW OPAMP The foreground calibration improves the Hourglass ADC energy efficiency. International Solid-State Circuits Conference 21 of 41
22 Linearity Calibration in Hourglass ADC Use an I-DAC to measure I-to-F curve and poly-fit the non-linearity 5 th order Binary-Weighted Tri-state DAC C p & noise DEM [TCAS-I, 2008] DAC linearity International Solid-State Circuits Conference 22 of 41
23 Closed-Loop Hourglass ADC The I-DAC subtracts i s by linear extrapolating the input at f OSR i [n-1] + i / t OSR 1 st -order Predictor [DCAS, 2014] International Solid-State Circuits Conference 23 of 41
![Closed-Loop Hourglass ADC The I-DAC subtracts i s by linear extrapolating the input at f OSR i fine = i s [n] { 2i [n-1] - i [n-2] } < i s,fs /2](/docs-images/83/87659371/images/24-0.jpg "9 with OSR > 71 i [n-1] + i / t OSR = 2i [n-1] - i [n-2] 1 st -order Predictor [DCAS, 2014] International Solid-State Circuits Conference 24 of")
24 Closed-Loop Hourglass ADC The I-DAC subtracts i s by linear extrapolating the input at f OSR i fine = i s [n] { 2i [n-1] - i [n-2] } < i s,fs /2 9 with OSR > 71 i [n-1] + i / t OSR = 2i [n-1] - i [n-2] 1 st -order Predictor [DCAS, 2014] International Solid-State Circuits Conference 24 of 41
25 Input Current <1pA to 10µA System Overview Hourglass ADC О High DR О Async. quantization О Noise-shaping О High linearity Predictive DAC О Coarse prediction International Solid-State Circuits Conference 25 of 41
26 C-TIA with Hourglass Switch Dual Cascode-Compensated Amplifier [TCAS-I, 2004] Benefit: Increase f p2 by g m R o Reduce C c by 3-4 Improve power efficiency A DC = 99dB f UGB = 26MHz Pwr = 180µW International Solid-State Circuits Conference 26 of 41
27 C-TIA with Hourglass Switch Low-Leakage Switch 0.1 pf Hourglass Switch International Solid-State Circuits Conference 27 of 41
28 Continuous-Time Comparator 1.3 V 0.5 V Switched-capacitor sampling: o Sample at start-up o Store both V R and V os International Solid-State Circuits Conference 28 of 41
29 Continuous-Time Comparator 1.3 V 0.5 V Switched-capacitor sampling: o Sample at start-up o Store both V R and V os Pre-amp + dynamic amp: o Reduce propagation delay International Solid-State Circuits Conference 29 of 41
30 Feedback Loop 9-bit Binary-Weighted I-DAC 1/10 Digital blocks in FPGA [TCAS-I, 2008] [DCAS, 2014] 1/10 o Biasing: g m /I D ~ 4, thermal noise o Large size: matching & flicker noise o Cascoded tail current: R out International Solid-State Circuits Conference 30 of 41
31 Die Photo TSMC 180nm CMOS process Core area ~0.5mm 2 International Solid-State Circuits Conference 31 of 41
32 Hourglass ADC with DAC off Measurement Results The linearity of the Hourglass ADC is improved by >37. International Solid-State Circuits Conference 32 of 41
33 Hourglass ADC with DAC off Measurement Results The input-referred noise in the Hourglass ADC is < 30fA/ Hz. International Solid-State Circuits Conference 33 of 41
34 Hourglass ADC with DAC on Measurement Results Linearity Error < ±7ppm The linearity of the entire current-measurement front-end is < ±7ppm. International Solid-State Circuits Conference 34 of 41
35 Power Breakdown The total power consumption is 295 µw. International Solid-State Circuits Conference 35 of 41
36 Summary & Comparison International Solid-State Circuits Conference 36 of 41
37 Summary & Comparison DR = 160 db International Solid-State Circuits Conference 37 of 41
38 Summary & Comparison Tconv 2.5 faster International Solid-State Circuits Conference 38 of 41
39 Summary & Comparison FOM = 197 db International Solid-State Circuits Conference 39 of 41
40 Summary & Comparison International Solid-State Circuits Conference 40 of 41
41 Conclusions The current measurement front-end enables precise wide dynamic range for bio-sensing applications Key challenges: dynamic range and linearity To address this, we: Designed an Hourglass ADC to increase DR and decrease quantization noise Designed a DAC with a 1 st -order predictor to further increase DR and improve the front-end power efficiency Used DEM and linearity compensation to improve linearity Result: A current measurement front-end with 160dB DR, 7ppm INL, and 197dB FOM International Solid-State Circuits Conference 41 of 41
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