EE 435. Lecture 7: Signal Swing Measurement/Simulation of High Gain Circuits Laboratory Support

Transcription

1 EE 435 Lecture 7: Signal Swing Measurement/Simulation of High Gain Circuits Laboratory Support 1

2 Review from last lecture: Operation of Op Amp A different perspective D D DD Small signal differential half-circuit d 2 BB C L v d 2 P F I BB SS P F G 2 G M1 1 1 G 1 BB - O + O v d 2 O C L C L v d 2 P F I BB BB SS P - O + O C L F v d If the input impedance to the counterpart circuit is infinite and the quiescent values of the left and right drain voltages are the same, connecting the bias port of the quarter circuit to 0- instead of to BB will cause the signal current in the right counterpart circuit to be equal to that in the left counterpart circuit This will double the signal current steered to o+ and thus double the voltage gain! This will also eliminate the need for a CMFB circuit! 2 C L 2

3 Review from last lecture: Basic Current Mirror I IN I OUT μc W I - OX 1 2 IN GS1 T 2L1 M 1 M 2 μc W I - 2 OX 2 OUT GS2 T 2L2 I I W L W L OUT 2 1 IN 1 2 n-channel 3

4 Review from last lecture: More Advanced Current Mirrors I IN I OUT I IN I OUT I IN I OUT M 3 M 4 M 3 M 4 M 4 M 1 M 2 M 1 M 2 M 1 M 2 Cascode Current Mirror Wilson Current Mirror Modified Wilson Current Mirror 4

5 Review from last lecture: USPTO search on Jan 21, 2018 I IN I OUT DD IN OUT Current Mirror (sinking) Current Mirror (sourcing) IN OUT I IN I OUT 569 patents with current and mirror in title since patents with current and mirror in title in 2016 and 2017 Number of patents/yearis about at the 3-decade average Is there still an opportunity to contribute to the current mirror field? 5

6 Review from last lecture: Signal Swing To keep M 1 out of Triode Region DD L 1 : OUT > in -Tn XX M 2 OUT To keep M 1 out of Cutoff L 2 : > in Tn in M 1 To keep M 2 out of Triode Region L 3 : OUT - DD > XX DD -Tp XX - Tp > OUT 6

7 Review from last lecture: L 1 : Signal Swing OUT > in -Tn > L 2 : in Tn L 3 : XX - Tp > OUT CC OUT L 2 L 1 L3 CC Tn ic 7

8 Review from last lecture: Signal Swing How do the transfer characteristics relate to the signal swing? CC OUT in XX DD M 2 M 1 OUT in CC For this circuit, high gain and large output signal swing for small EB1 8

9 Review from last lecture: Signal Swing of Single-Stage Op Amp What type of signal swing is needed? OUT CC OUT CC SS CC SS CC ic ic SS Wide ic and OUT range Expected for catalog parts and overall I/O in many applications SS Narrow ic and wide OUT range Acceptable when ic is fixed OUT OUT CC CC SS CC SS CC ic ic SS Narrow OUT and wide ic range Acceptable when followed by high-gain stage SS Narrow ic and OUT range Acceptable when ic fixed and followed by high-gain stage 9

10 Signal Swing of Single-Stage Op Amp DD Constraining Equations: M 3 M 4 OUT M 1 M L 3 : L 1 : L 2 : ic To keep M 2 in Saturation: OUT OUT ic DD T2 To keep M 4 in Saturation: DD To keep M 1 in Saturation: EB4 T1 T3 EB3 XX M 5 To keep M 5 in Saturation: SS L 4 : ic T1 EB1 EB5 SS 10

11 L 2 : Signal Swing of Single-Stage Op Amp OUT DD EB4 L 3 : L 1 : L 1 : To keep M 2 in Saturation: OUT ic T2 T1 SS EB1 EB5 T2 EB3 DD T3 ic L 3 : T1 L 2 : ic To keep M 4 in Saturation: DD OUT DD To keep M 1 in Saturation: EB4 T1 T3 EB3 To keep M 5 in Saturation: L 4 : SS L 4 : ic T1 EB1 EB5 SS 11

12 Signal Swing of Single-Stage Op Amp OUT L 4 L 3 L 1 DD EB4 L 2 T1 EB1 EB5 EB3 T3 T1 Constraining Equations: SS 1 T2 1 SS DD L 3 : ic L 1 : L 2 : ic DD OUT OUT ic DD T2 EB4 T1 T3 EB3 L 4 : ic T1 EB1 EB5 SS 12

13 Signal Swing of Single-Stage Op Amp OUT L 4 L 3 L 1 DD EB4 L 2 T1 EB1 EB5 EB3 T3 T1 SS T2 DD ic 1 1 SS 13

14 Signal Swing of Single-Stage Op Amp OUT DD EB4 T1 EB1 EB5 Constraining Equations: EB3 T3 T1 OUT ic T2 SS T2 DD ic OUT DD EB4 1 1 ic DD T1 T3 EB3 SS ic T1 EB1 EB5 SS Signal swings are Important Performance Parameters!! Signal swing parameters are in practical parameter domain 14

15 Design space for single-stage op amp DD Performance Parameters in Practical Parameter Domain { EB1 EB2 EB5 P}: M 3 M 4 IN M 1 M 2 IN C L I T B2 M 5 SS OUT ic ic 1 2 A 0 λ λ 1 3 EB1 P 2 GB DDCL EB1 SR P C OUT OUT DD T1 DD ic EB3 T2 T1 T3 EB3 EB1 DD SS L EB5 SS Simple Expressions in Practical Parameter Domain 15

16 Design space for single-stage op amp DD M 3 M 4 IN M 1 M 2 IN C L I T B2 M 5 SS < ic DD T1 T3 μ C p I T OX OUT W L I I + T T ic T1 SS W1 W μ 5 n COX μn COX L1 L5 Performance Parameters in Natural Parameter Domain { W 1 /L 1 W 3 /L 3 W 5 /L 5 I T }: 3 3 W1 4μn COX L A 1 0 λ1 λ3 IT I SR T C L μ C GB OUT Complicated Expressions in Practical Parameter Domain 16 n OX 1 I T CL L1 DD OUT μ C p I T OX ic W W L 3 3 T2

17 Measurement and Simulation of Op Amps Measurement of A is challenging Because it is so large Even harder as A 0 becomes larger Offset voltage causes a problem Embed in Feedback Network to Stabilize Operating Point Stability must be managed Use time varying input to distinguish signal information from offset Must be well below first pole frequency to measure A v0 Measurement challenges often parallel simulation challenges Measurement of GB by indirect closed loop BW measurement is easy Measurement of R 0 is challenging Often very small Often challenging to avoid having measurement circuit cause output current to exceed I OMAX 17

18 Laboratory Support Problems observed in laboratory Could not see gain (signals were too small) Did not know how big of signals to expect Amplifier offset made it difficult to see output Output was real noisy (be sure to use DD and SS bypass capacitors) Gain did not agree with expected results Not operating at right Q-point Amplifier was defective Multimeter used incorrectly to measure gain (Always use scope to monitor signals!) Buffer amplifier did not have right gain oltage on protoboard pin did not agree with voltage on op amp pin Sparks fly when connected scope to circuit Red and black banana jack barrels on terminator were switched 18

19 Laboratory Support Problems observed in laboratory Signal generator was defective because monstrous noise on output Scope was not appropriately triggered Did not see output waveform from signal generator Horizontal time base setting was orders of magnitude off ertical amplifier setting was orders of magnitude off Auto-find function on scope is not your friend!!!!! Signals on scope were too noisy Bandwidth limit on scope useful for eliminating high frequency noise from measurement environment 19

20 Laboratory Support Problems observed in laboratory Ground and common were somewhat randomly interconnected Earth ground corresponds to the third prong on a standard 120 connector and is connected to a large conducting rod that is driven deeply into the surface of the earth somewhere in our around the building. The chasis (if metal) on test equipment is usually connected to the third prong on the power supply cable and the metal on the benches is usually connected independently to earth ground. The ground (black) conductor on most test equipment and the outside conductor on BNC connectors is usually connected to the third prong on the power supply cable and thus to earth ground. Circuit ground is whatever you decide to call it but designers usually connect it to earth ground. Common on dc power supplies is usually floating at low frequencies relative to earth ground as are the positive and negative terminals of the dc power supplies. Everything connected to earth ground is connected together and no ac or dc signal source can be connected between two earth ground connections!! 20

21 Laboratory Support Offset oltage Systematic Offset oltage Random Offset oltage OUT ICQ 21

22 Laboratory Support Offset oltage Systematic Offset oltage Random Offset oltage OUT ICQ Definition: The output offset voltage is the difference between the desired output and the actual output when id =0 and ic is the quiescent commonmode input voltage. OUTOFF = OUT - OUTDES Note: OUTOFF is dependent upon ICQ although this dependence is usually quite weak and often not specified 22

23 Laboratory Support OFF OUT ICQ Definition: The input-referred offset voltage is the differential dc input voltage that must be applied to obtain the desired output when ic is the quiescent common-mode input voltage. Note: OFF is usually related to the output offset voltage by the expression OUTOFF OFF= AC Note: OFF is dependent upon ICQ although this dependence is usually quite weak and often not specified 23

24 Laboratory Support OFF DD OUT - DD When differential input op amps are biased with symmetric supply voltages, it is generally assumed that the desired quiescent input voltage Is 0 and the desired quiescent output voltage is 0 so OFF is the differential Input voltage needed to make OUT =0. The input offset voltage is comprised of two parts, a systematic component and a random component OFF = OFFSYS +OSR 24

25 Laboratory Support OFF DD OUT - DD OFF = OFFSYS +OSR After fabrication there is no distinction made between OFFSYS and OSR and simply OFF is of concern OSR is determined entirely by random variations in component values from Their ideal value and will only be seen in a simulation if deviations are intentionally introduced (Monte Carlo Analysis if often used for predicting OSR ) It is expected that OFFSYS should be small (much smaller than OSR ) and it is the designer s responsibility to make this small 25

26 Laboratory Support OFF DD OUT - DD OFF = OFFSYS +OSR It is not necessary to make OFFSYS =0 although this can and is often done by making a minor tweak of matching critical parameters after the design of the op amp is almost complete OFFSYS can also be set to 0 by using a degree of freedom of the amplifier design variables but this is generally an unwise use of degrees of freedom (although some textbooks including Martin and Johns in Sec 5.1 do this!) 26

27 Laboratory Support DD M 3 M 4 D3 OUT M 1 M 2 B2 M 9 - DD (If no missmatch is introduced, will be seeing only effects of systematic offset) By symmetry, to force OUT = 0, it is necessary to have D3 =0 Making D3 =0 sets EB3 = DD + Tp and results in the use of one degree of freedom! Making EB3 so large will severely limit the voltage swing at OUT This shows why it is not wise to use a degree of freedom to make desired output voltage 0 27

28 Laboratory Support DD DD M 3 M 4 OUT M 3 M 4 OUT M 1 M 2 OS M 1 M 2 B2 M 9 B2 M 9 - DD - DD Can sweep a voltage in simulator at gate of M 1 to make OUT = OUT_DESIRED This is the systematic offset voltage Can simply add the systematic offset voltage to input throughout rest of the design phase and then remove after design is complete or tweak at end of design to eliminate systematic offset. 28

29 Laboratory Support DD M 3 M 4 OUT OFF M 1 M 2 B2 M 9 Usually OFF will change if changes in any design variables are made so re-simulation will be needed to get the correct value of OFF If OFF is not included, ac simulation of open-loop amplifier will usually not give desired results because small-signal models will be developed in simulator at incorrect operating point (often even in incorrect region of operation) - DD Alternative is to do ac simulations by embedding op amp into a FB configuration that will inherently compensate for offset voltage but issue of compensation must be addressed for amplifiers with two or more poles 29

30 End of Lecture 7 30