EE 435 Lecture 15. Two-Stage Op Amp Design
|
|
- Jeffery Heath
- 5 years ago
- Views:
Transcription
1 EE 435 Lecture 15 Two-Stage Op Amp Design
2 Review from Last Time Cascaded Amplifier Issues A A 0 p s p Single-stage amplifiers -- widely used in industry, little or no concern about compensation Two amplifier cascades 4β A 0TOT k 2β A 0TOT -- widely used in industry but compensation is essential! Three amplifier cascades - for ideally identical stages 3 8 βa 0 -- seldom used in industry but starting to appear! Four or more amplifier cascades - problems even larger than for three stages -- seldom used in industry! Note: Some amplifiers that are termed single-stage amplifiers in many books and papers are actually two-stage amplifiers and some require modest compensation. Some that are termed twostage amplifiers are actually three-stage amplifiers. These invariable have a very small gain on the first stage and a very large bandwidth. The nomenclature on this summary refers to the number of stages that have reasonably large gain. Results given above vary somewhat if a zero is present in the amplifier.
3 Review from Last Time Two-stage Cascade (continued) D FB (s) s 2 sp ~ kkp ~ 1 βa 1 0TOT A A 0 p s p p p ~ 2 - k j 4A kβ 1 2 1,2 0TOT k Case 1: Identical negative real-axis poles; must make discriminate 0, thus (maximally fast time-domain response w/o ringing) k 4β A 0TOT Im Im p 2 p 1 Re p 1F,p 2F Re
4 Review from Last Time Two-stage Cascade (continued) p p ~ 2 - k j 4A kβ 1 2 1,2 0TOT k A A 0 p s p Case 2: Maximally flat magnitude response; must make real and imaginary parts equal k 4A 0TOT kβ k 2 k 2β A 0TOT Im Im p 1F 45 o p 2 p 1 Re Re p 2F Small ringing in step response Factor of 2 reduction in pole spread
5 Review from Last Time Basic Two-Stage Cascade V DD V DD V d 2 P F P F V BB V OUT V BB P V d V 2 1 V 2 F V 1 V OUT I BIAS V SS Widely used structure for single-ended output Quarter circuits often different between first stage and second stage
6 Review from Last Time Basic Two-Stage Cascade V DD V DD V DD V BB1 V OUT P V BB VOUT1 P P V BB V OUT1 P VBB1 VOUT F V d 2 F F V d 2 F V SS V SS I BIAS Widely used structure for differential outputs Quarter circuits often different between first stage and second stage
7 Review from Last Time Two-stage op amp design It is essential to know where the poles of the op amp are located since there are some rather strict requirements about the relative location of the openloop poles when the op amp is used in a feedback configuration.
8 Review from Last Time Parasitic Capacitances in MOS Devices S G D CGSOL CGDOL CBS CGB when off CGC when on CBD S G D CGSOL CGDOL CBS CGB when off CGC when on CBD CWELLSSUB C GD C BD C GS C BS SUB C B-SUB C GS C GD C BD C BS Parasitic Capacitances added to Device Models C GS is often largest C BD and C BS often quite large with large drain/source area
9 Review from Last Time Pole approximation methods 1. Consider all shunt capacitors 2. Decompose these into two sets, those that create low frequency poles and those that create high frequency poles (large capacitors create low frequency poles and small capacitors create high frequency poles) {C L1, C Lk } and {C H1, C Hm } 3. To find the k low frequency poles, replace all independent voltage sources with ss shorts and all independent current sources with ss opens, all high-frequency capacitors with ss open circuits and, one at a time, select C Lh and determine the impedance facing it, say R Lh if all other low-frequency capacitors are replaced with ss short circuits. Then an approximation for the pole corresponding to C Lh is p Lh =-1/(R Lh C Lh ) 4. To find the m high-frequency poles, replace all independent voltage sources with ss shorts and all independent current sources with ss opens, replace all low-frequency capacitors with ss short circuits and, one at a time, select C Hh and determine the impedance facing it, say R Hh if all other high-frequency capacitors are replaced with ss open circuits. Then the approximation for the pole corresponding to C Hh is p Hh =-1/(R Hh C Hh )
10 Compensation of Basic Two-Stage Cascade P 1 P 2 P 1 P 2 V OUT V OUT V IN F 1 F 2 C 1 V IN F 1 F 2 C 2 Internally Compensated Output Compensated Modest variants of the compensation principle are often used Internally compensated creates the dominant pole on the internal node Output compensated created the dominant pole on the external node Output compensated often termed self-compensated Everything else is just details!!
11 Two-stage Architectural Choices Common Source Current Mirror Differential Input Single Ended Input Stage 1 Tail Voltage Tail Current Common Source Current Mirror Differential Input Single Ended Input Stage 2 Tail Voltage Output Compensated Tail Current Internally Compensated
12 Two-stage Architectural Choices Common Source Current Mirror 6 Differential Input Single Ended Input 2 Stage 1 Tail Voltage Tail Current 2 Common Source Current Mirror 6 Differential Input Single Ended Input 2 Stage 2 Tail Voltage Tail Current 2 Output Compensated Internally Compensated 2 Plus n-channel or p-channel on each stage Choices!!!
13 Two-stage Architectural Choices Common Source Current Mirror Differential Input Single Ended Input Stage 1 Tail Voltage Tail Current Common Source Current Mirror Differential Input Single Ended Input Stage 2 Tail Voltage Output Compensated Tail Current Internally Compensated Plus n-channel or p-channel on each stage Which of these 2304 choices can be used to build a good op amp? All of them!!
14 Two-stage Architectural Choices There are actually a few additional variants so the number of choices is larger Basic analysis of all is about the same and can be obtained from the quarter circuit of each stage A very small number of these are actually used Some rules can be established that provide guidance as to which structure may be most useful in a given application
15 Two-stage Architectural Choices Guidelines for Architectural Choices Tail current source usually used in first stage, tail voltage source in second stage Large gain usually used in first stage, smaller gain in second stage First and second stage usually use quarter circuits of opposite types (n-p or p-n) Input common mode input range of concern on first stage but output swing of first stage of reduced concern. Output range on second stage of concern. CMRR of first stage of concern but not of second stage Noise on first stage of concern but not of much concern on second stage Offset voltage usually dominated by that of the first stage
16 Two-stage Architectural Choices Common Source Current Mirror Differential Input Single Ended Input Stage 1 Tail Voltage Tail Current Common Source Current Mirror Differential Input Single Ended Input Stage 2 Tail Voltage Output Compensated Tail Current Internally Compensated Plus n-channel or p-channel on each stage Basic Two-Stage Op Amp
17 Two-stage Architectural Choices Common Source Current Mirror Differential Input Single Ended Input Stage 1 Tail Voltage Tail Current Common Source Current Mirror Differential Input Single Ended Input Stage 2 Tail Voltage Output Compensated Tail Current Internally Compensated Plus n-channel or p-channel on each stage -Cascade Two-Stage Op Amp
18 Two-stage Architectural Choices Common Source Current Mirror Differential Input Single Ended Input Stage 1 Tail Voltage Tail Current Common Source Current Mirror Differential Input Single Ended Input Stage 2 Tail Voltage Output Compensated Tail Current Internally Compensated Plus n-channel or p-channel on each stage -Cascade Two-Stage Op Amp
19 Basic Two-Stage Op Amp (compensated on first stage) V DD M 3 M 4 M 5 V OUT V IN M 1 M 2 V IN C C C L I T V B2 M 7 V B3 M 6 V SS o One of the most widely used op amp architectures o Essentially just a cascade of two common-source stages o Compensation Capacitor C C used to get wide pole separation o Pole on drain node of M 1 usually of little concern o Two poles in differential operation of amplifier usually dominate performance o C C can be internal (termed internally compensated) or external (termed externally compensated) o External compensation works but is usually not practical o No universally accepted strategy for designing this seemingly simple amplifier Pole spread k β A A 2 k makes C C unacceptably large for on-chip solutions
20 Basic Two-Stage Op Amp V DD M 3 M 4 M 5 V OUT V IN M 1 M 2 V IN C C C L I T V B2 M7 V B3 M 6 Pole spread βa 01 A 02 V SS makes C C unacceptably large Remember, pole spread strongly dependent upon β C C is usually an additional capacitor that is added Concept of Miller compensation will be used to reduce actual size of C C What about just making C C larger than what is needed? GB will degrade, power and area will increase What about providing additional compensation by making C L larger too? Poles will move together and degrade performance What about compensating for worst-case β=1 so β dependence can be ignored? Good solution for catalog parts so application space large but at a cost! Penalty in GB, power, and area sever if compensated for much different β than needed
21 Basic Two-Stage Op Amp V DD M 3 M 4 M 5 V OUT V IN M 1 M 2 V IN C C C L I T V B2 M 7 V B3 M 6 V SS Pole spread βa 01 A 02 makes C C unacceptably large Important to compensate just for what is needed, even a little more comes at a rather big penalty in performance, power, or area!!
22 Selected Commercial Op Amps
23 Selected Commercial Op Amps
24 Selected Commercial Op Amps
25 Selected Commercial Op Amps
26
27 Selected Commercial Op Amps Decompensated Op Amp
28 Selected Commercial Op Amps
29 Example: Sketch the circuit of a two-stage internally compensated op amp with a telescopic cascode first stage, single-ended output, tail current bias first stage, tail voltage bias second stage, p-channel inputs and n-channel inputs on the second stage.
30 Two-stage Architectural Choices Common Source Current Mirror Differential Input Single-Ended Input Differential Output Single-Ended Output Stage 1 Tail Voltage Bias Tail Current Bias Common Source Current Mirror Differential Input Single-Ended Input Differential Output Single-Ended Output Stage 2 Tail Voltage Bias Tail Current Bias Internally Compensated Output Compensated p-channel Input n-channel Input -Cascade Two-Stage Op Amp
31 Example Solution V DD V X4 V X5 V IN V IN V OUT V X3 C C
32 First Commercial Operational Amplifier K2-W Op Amp by Philbrickk,
33 Inventor of the Two-Stage Op Amp Robert Widlar Many say he started the field of analog IC design, considered a brilliant engineer Widlar began his career at Fairchild semiconductor, where he designed a couple of pioneering op amps. By 1966, the commercial success of his designs became apparent, and Widlar asked for a raise. He was turned down, and jumped ship to the fledgling National Semiconductor. At National he continued to turn out amazing designs, and was able to retire just before his 30th birthday in (from posted www site)
34 Inventor of the internally-compensated Op Amp Dave Fullagar (from posted www site) Designed the first internally-compensate op amp, the 741 Fullagar was 26 years old when this was designed (introduced?) Introduced in 1968 Largest selling integrated circuit ever Still in high-volume production even though over 40 years old Fullagar later started the linear design activities at Intersil Cofounder (catalyst) of Maxim
35 Analysis of Internally Compensated Two- Stage Op Amps P 1 P 2 V OUT V F F IN 1 2 C C C L Consider single-ended input-output (differential analysis only slightly different) Can t get everything but can get most of the small-signal results Since internally compensated, must have p 1 <<p 2
36 Analysis of Internally Compensated Two- Stage Op Amps For p 1 << p 2 A 0 A 0 A s = s s p p 1 2 p 1 p 2 ω BW p 1
37 Analysis of Internally Compensated Two- Stage Op Amps V 3 g MP1 V 3 g op1 V 4 g MP2 V 4 g op2 V OUT V IN g MF1 V 1 g of1 g MF2 V 2 V 1 C C g of2 V 2 C L
38 Analysis of Internally Compensated Two- Stage Op Amps g op1 g op2 V OUT V IN g MF1 V 1 g of1 g MF2 V 2 V 1 C C g of2 V 2 C L A V0 g gmf1 g of1 op1 g of2 gmf2 g op2 p 2 g of2 g C L op2 p 1 g of1 g C C op1 BW GB g p 1 gmf1g g of2 mf2 op2 C C
39 Analysis of Load Compensated Two-Stage Op Amps P 1 P 2 V OUT V F F IN 1 2 C 1 C C Can t get everything but can get most of the small-signal results
40 Analysis of Load Compensated Two-Stage Op Amps V 3 g MP1 V 3 g op1 V 4 g MP2 V 4 g op2 V OUT V IN g MF1 V 1 g of1 g MF2 V 2 V 1 C 1 g of2 V 2 C C
41 Analysis of Externally Compensated Two- Stage Op Amps g op1 g op2 V OUT V IN g MF1 V 1 g of1 V 1 C 1 g of2 V 2 g MF2 V 2 C C A V0 g gmf1 g of1 op1 g of2 gmf2 g op2 p 2 g of2 g C C op2 p 1 g of1 g C 1 op1 BW GB g of1 p 2 gmf1g g mf2 op1c C
42 Consider Again the Internally Compensated Two-Stage Op Amp P 1 P 2 V OUT V IN F 1 F 2 C C C L Recall approximate compensation requirements: where p2 kp 1 Thus, approximately, p2 3β A0TOT p 3β g of1 gmf1 g op1 C g C of2 gmf2 g 3β g op2 g of2 4β A k 2β 0TOT A 0TOT Since the pole ratio needs to be very large, C C gets very large! 1 g mf1 g g mf2 op2 of2 2 g C L C L op2 g of1 CC g op1
43 Miller Capacitance - Review C V 1 V 2 C 1EQ C 2EQ If V 2 = -AV 1 C 1EQ then for A large A CA C C 1 C C 1 2EQ 1 A Thus, a large effective capacitance can be created with a much smaller capacitor if a capacitor bridges two nodes with a large inverting gain!!
44 Miller Capacitance - Review C V 1 V 2 C 1EQ V 1 V 2 C 2EQ C 1EQ C 2EQ C 1EQ If V 2 = -AV 1 then for A large C 1 1 2EQ A A CA C C 1 C If A changes with frequency, C 1EQ and C 2EQ are no longer pure capacitors More useful for giving a concept than for accurate actual analysis because of frequency dependence of A
45 Miller Capacitance - Review The Basic Concept from capacitance multiplication Z IN =? -A C I X I X= Vx -(-AV X) sc = VXs C 1+A V X -A C thus VX 1 Z IN= IX s C 1+A So, if A is constant, input looks like a capacitor of value C EQ=C 1+A
46 Miller Capacitance - Review Z IN =? Cond -A C Ideal Capacitor VX 1 Z IN= IX s C 1+A A If A 0 s = s +1 p s +1+A 0 p G IN=s C 1+A sc s +1 p p Miller Capacitor ω Does not behave as a capacitor for ω > p
47 End of Lecture 15
EE 230 Lecture 17. Nonideal Op Amp Characteristics
EE 3 Lecture 17 Nonideal Op Amp Characteristics Quiz 11 The dc gain of this circuit was measured to be 5 and the 3dB bandwidth was measured to be 6KHz. Determine as many of the following as possible from
More informationYou will be asked to make the following statement and provide your signature on the top of your solutions.
1 EE 435 Name Exam 1 Spring 216 Instructions: The points allocated to each problem are as indicated. Note that the first and last problem are weighted more heavily than the rest of the problems. On those
More informationHomework Assignment EE 435 Homework 4 Spring 2014 Due Wednesday Feb 26
Homework Assignment EE 435 Homework 4 Spring 2014 Due Wednesday Feb 26 In the following problems, if reference to a semiconductor process is needed, assume processes with the following characteristics:
More informationChapter 12 Opertational Amplifier Circuits
1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded cascode circuit.
More informationExperiment 1: Amplifier Characterization Spring 2019
Experiment 1: Amplifier Characterization Spring 2019 Objective: The objective of this experiment is to develop methods for characterizing key properties of operational amplifiers Note: We will be using
More informationYou will be asked to make the following statement and provide your signature on the top of your solutions.
1 EE 435 Name Exam 1 Spring 2018 Instructions: The points allocated to each problem are as indicated. Note that the first and last problem are weighted more heavily than the rest of the problems. On those
More informationECEN 474/704 Lab 6: Differential Pairs
ECEN 474/704 Lab 6: Differential Pairs Objective Design, simulate and layout various differential pairs used in different types of differential amplifiers such as operational transconductance amplifiers
More informationLecture 240 Cascode Op Amps (3/28/10) Page 240-1
Lecture 240 Cascode Op Amps (3/28/10) Page 2401 LECTURE 240 CASCODE OP AMPS LECTURE ORGANIZATION Outline Lecture Organization Single Stage Cascode Op Amps Two Stage Cascode Op Amps Summary CMOS Analog
More informationEE 435. Lecture 6: Current Mirrors Signal Swing
EE 435 ecture 6: Current Mirrors Signal Swing 1 Review from last lecture: Where we are at: Basic Op Amp Design Fundamental Amplifier Design Issues Single-Stage ow Gain Op Amps Single-Stage High Gain Op
More informationSolid State Devices & Circuits. 18. Advanced Techniques
ECE 442 Solid State Devices & Circuits 18. Advanced Techniques Jose E. Schutt-Aine Electrical l&c Computer Engineering i University of Illinois jschutt@emlab.uiuc.edu 1 Darlington Configuration - Popular
More informationLecture 200 Cascode Op Amps - II (2/18/02) Page 200-1
Lecture 200 Cascode Op Amps II (2/18/02) Page 2001 LECTURE 200 CASCODE OP AMPS II (READING: GHLM 443453, AH 293309) Objective The objective of this presentation is: 1.) Develop cascode op amp architectures
More information6.776 High Speed Communication Circuits Lecture 7 High Freqeuncy, Broadband Amplifiers
6.776 High Speed Communication Circuits Lecture 7 High Freqeuncy, Broadband Amplifiers Massachusetts Institute of Technology February 24, 2005 Copyright 2005 by Hae-Seung Lee and Michael H. Perrott High
More informationLecture 110 Intro. and Characterization of the Op Amp (1/28/02) Page 110-1
Lecture 110 Intro. and Characterization of the Op Amp (1/28/02) Page 1101 LECTURE 110 INTRODUCTION AND CHARACTERIZATION OF THE OP AMP (READING: GHLM 404424, AH 243249) Objective The objective of this presentation
More informationd. Can you find intrinsic gain more easily by examining the equation for current? Explain.
EECS140 Final Spring 2017 Name SID 1. [8] In a vacuum tube, the plate (or anode) current is a function of the plate voltage (output) and the grid voltage (input). I P = k(v P + µv G ) 3/2 where µ is a
More informationMicroelectronic Circuits II. Ch 10 : Operational-Amplifier Circuits
Microelectronic Circuits II Ch 0 : Operational-Amplifier Circuits 0. The Two-stage CMOS Op Amp 0.2 The Folded-Cascode CMOS Op Amp CNU EE 0.- Operational-Amplifier Introduction - Analog ICs : operational
More informationAnalysis and Design of Analog Integrated Circuits Lecture 20. Advanced Opamp Topologies (Part II)
Analysis and Design of Analog Integrated Circuits Lecture 20 Advanced Opamp Topologies (Part II) Michael H. Perrott April 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Outline of Lecture
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
Low power OTA 1 Two-Stage, Miller Op Amp Operating in Weak Inversion Low frequency response: gm1 gm6 Av 0 g g g g A v 0 ds2 ds4 ds6 ds7 I D m, ds D nvt g g I n GB and SR: GB 1 1 n 1 2 4 6 6 7 g 2 2 m1
More informationEE 435. Lecture 7: Signal Swing Measurement/Simulation of High Gain Circuits Laboratory Support
EE 435 Lecture 7: Signal Swing Measurement/Simulation of High Gain Circuits Laboratory Support 1 Review from last lecture: Operation of Op Amp A different perspective D D DD Small signal differential half-circuit
More informationEECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design
EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design References: Analog Integrated Circuit Design by D. Johns and K. Martin and Design of Analog CMOS Integrated Circuits by B. Razavi All figures
More informationChapter 15 Goals. ac-coupled Amplifiers Example of a Three-Stage Amplifier
Chapter 15 Goals ac-coupled multistage amplifiers including voltage gain, input and output resistances, and small-signal limitations. dc-coupled multistage amplifiers. Darlington configuration and cascode
More informationOperational Amplifiers
CHAPTER 9 Operational Amplifiers Analog IC Analysis and Design 9- Chih-Cheng Hsieh Outline. General Consideration. One-Stage Op Amps / Two-Stage Op Amps 3. Gain Boosting 4. Common-Mode Feedback 5. Input
More informationIndex. Small-Signal Models, 14 saturation current, 3, 5 Transistor Cutoff Frequency, 18 transconductance, 16, 22 transit time, 10
Index A absolute value, 308 additional pole, 271 analog multiplier, 190 B BiCMOS,107 Bode plot, 266 base-emitter voltage, 16, 50 base-emitter voltages, 296 bias current, 111, 124, 133, 137, 166, 185 bipolar
More informationRail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation
Rail-To-Rail Op-Amp Design with Negative Miller Capacitance Compensation Muhaned Zaidi, Ian Grout, Abu Khari bin A ain Abstract In this paper, a two-stage op-amp design is considered using both Miller
More informationECE 442 Solid State Devices & Circuits. 15. Differential Amplifiers
ECE 442 Solid State Devices & Circuits 15. Differential Amplifiers Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 442 Jose Schutt Aine 1 Background
More informationEE 435. Lecture 16. Compensation Systematic Two-Stage Op Amp Design
EE 435 Lecture 16 Compensation Systematic Two-Stage Op Amp Design Review from last lecture Review of Basic Concepts Pole Locations and Stability Theorem: A system is stable iff all closed-loop poles lie
More informationUniversity of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1. A High Speed Operational Amplifier
University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1 A High Speed Operational Amplifier A. Halim El-Saadi, Mohammed El-Tanani, University of Michigan Abstract This paper
More informationAdvanced Operational Amplifiers
IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage
More informationAnalog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem
Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem A report Submitted to Canopus Systems Inc. Zuhail Sainudeen and Navid Yazdi Arizona State University July 2001 1. Overview
More informationEE 435. Lecture 4 Spring Fully Differential Single-Stage Amplifier Design
EE 435 Lecture 4 Spring 019 ully Differential Single-Stage Amplifier Design General Differential Analysis 5T Op Amp from simple quarter circuit Biasing with CMB circuit Common-mode and differential-mode
More informationPreliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B
Preliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B Problem 1. Consider the following circuit, where a saw-tooth voltage is applied
More informationCSE 577 Spring Insoo Kim, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Penn State University
CSE 577 Spring 2011 Basic Amplifiers and Differential Amplifier, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Penn State University Don t let the computer
More informationECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers
ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic
More informationETIN25 Analogue IC Design. Laboratory Manual Lab 2
Department of Electrical and Information Technology LTH ETIN25 Analogue IC Design Laboratory Manual Lab 2 Jonas Lindstrand Martin Liliebladh Markus Törmänen September 2011 Laboratory 2: Design and Simulation
More informationECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier
ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier Objective Design, simulate and test a two-stage operational amplifier Introduction Operational amplifiers (opamp) are essential components of
More informationBasic Circuits. Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair,
Basic Circuits Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair, CCS - Basic Circuits P. Fischer, ZITI, Uni Heidelberg, Seite 1 Reminder: Effect of Transistor Sizes Very crude classification:
More informationESE319 Introduction to Microelectronics High Frequency BJT Model & Cascode BJT Amplifier
High Frequency BJT Model & Cascode BJT Amplifier 1 Gain of 10 Amplifier Non-ideal Transistor C in R 1 V CC R 2 v s Gain starts dropping at > 1MHz. Why! Because of internal transistor capacitances that
More informationAmplifiers Frequency Response Examples
ECE 5/45 Analog IC Design We will use the following MOSFET parameters for hand-calculations and the µm CMOS models for corresponding simulations. Table : Long-channel MOSFET parameters. Parameter NMOS
More informationINF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation
INF3410 Fall 2013 Compensation content Introduction Two Stage Opamps Compensation Slew Rate Systematic Offset Advanced Current Mirrors Operational Transconductance Amplifiers Current Mirror Opamps Folded
More informationLecture 030 ECE4430 Review III (1/9/04) Page 030-1
Lecture 030 ECE4430 Review III (1/9/04) Page 0301 LECTURE 030 ECE 4430 REVIEW III (READING: GHLM Chaps. 3 and 4) Objective The objective of this presentation is: 1.) Identify the prerequisite material
More informationEE105 Fall 2015 Microelectronic Devices and Circuits
EE105 Fall 2015 Microelectronic Devices and Circuits Multi-Stage Amplifiers Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of MOS Amplifiers Common
More informationMicroelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Feedback 1 Figure 8.1 General structure of the feedback amplifier. This is a signal-flow diagram, and the quantities x represent either voltage or current signals. 2 Figure E8.1 3 Figure 8.2 Illustrating
More informationAnalog Integrated Circuits Fundamental Building Blocks
Analog Integrated Circuits Fundamental Building Blocks Basic OTA/Opamp architectures Faculty of Electronics Telecommunications and Information Technology Gabor Csipkes Bases of Electronics Department Outline
More informationProblem 1. Final Exam Spring 2018 (Reposted 11p.m. on April 30)
EE 435 Final Exam Spring 2018 (Reposted 11p.m. on April 30) Name Instructions: This is an open-book, open-notes exam. It is due in the office of the course instructor by 12:00 noon on Wednesday May 2.
More informationLab 2: Discrete BJT Op-Amps (Part I)
Lab 2: Discrete BJT Op-Amps (Part I) This is a three-week laboratory. You are required to write only one lab report for all parts of this experiment. 1.0. INTRODUCTION In this lab, we will introduce and
More information(W) 2003 Analog Integrated Electronics Assignment #2
97.477 (W) 2003 Analog Integrated Electronics Assignment #2 written by Leonard MacEachern, Ph.D. c 2003 by Leonard MacEachern. All Rights Reserved. 1 Assignment Guidelines The purpose of this assignment
More informationLecture 2: Non-Ideal Amps and Op-Amps
Lecture 2: Non-Ideal Amps and Op-Amps Prof. Ali M. Niknejad Department of EECS University of California, Berkeley Practical Op-Amps Linear Imperfections: Finite open-loop gain (A 0 < ) Finite input resistance
More informationFinal Exam Spring 2012
1 EE 435 Final Exam Spring 2012 Name Instructions: This is an open-book, open-notes, open computer exam but no collaboration either personal or electronic with anyone except the course instructor is permitted.
More informationLecture 4: Voltage References
EE6378 Power Management Circuits Lecture 4: oltage References Instructor: t Prof. Hoi Lee Mixed-Signal & Power IC Laboratory Department of Electrical Engineering The University of Texas at Dallas Introduction
More informationCHAPTER 3. Instrumentation Amplifier (IA) Background. 3.1 Introduction. 3.2 Instrumentation Amplifier Architecture and Configurations
CHAPTER 3 Instrumentation Amplifier (IA) Background 3.1 Introduction The IAs are key circuits in many sensor readout systems where, there is a need to amplify small differential signals in the presence
More informationAnalog Integrated Circuit Configurations
Analog Integrated Circuit Configurations Basic stages: differential pairs, current biasing, mirrors, etc. Approximate analysis for initial design MOSFET and Bipolar circuits Basic Current Bias Sources
More informationChapter 10 Feedback ECE 3120 Microelectronics II Dr. Suketu Naik
1 Chapter 10 Feedback Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: Active-Loaded Differential Pair 4. Ch 10: Feedback 5. Ch 11: Output
More informationAnalysis and Design of Analog Integrated Circuits Lecture 18. Key Opamp Specifications
Analysis and Design of Analog Integrated Circuits Lecture 8 Key Opamp Specifications Michael H. Perrott April 8, 0 Copyright 0 by Michael H. Perrott All rights reserved. Recall: Key Specifications of Opamps
More informationCMOS Operational-Amplifier
CMOS Operational-Amplifier 1 What will we learn in this course How to design a good OP Amp. Basic building blocks Biasing and Loading Swings and Bandwidth CH2(8) Operational Amplifier as A Black Box Copyright
More informationINF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation
INF3410 Fall 2015 Book Chapter 6: Basic Opamp Design and Compensation content Introduction Two Stage Opamps Compensation Slew Rate Systematic Offset Advanced Current Mirrors Operational Transconductance
More informationEE 435 Lecture 12. OTA circuits. Cascaded Amplifiers. -- Stability Issues. -- Two-Stage Op Amp Design
EE 435 Lecture 12 OTA circuits Cascaded Amplifiers -- Stability Issues -- Two-Stae Op Amp Desin Review from last lecture: Current Mirror Op Amp W/O CMFB DD M : 1 1 : M M meq m1 Often termed an OTA I T
More informationIOWA STATE UNIVERSITY. EE501 Project. Fully Differential Multi-Stage Op-Amp Design. Ryan Boesch 11/12/2008
IOWA STATE UNIVERSITY EE501 Project Fully Differential Multi-Stage Op-Amp Design Ryan Boesch 11/12/2008 This report documents the design, simulation, layout, and post-layout simulation of a fully differential
More informationPerformance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design
RESEARCH ARTICLE OPEN ACCESS Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design Ankush S. Patharkar*, Dr. Shirish M. Deshmukh** *(Department of Electronics and Telecommunication,
More informationCMOS Operational-Amplifier
CMOS Operational-Amplifier 1 What will we learn in this course How to design a good OP Amp. Basic building blocks Biasing and Loading Swings and Bandwidth CH2(8) Operational Amplifier as A Black Box Copyright
More informationEE 435. Lecture 4 Spring Fully Differential Single-Stage Amplifier Design
EE 435 Lecture 4 Spring 018 ully Differential Single-Stage Amplifier Design eneral Differential Analysis 5T Op Amp from simple quarter circuit Biasing with CMB circuit Common-mode and differential-mode
More informationAnalog Integrated Circuits. Lecture 7: OpampDesign
Analog Integrated Circuits Lecture 7: OpampDesign ELC 601 Fall 2013 Dr. Ahmed Nader Dr. Mohamed M. Aboudina anader@ieee.org maboudina@gmail.com Department of Electronics and Communications Engineering
More informationLecture 20: Passive Mixers
EECS 142 Lecture 20: Passive Mixers Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California, Berkeley EECS 142 Lecture 20 p.
More informationDC Coupling: General Trends
DC Coupling: General Trends * Goal: want both input and output to be centered at halfway between the positive and negative supplies (or ground, for a single supply) -- in order to have maximum possible
More informationChapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier
Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in double-ended
More informationEE 230 Lecture 19. Nonideal Op Amp Characteristics. Offset Voltage Common-mode input range Compensation
EE 230 Lecture 19 Nonideal Op Amp Characteristics Offset Voltage Common-mode input range Compensation Quiz 13 The operational amplifier has a GB of 20MHz. Determine the 3dB bandwidth of the closed-loop
More informationHigh bandwidth low power operational amplifier design and compensation techniques
Graduate Theses and Dissertations Graduate College 2009 High bandwidth low power operational amplifier design and compensation techniques Vaibhav Kumar Iowa State University Follow this and additional
More informationComparative Analysis of Compensation Techniques for improving PSRR of an OPAMP
Comparative Analysis of Compensation Techniques for improving PSRR of an OPAMP 1 Pathak Jay, 2 Sanjay Kumar M.Tech VLSI and Embedded System Design, Department of School of Electronics, KIIT University,
More informationC H A P T E R 5. Amplifier Design
C H A P T E 5 Amplifier Design The Common-Source Amplifier v 0 = r ( g mvgs )( D 0 ) A v0 = g m r ( D 0 ) Performing the analysis directly on the circuit diagram with the MOSFET model used implicitly.
More informationHomework Assignment 07
Homework Assignment 07 Question 1 (Short Takes). 2 points each unless otherwise noted. 1. A single-pole op-amp has an open-loop low-frequency gain of A = 10 5 and an open loop, 3-dB frequency of 4 Hz.
More information6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers
6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott Broadband Communication
More informationANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS
ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,
More informationA PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER
A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei ABSTRACT A novel class-ab architecture for single-stage operational amplifiers is presented. The structure
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
OTA-output buffer 1 According to the types of loads, the driving capability of the output stages differs. For switched capacitor circuits which have high impedance capacitive loads, class A output stage
More informationLecture 34: Designing amplifiers, biasing, frequency response. Context
Lecture 34: Designing amplifiers, biasing, frequency response Prof J. S. Smith Context We will figure out more of the design parameters for the amplifier we looked at in the last lecture, and then we will
More informationThe Miller Approximation. CE Frequency Response. The exact analysis is worked out on pp of H&S.
CE Frequency Response The exact analysis is worked out on pp. 639-64 of H&S. The Miller Approximation Therefore, we consider the effect of C µ on the input node only V ---------- out V s = r g π m ------------------
More informationMicroelectronic Devices and Circuits Lecture 22 - Diff-Amp Anal. III: Cascode, µa Outline Announcements DP:
6.012 Microelectronic Devices and Circuits Lecture 22 DiffAmp Anal. III: Cascode, µa741 Outline Announcements DP: Discussion of Q13, Q13' impact. Gain expressions. Review Output Stages DC Offset of an
More informationAmplifier Frequency Response, Feedback, Oscillations; Op-Amp Block Diagram and Gain-Bandwidth Product
Amplifier Frequency Response, Feedback, Oscillations; Op-Amp Block Diagram and Gain-Bandwidth Product Physics116A,12/4/06 Draft Rev. 1, 12/12/06 D. Pellett 2 Negative Feedback and Voltage Amplifier AB
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN OPAMP DESIGN AND SIMULATION Vishal Saxena OPAMP DESIGN PROJECT R 2 v out v in /2 R 1 C L v in v out V CM R L V CM C L V CM -v in /2 R 1 C L (a) (b) R 2 ECE415/EO
More informationDesign of Rail-to-Rail Op-Amp in 90nm Technology
IJSTE - International Journal of Science Technology & Engineering Volume 1 Issue 2 August 2014 ISSN(online) : 2349-784X Design of Rail-to-Rail Op-Amp in 90nm Technology P R Pournima M.Tech Electronics
More informationMicroelectronics Part 2: Basic analog CMOS circuits
GBM830 Dispositifs Médicaux Intelligents Microelectronics Part : Basic analog CMOS circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim!! http://www.cours.polymtl.ca/gbm830/! mohamad.sawan@polymtl.ca!
More informationChapter 2. Operational Amplifiers
Chapter 2. Operational Amplifiers Tong In Oh 1 2.5 Integrators and Differentiators Utilized resistors in the op-amp feedback and feed-in path Ideally independent of frequency Use of capacitors together
More informationToday s topic: frequency response. Chapter 4
Today s topic: frequency response Chapter 4 1 Small-signal analysis applies when transistors can be adequately characterized by their operating points and small linear changes about the points. The use
More informationLecture 4. Integrated Electronics
Lecture 4 Integrated Electronics P, N is the doping of silicon to carry P (+) or N (-) charge) DIODES -> Recitifier I P N If V > V ON of diode, V V ON I = R Forward bias, conducting I Von ~ 0.6 V Example:
More informationDesign of High Gain Two stage Op-Amp using 90nm Technology
Design of High Gain Two stage Op-Amp using 90nm Technology Shaik Aqeel 1, P. Krishna Deva 2, C. Mahesh Babu 3 and R.Ganesh 4 1 CVR College of Engineering/UG Student, Hyderabad, India 2 CVR College of Engineering/UG
More informationANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS
ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,
More informationI1 19u 5V R11 1MEG IDC Q7 Q2N3904 Q2N3904. Figure 3.1 A scaled down 741 op amp used in this lab
Lab 3: 74 Op amp Purpose: The purpose of this laboratory is to become familiar with a two stage operational amplifier (op amp). Students will analyze the circuit manually and compare the results with SPICE.
More informationLecture 300 Low Voltage Op Amps (3/28/10) Page 300-1
Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1 LECTURE 300 LOW VOLTAGE OP AMPS LECTURE ORGANIZATION Outline Introduction Low voltage input stages Low voltage gain stages Low voltage bias circuits
More informationBJT Circuits (MCQs of Moderate Complexity)
BJT Circuits (MCQs of Moderate Complexity) 1. The current ib through base of a silicon npn transistor is 1+0.1 cos (1000πt) ma. At 300K, the rπ in the small signal model of the transistor is i b B C r
More informationBasic Information of Operational Amplifiers
EC1254 Linear Integrated Circuits Unit I: Part - II Basic Information of Operational Amplifiers Mr. V. VAITHIANATHAN, M.Tech (PhD) Assistant Professor, ECE Department Objectives of this presentation To
More informationHomework Assignment 07
Homework Assignment 07 Question 1 (Short Takes). 2 points each unless otherwise noted. 1. A single-pole op-amp has an open-loop low-frequency gain of A = 10 5 and an open loop, 3-dB frequency of 4 Hz.
More informationECEN 474/704 Lab 7: Operational Transconductance Amplifiers
ECEN 474/704 Lab 7: Operational Transconductance Amplifiers Objective Design, simulate and layout an operational transconductance amplifier. Introduction The operational transconductance amplifier (OTA)
More informationNOVEMBER 29, 2017 COURSE PROJECT: CMOS TRANSIMPEDANCE AMPLIFIER ECG 720 ADVANCED ANALOG IC DESIGN ERIC MONAHAN
NOVEMBER 29, 2017 COURSE PROJECT: CMOS TRANSIMPEDANCE AMPLIFIER ECG 720 ADVANCED ANALOG IC DESIGN ERIC MONAHAN 1.Introduction: CMOS Transimpedance Amplifier Avalanche photodiodes (APDs) are highly sensitive,
More informationPage 1. Telecommunication Electronics ETLCE - A2 06/09/ DDC 1. Politecnico di Torino ICT School. Amplifiers
Politecnico di Torino ICT School Amplifiers Telecommunication Electronics A2 Transistor amplifiers» Bias point and circuits,» Small signal models» Gain and bandwidth» Limits of linear analysis Op Amp amplifiers
More informationDESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER
DESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER Mayank Gupta mayank@ee.ucla.edu N. V. Girish envy@ee.ucla.edu Design I. Design II. University of California, Los Angeles EE215A Term Project
More informationExperiment #7 MOSFET Dynamic Circuits II
Experiment #7 MOSFET Dynamic Circuits II Jonathan Roderick Introduction The previous experiment introduced the canonic cells for MOSFETs. The small signal model was presented and was used to discuss the
More informationSystem on a Chip. Prof. Dr. Michael Kraft
System on a Chip Prof. Dr. Michael Kraft Lecture 4: Filters Filters General Theory Continuous Time Filters Background Filters are used to separate signals in the frequency domain, e.g. remove noise, tune
More informationUNIT I BIASING OF DISCRETE BJT AND MOSFET PART A
UNIT I BIASING OF DISCRETE BJT AND MOSFET PART A 1. Why do we choose Q point at the center of the load line? 2. Name the two techniques used in the stability of the q point.explain. 3. Give the expression
More informationEE 501 Lab 4 Design of two stage op amp with miller compensation
EE 501 Lab 4 Design of two stage op amp with miller compensation Objectives: 1. Design a two stage op amp 2. Investigate how to miller compensate a two-stage operational amplifier. Tasks: 1. Build a two-stage
More informationTuesday, March 22nd, 9:15 11:00
Nonlinearity it and mismatch Tuesday, March 22nd, 9:15 11:00 Snorre Aunet (sa@ifi.uio.no) Nanoelectronics group Department of Informatics University of Oslo Last time and today, Tuesday 22nd of March:
More informationExamining a New In-Amp Architecture for Communication Satellites
Examining a New In-Amp Architecture for Communication Satellites Introduction With more than 500 conventional sensors monitoring the condition and performance of various subsystems on a medium sized spacecraft,
More informationModulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies
A. Pena Perez, V.R. Gonzalez- Diaz, and F. Maloberti, ΣΔ Modulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies, IEEE Proceeding of Latin American Symposium on Circuits and Systems, Feb.
More information