Chapter 7 PHASE LOCKED LOOP

Transcription

1 Chapter 7 PHASE LOCKED LOOP A phase-locked loop (PLL) is a closed -loop feedback system. The phase detector (PD), low-pass filter (LPF) and voltage controlled oscillator (VCO) are the main building blocks of PLL. A fixed phase relationship between reference signal and generated output signal is preserved by PLL with the help of these blocks. Thus, PLL is extensively used in applications where a steady clock signal with a variable frequency range ( to G) is required. In this chapter, detailed analysis of the main building blocks is presented using the suggested methodology for AMS circuit design. 7.1 Introduction PLL is invented in the year 1930 and today also, the basic concept of phase locking is same. PLL is an important block of many high performance communication systems and is used for carrier recovery, tracking filters, frequency and phase demodulation, frequency synthesis, clock synchronization, etc. Therefore, a great amount of research is carried out to design a robust PLL. Still, the design and implementation of PLLs continue to be challenging because design specification of PLL such as clock timing uncertainty, power consumption and area are becoming more stringent [154]. The performance parameters of PLL are greatly varied by the design specification assigned to it and usually found out with the help of mathematical model. Therefore, understanding a mathematical model is a first step in PLL design and is discussed in the next section. 105

2 7.2 Mathematical model of second order PLL A linear control system model of the phase feedback loop of PLL in the locked state consists of phase detector gain () K d, VCO gain ( Kvco /) s and loop filter gain (()) F s divided by the gain of the feedback counter modulus (N) is shown in the figure 7.1. Figure 7.1 Mathematical model of PLL system A good estimation of loop performance parameters is provided by a linear approximation analysis of mathematical model. The loop parameters such as bandwidth, lock range, settling time and stability of system are found out by the analysis. The analytical equations for a phase transfer function are written using PLL linear model and feedback theory as follows: 0 K F() s Forward loop gain: G s e s r 1 Reverse loop gain: H () s N K () d vco 0 Kd F() s Kvco Open loop gain: G().() s H s i s N 0 G() s Closed loop gain: 1()() G s H s i 0 (7.1) (7.2) (7.3) (7.4) In general loop response for PLL is calculated by equation [152], [157]. Where, 0 i d vco K 0 d Kvco F s s K K F s = the output phase in radians, i = the input phase in radians, K d (7.6) = the phase detector gain in volts per radian, K vco = the VCO gain in radians per volt-second 106

3 and F s = the loop filter transfer function. The loop characteristic of PLL is controlled by a low pass filter. The simplest LPF is a one-pole RC circuit and the first ordered transfer function of LPF is given by eq.(7.7). F s 1 (7.7) 1 src By substituting eq. ( 7.7) in eq. (7.6), the loop response for second order PLL is as follows. Kd Kvco RC Kd K RC RC 0 i 2 s s The standard transfer function second order system is given as T( s) s 2 s 2 2s n vco 2 n (7.8) (7.9) Comparing the equation (7.8) with equation (7.9) we get, The damping ratio 1 (7.10) 2 K K RC K The natural frequency d K (7.11) vco n RC Where, RC = Time constant. d vco As discussed in section 2.3.2, the improved performance is obtained by SDPLL compare to APLL. Therefore, in CP-PLL, phase detector block is replaced by PFD along with charged pump. The next section presents analysis of CP-PLL with a modified analytical model. 7.3 Mathematical model of second order CP-PLL The analytical optimum design model for CP-PLL with feedback counter modulus N=1 is shown in the figure

4 Figure 7.2 Linear model of CP-PLL The open loop gain and closed loop transfer function for second order PLL is given as equation 7.12, 7.13 respectively. I ( 1) 0 p K vco src (7.12) G ().() s H s 2 i 2 s C si pkvcor I pk (7.13) vco 0 G () 2 2 c s C si i 2 pkvcor I pkvco s 2 2 C By comparing equation (7.13) with equation (7.10), we get The natural frequency n I P K 2 C vco (7.14) The damping factor R I C K The lock time, lock range and bandwidth are calculated as follows [105]. p 2 vco (7.15) Lock time/settling time T L 2 n (7.16) Lock range wl (7.17) n Bandwidth, BW n ) / 2 1/ 2 (7.18) From the above analysis, it is observed that the choice of parameters like charge pump current ( I p ) and LPF capacitor has an impact on a loop performance of CP- PLL. The typical range of charge pump current is 100µA to 1mA [157,105]. Considering these facts, the next section presents the novel method for analysis and design method for second order PLL. 108

5 7.4 Frame work for second order PLL design As per mathematical model discussed in the section 7.2 and 7.3, the loop performance of PLL depends upon different parameters. The effects of these parameters on the over-all system characteristics must be evaluated carefully to achieve optimized circuit behavior. Therefore, the choice of acute design constraints and system characteristics are two important aspects of PLL design flow. As a result the designing of PLL for a particular application is time consuming process. A simple solution to this problem is to perform pre-design analysis using extensive modeling and simulation. The simulation environment that allows the modeling of all circuit impairments helps the designer to decide the design flow before executing the physical circuit design. In turn, it guides designer to implement robust and versatile circuit model as a whole system. The next section describes the setup for evaluation of the second order PLL designed in Matlab-Simulink environment Setup for PLL Simulation The inbuilt implementation model of analog and semi digital PLL are used in a setup for second order PLL is designed in Simulink and are shown in the figure 7.3. Figure 7.3 Setup for measurement of PLL parameters 109

6 The two analog PLL models namely baseband PLL and Linearized baseband PLL are implemented. In the set up, the inputs to analog PLL are the filter's transfer function and the sensitivity of the VCO. The charged pump PLL has input parameters such as filter's transfer function, the sensitivity of the VCO along with VCO quiescent frequency, VCO initial phase, VCO output amplitude. The automated program guides the user to find suitable value for these parameters to get the desired output. For example, the order coefficient of low pass filter is found out using the transfer function Measurement of PLL parameters The set up designed using Simulink model is simulated in Matlab on Intel processor core 2 Duo processor@2.93 G with 1.96GBRAM. The simulated results for LPF, PD and VCO were obtained in real time on scope data and are stored in workspace. Then, this data is analyzed using graphical analysis method. In a graphical analysis method, the first positive peak value and negative peak value of filter output waveform are utilized to find the damping ratio and natural frequency [152]. The figure 7.4 shows the typical filter output waveform of second order PLL in real time. With the help of automated program, the peak values i. e A1 and A2 are found out from data stored in workspace along with frequency for given time constant. damping ratio and natural Figure 7.4 Measurement of PLL parameters [152] 110

7 n 2 A A A 2 ln A1/ 2 (7.19) ln 1/ 2 T 2 (7.20) 1 2 Where, A 1= First maximum peak amplitude, A 2 = First minimum peak amplitude For the second order charged pump PLL, the simulated low pass filter waveform obtained on a scope is shown in the figure 7.5. Figure 7.5 Second order CP-PLL filter output Results and discussion for second order PLL The comparative study of these results is listed in the table 7.1. The analytical and simulated results are plotted the figure 7.6. It is observed that Baseband PLL has a smaller lock range and settling time is directly proportional to VCO sensitivity. Thus, selection of appropriate time constant is important and typically used for narrow BW applications such as GPS (0-10). In linearized PLL, the lock range decreases drastically with an increase in VCO sensitivity. The digital PLL i.e. charged pump PLL is preferred compared to analog PLL in 111

8 communication field applications due to its wide bandwidth, faster settling time and large lock range [155] [156]. In case of the second order charged pump PLL, the forward gain is directly proportional to natural frequency and the decrease in the natural frequency degrades stability of the system. This problem is addressed by simply increasing order of filter in turn by increasing order of the PLL. Therefore, third order CP-PLL designed using suggested AMS design methodology and analysis and implementation is discussed in the next section. Table 7.1 Comparative results for second order PLL PLL type Kvco Settling time Lock Range Bandwidth Baseband PLL 6.36 K/Volt Analytical 0.75 sec Simulated 0.9 sec Analytical 0.75 Simulated 0.65 Analytical 12.5 Simulated K/Volt 0.54 sec 0.60 sec K/Volt 0.45 sec 0.52 sec Charge pump PLL 100 M/Volt 250 M/volt 1.13 µsec 70.4 µsec 1.5 µsec 90.5 µsec 2.83 M 2.89 M 2.19 M 2.78 M 8.6 M 138 M 6.28 M 152 M 400 M/volt 56.1 µsec 79.3 µsec 3.17 M 2.9 M 173 M 152 M Linearized baseband PLL 10 K/Volt 30 K/Volt 4.7 msec 2.7 msec 5.2 msec 2.4 msec K K K K 70 K/Volt 1.5 msec 1.6 msec K K 112

9 Figure 7.6 Second order PLL output analysis 7.5 Analysis of third order CP-PLL Figure 7.7 Block diagram of third order CP-PLL A block diagram of third order charged pump PLL is shown in the figure 7.7[104]. The charged pump PLL works as [164] follows: The PFD produces a voltage pulse 113

10 signal proportional to phase difference between input reference signal (Ext_CLK) and output of VCO (Int_CLK) signal. The two output signals of PFD are UP and DOWN turns on the charge pump switch. The charge pump converts the logic state of a PFD into analog signals suitable for the VCO. The LPF produces a comparative stable DC voltage after filtering high frequency clutter signal and controls the output frequency of VCO. The output frequency of VCO returns as one of the inputs of PFD, comparing it with the phase of reference signal, the cyclic process finished. The phase difference will finally be zero or keep a fixed value, accordingly the VCO input stable frequency. The whole locking process is a complex non-linear process. The nonlinear equation of the system beyond second order is difficult to solve. But, when the phase difference is very small, it can be approximated to a linear model [117]. The transfer function of second order low pass filter is given by eq. (7.21) as follows 1 2 F() s R 1/ C S}/ /1/ C S (7.21) Substituting eq. (7.21) in eq. (7.6), the loop response for third PLL is written as order charged pump si pkvcor I pkvco (7.22) C1 Gc () s si i 3 pkvcor I pkvco s mrc1 2 2 C1 C2 Where, m is the capacitance ratio and usually ( m 1) C2 is much smaller C 1 thanc 1. The standard transfer function third order system is given by G () s c 2 2n s 2 m s ( m 1) s n n Comparing the eq.(7.22) with eq.(7.23), the value of frequency and capacitance ratio are found out. (7.23) the damping factor, natural For above mathematical analysis, it is clear that to design a robust model of third order charged pump PLL as a whole system, the detailed analysis of its each building block is necessary. 114

11 7.6 Phase frequency detector (PFD) The different types of phase detectors such as multiplier, EX-OR and PFD are used in PLL design. The charged pump PLL uses EX-OR or PFD as a phase detector. PLL with only PD has a limited acquisition range problem [108]. The frequency detector in addition to phase detection i. e. PFD is a sequential circuit which can detect both phase and frequency differences. It has an unlimited detection range, theoretical zero phase offset and low cost [29][165]. Therefore, modern PLLs are designed using PFD with wide frequency range Implementation model of PFD The implementation model of PFD is shown in the figure 7.8 and the state diagram representation of PFD is shown in the figure 7.9 [157]. In the state diagram of PFD, out of four states only three states are allowed and the fourth one is forbidden. This frequency referred as a tri-state PFD. The performance of PFD model is evaluated in Matlab Simulink environment. The characteristic curve of PFD is plotted with the help of obtained results and is shown in the figure Figure 7.8 Implementation model of PFD 115

12 Figure 7.9 State diagram of PFD[157] Figure 7.10 The PFD characteristics using implementation model PFD co-simulation using HDL The co-simulation of PFD model is executed by loading a VHDL code in HDL cosimulator block. The different parameters in all the blocks of the model and panes are assigned to set up HDL coder environment. Once the link is assigned, the entire set up is simulated in Modelsim simulator through Matlab. The following test bench is generated after successful synthesis of designed set up and is shown in the figure

13 Figure 7.11 PFD Test bench 117

14 7.7 Charge Pump (CP) In CP-PLL, PFD is followed by the charge pump. It is consists of two current sources in series with two switches UP and DOWN and are controlled by the PFD outputs. The implementation model of charge pump along with low pass filter is shown in the figure The parallel combination of capacitor C2 with series connected resistor R1 and C2 form a second order filter. The R2 and R3 are the resistance associated with UP and DOWN switches respectively. Figure 7.12 Implementation model of CP with second order LPF circuit Ext_CLK Int_CLK _ Ip Vc Figure 7.13 The response of charge pump with PFD and LF 118

15 As the PFD input Ext_CLK leads the input Int_CLK, the signal of Up will go high and turn on the switch to charge the LPF and the voltage Vc will increase steadily. On the other hand, if the input Ext_CLK lagged the input Int_CLK, the voltage at LPF will decrease. Furthermore, when both of them have the same frequency and phase, no net current will flow to the output node that these two current sources to match with each other, leaving filter output at a high-impedance node. The obtained response of the charge pump with PFD is shown in the figure A common problem associated with charged pump PLL is the dead zone in the charged pump. The dead zone is the amount of phase error that does not result in a charging/discharging pump current. For a three-state phase detector and charged pump, the dead zone is overcome by generating small equal width Up/Down pulses or by implementing a high speed PFD with new reset techniques when the CP -PLL is in phase lock [82]. Using these techniques, a well designed PFD and charged pump combination has a very small dead zone and hence has negligible effect on the PLL behavior and therefore, in this work zero dead zone is assumed. 7.8 Loop Filter (LF) The charge pump passive loop filter used communication applications is referred as the current source loop filter [39][116]. The choice of filter order and bandwidth along with system gain decides the overall performance of the PLL system. Therefore, the selection and design of LF is an important step in PLL design [39]. They are available in two types active and passive. The low-pass filter usually uses the passive filter in monolithic PLL, since the active filter usually has big bulk and easily introduces the environment noise [116]. The value of loop filter resistance is typically chosen based on noise and area constraints [117]. The order of LF decides the order of PLL i.e. If order of PLL is n then n is order of the loop filter. Ideally the loop filter should be of a high order. The high-order filter has poor stability but better rejection of out-band noise within the PLL,

16 whereas the low-order filter has more stable operations with moderate noise rejection capability [120]. The next important block of CP- PLL is a voltage controlled oscillator. The VCO is a heart of PLL. In recent years, the voltage controlled ring oscillator ( R-VCO) is an important component of many systems such PLL [123][162], mobile phone [151], Biotelemetry [148][149], etc as compared to LC oscillator. Therefore, designing of ring oscillator has a great impact on the overall system behavior and is discussed in the next section. 7.9 Voltage controlled oscillator (VCO) An oscillator is an integral part of many electronic systems and has many applications at wireless frequencies [151,148]. Most of the application requires that oscillators to be tunable and their output frequency is a function of a control input, usually a voltage known as VCO. An ideal VCO is a circuit whose output frequency is a linear function of its controlled voltage [144] is shown in the figure Figure 7.14 Ideal voltage controlled oscillator curve The output oscillation frequency f out is calculated as follows: Where, applied to VCO. fo is the Intercept, f f K. V (7.24) out o vco cont Kvco is the gain of VCO and V cont 120 is the controlled voltage

17 7.9.1 Topologies of VCO The different topologies for VCO on silicon ICs are broadly categorized as Ring oscillators and LC oscillators. Typically, many traditional oscillators are based on LC resonators. The resonator based LC oscillators are known for their good phase noise performance, but their tuning range is relatively small (around 10-20%)[152]. Another problem is on-chip spiral inductors occupy a lot of chip area. The addition of high-quality inductors increases the cost and the complexity of on chip inductors in CMOS process. Therefore, the resonator less VCOs has drawn significant attention for SoC solutions especially in communication trans-receiver design [55]. The resonator less VCOs (i.e. ring oscillators) can be built in any standard CMOS process. They are also compatible with digital CMOS technologies. These VCOs have a wide tuning range, high frequency stability and spectral purity. They occupy less on chip area. Therefore, the voltage controlled ring oscillator R-VCO is an attractive option while designing of PLL due to its simplicity and flexibility compare to LC oscillators for SoC solutions. The ring oscillator has no resonant tank to determine the oscillation frequency. Hence, the phase noise in ring oscillators has been relatively larger than that of resonator-based oscillators. In recent years, the design of CMOS VCOs with low phase noise and low cost is a challenging research topic and has been studied extensively [ ] [ ] Topologies of ring oscillator The Ring-oscillator has two main topologies a single-ended and differential respectively. The single ended topology is implemented with an odd number of cells whereas differential topology is implemented with an even number of cells. The block diagram of these topologies is shown in the figure The differential R- VCO has higher phase noise level than the single-ended R-VCO, when operated at 121

18 the same power, frequency and with an equal number of stages. The single-ended topology power dissipation is calculated as per transition basis and has a better phase noise for a given power dissipation. The difference in phase noise for these two topologies becomes even larger when the number of stages increases [150]. Therefore, the single ended topology is preferred in this work and discussed in the next section. (a) Differential topology (b) Single ended topology Figure 7.15 Topologies of ring oscillator Single-ended R-VCO The ring oscillator is a distributed version of the delay oscillator. A time-delay oscillator consists of an inverting amplifier with a delay element between the amplifier output and its input. The block diagram of R-VCO with delay element is shown in the figure The ring oscillator has an odd number of inverters to give the effect of a single inverting amplifier with a gain of greater than one. Figure 7.16 Block diagram of R-VCO The circuit diagram of R-VCO using variable resistor known as transmission gate is shown in the figure The inverter and variable resistor are the two important subsystems of R-VCO. The addition of more number of inverter pairs to R-VCO increases the total delay and decreases the frequency of oscillation. Therefore, the selection of number of inverter stages is required to be done carefully. 122

19 Figure 7.17 The circuit diagram of R-VCO using CMOS 7.10 Inverter circuit analysis and simulation The CMOS inverter is a basic building block of R-VCO circuit. It has quick transition time and low power dissipation. It has sharp VTC transition resembling that of an ideal inverter. This allows more CMOS gates to be integrated on an IC, resulting in much better performance CMOS inverter model Figure 7.18 CMOS inverter implementation model The CMOS inverter model is designed using LEVEL 3 SPICE model of CMOS process. The designed inverter sub-circuit is shown in the figure The effect of a change in driver to load ratio i.e. (W/L) n /(W/L) p= n p for constant value of 123

20 capacitive load and the effect of a change in capacitive load for the constant driver to load ratio on the VTC curve of inverter sub-circuit is found out. It has been observed that, as the driver to load ratio value of MOS transistor decreases the transition region shifts from left to right i.e. the inverter threshold voltage decreases with increasing aspect ratio and change in load causes a shift in the transition region. Therefore, the driver to load ratio is considered as a primary design parameter to achieve the desired VTC shape Propogation delay The average propogation delay of the inverter is the average time required for the input signal to propogate through inverter [148]. The inverter operates in the three different modes when there is a transition from low to high or high to low state of the output with respect to the input. The propogation delay i.e. low to high high to low t plh t phl and and V th threshold voltage for CMOS inverter is calculated by the equation 7.25,7.26 and 7.27 respectively. t t ph L plh t p 2 C 2V 4 V V lo a d t T N ln D D T N 1 p H L K V V V V V n O H T N O H T N D D V th V D D VT P VT N 1 n p n p (7.25) (7.26) (7.27) From equation (7.25),(7.26)and (7.27), the propogation delay depends upon load capacitance and driver to load ratio. The effect of propogation delay on output waveform of inverter due to change in load with constant driver to load ratio of one is shown in the figure 7.19 and the relative comparative results are listed in the table7.2 respectively. 124

21 6 Effect of load on Propagation Delay Voltage (V) O/p due to c_10pf O/p due to c_20pf O/p due to c_30pf O/p due to c_40pf i/p Signal Time (µsec) Figure 7.19 The effect of change in capacitive load on output waveform Table 7.2 The comparative results for propogation delay Capacitive Load Simulink Results Analytical Results % error 10 pf 22ns 24ns pf 45 ns 48 ns pf 70 ns 72 ns pf 88 ns 96 ns 8.33 The internal and external capacitance contributes to total capacitance which affect the switching speed of a CMOS transistor. For ring oscillator in most sub-micron CMOS technologies, drain-body junction capacitance C db and gate capacitance C g are major contributors for total capacitance [45]. Therefore, the calculation of total capacitance is another important step while designing of the each inverter stage. The plot of channel width Vs propogation delay with constant load is shown in the figure It has been observed that the delay asymptotically approaches a limit value of about 0.2ns. This is mainly determined by technology-specific parameters and independent of the extrinsic capacitance component. Based on simulation results, it is concluded that the obtainable delay reduction is very small beyond a point(0.95-1µm). Therefore, the increase in channel width of NMOS beyond that point will result in a waste of the valuable silicon area. 125

22 Propogation delay(ns) Effect of channel width on Propogation delay propogation delay NMOS Channel Width(µm) Figure 7.20 The propogation delay variation w.r. t. width Inverter sub-system In the ring oscillator, the output of every inverter of a ring oscillator changes after a finite amount of time, once the input has changed. Thus, adding more no of inverters to the chain increases the total gate delay, in turn reducing the frequency of oscillation. In this work,three identical inverter models are connected in series to form an inverter sub-system for the ring oscillator as shown in the figure It is observed that the delay of 70ns is introduced by each stage due to total capacitance. Figure 7.21 The designed ring oscillator with inverter sub-system 126

23 7.11 Design and analysis of ring oscillator The oscillation period of ring oscillator is the sum of propogation delay due to all inverter stages. The frequency of oscillation is given by[44] fosc 1 (7.28) 2. N. tp Where, N = No. of the stages, tp = the delay of each inverter stage. The frequency of oscillations can be varied by changing propogation delay i.e by varying delay elements. The delay tp of each stage is approximated by eq.(7.29). Substituting eq.(7.29) in eq. (7.28) we get eq.(7.30), C(1) GM Rv tp GM 1 GM fosc 1 2. N.() Rv C 2. N. C.(1) GM Rv G M (7.29) (7.30) Where, C is a parasitic capacitor of MOSFET, GM is a transconductance and the equivalent resistance Rv. The oscillation frequency mainly depends upon transconductance, equivalent resistance and capacitance. But, the increase the capacitive load increases the delay time in turn reduces the oscillation frequency. The relative comparative results for the different capacitive load is shown in the table 7.3. Table 7.3 The comparative results for oscillation frequency of ring oscillator Capacitive Load Analytical Frequency Simulated Frequency Percentage error 1 pf 33 M 35 M pf 333 M 348 M pf 450 M 470 MHZ pf 900 M 930 M 3.2 The parasitic capacitance C and transconductance GM of MOSFET are constant. Thus, in this work oscillation frequency is varied by using variable resistance. The 127

24 small area and less stages are achievable by realizing variable resistance with PMOS or NMOS [147]. The next section presents the design of variable resistor Design and analysis of transmission gate The voltage transmission is a nonlinear process in transmission gate. Therefore, it is essential to define the large-signal equivalent resistance of a transmission gate. However, a simple analytical model for the variable resistor is possible to develop and is shown in the figure The variable resistance Rv acting as a voltagecontrolled switch changes its value as per the gate voltage [142]. Figure 7.22 CMOS based variable resistor The effective resistance Rv is given as 1 For 1 1 e. VDD V V 1 e. V V CTRL TH DD TH Rv G M 0.3 VCTRL V TH 1 For 1 e. V DD V TH V CTRL, 1 Rv GM.ln 1 VDD e. VCTRL V TH, (7.31) (7.32) Where, VTH is the threshold voltage, VDD is DC supply voltage and V CTRL is the gate control voltage. The sub-system for the transmission gate in CMOS 0.18um process is shown in the figure

25 Figure 7.23 The variable resistance sub-system Resitance (K) The Equivalent Gate Resistance 9 8 Bn/Bp= Bn/Bp= Bn/Bp= Gate control voltage(v) Figure 7.24 The variation in eq. resistance for the various gate voltages The effect of variation in driver to load ratio on equivalent gate resistance is shown in the figure It has been observed that the resistance offered by transmission gate decreases as the control voltage increases. Hence, proper selection of variable resistance is mandatory to achieve a wide-range tuning range for R-VCO Design and analysis of R-VCO The R-VCO system is a combination of the three inverter sub-system and the variable 129

26 resistor sub-system. The R-VCO is implemented in Level 3,0.18um CMOS process as shown in the figure Figure 7.25 The designed R-VCO using CMOS transistors sub-system With reference to equation 7.30, assuming the frequency can be approximated as [143] When fosc Rv is large and GM Rv >>1. G M 2. N. C 1 fosc 2. N. C. Rv Rv is very small, i.e. ON state, the (7.33) (7.34) Substituting equation (7.31) in equation (7.34) we get, 1 fosc 1 1 e. V DD 2. N. C. G M 0.3 VCTRL V TH (7.35) Result and discussion R-VCO As per discussion in section 7.11 and 7.12, the sub-system design for inverter and variable resistance are important steps in the designing voltage controlled ring oscillator. The behavior of these circuits depends upon the driver to load ratio. Therefore, The selection of the driver to load ratio of these sub-systems is needed to be done carefully. 130

27 Frequency(M) Characteristics curve of R-VCO Bn/Bp=0.5 Bn/Bp=1 Bn/Bp=2 Bn/Bp= Control Voltage(V) Figure 7.26 The effect on R-VCO Characteristics with variable resistance The VCO characteristic curve is plotted for different values of driver to load ratio of the variable resistance for constant driver to load ratio of one for the inverter subsystem and different values of driver to load of the inverter sub-system for constant driver to load ratio of two for variable resistance are shown in the figure 7.26 and 7.27 respectively. Frequency(M) Characteristics curve of R-VCO Control Voltage(V) Bn/Bp=0.5 Bn/Bp=1 Bn/Bp=2 Figure 7.27 The effect on R-VCO characteristics with variation in inverter 131

28 Table 7.4 Spaces The W/L ratios of the MOS transistors W n () m L n () m W p () m L p () m CMOS Inverter Transmission Gate Figure 7.28 The obtained phase noise plot for R-VCO The power supply VDD is fixed to 3.3V and controlled voltage range is varied from 0-3.3V. The obtained values of width and length are shown in the table 7.4. The obtained phase noise plot is shown in the figure The phase noise of -80 dbc/ is obtained at 1M offset frequency. The obtained output frequency of VCO is shown in the figure Voltage(V) Time (sec) Figure 7.29 The obtained output at 2 V control voltage with designed R-VCO 132

29 Table 7.5 The obtained frequency for R- VCO for variation of control voltage Control Voltage (in Volts) Frequency of Oscillation (in M) The highest tuning range i.e. 8M -454M for control voltage 0-3.3V is achieved with driver to load ratio of two for variable resistance and driver to load ratio value of one for inverter. The obtained output frequency of oscillation for the different input control voltage is tabulated in the table 7.5. The results obtained by analytical equations and simulation model were compared with behavioral model. The next section presents the implementation of the behavioral model using suggested AMS circuit design methodology Behavioral model and test bench results for R- VCO The behavioral model for the R VCO is designed to establish a link between Matlab Simulink and HDL coder. The designed behavioral model for the R-VCO consists of a three inverter stage as shown in the figure The simulated output waveform is captured on scope and is shown in the figure

30 Figure 7.30 Behavioral model of R-VCO Voltage (V) Time (sec) Figure 7.31 The obtained output with behavioral model The resulted files after linking Simulink model to HDL coder are listed below. Ringt _tb.vhd: VHDL test bench code and generated test and output data. Ringt_ tb_compile.do: This script compiles and loads both the entity to be tested and the test bench code (tb.vhd). The generated test bench and script files reflect as invt_tb, invt_tb_compile.do, invt_tb_sim.do respectively. The automated generated VHDL code result is compared with analytical equations, implementation model and behavioral model is shown in table 7.6. The comparative plot of obtained results is shown in the figure Table 7.6 Comparative results for R-VCO Corresponding Analytical Simulated Frequency (M) Control Propogation Frequency Implementation Behavioral Test Voltage(V) delay (ns) (M) Model Model Bench

31 Frequency (M) Figure 7.32 Characteristic curve of R-VCO Control Voltage (V) Analytical Behavioral Test Bench Implementation The comparative study of VCO characteristics Table 7.7 The comparative study for designed R-VCO Ref. [141] [143] [145] [146] This Tunning Range(M) Power mw Phase Noise@ -108@ -88@ Offset 1M 1M 1M 1M Technology (µm) No of delay cells Area 84*50 60* * 1.44 The performance of designed R-VCO is summarized in table 7.7 along with the reported results of other designs from the last decade Summary In this chapter, the effect of the different parameters on performance of second order PLL is discussed using a novel graphical analysis method. The analysis and design of 135

32 third order charged pump PLL s sub- blocks are done using the methodology for AMS circuit. The result obtained from implementation model is compared with an auto generated test bench by co-simulation of PFD. The effectiveness of the AMS design methodology is successfully tested for PFD and R-VCO. The phase noise performance of the proposed ring oscillator is found to be better than the performance of any previously published design. In the next chapter, the performance analysis of designed third order charged pump PLL along with its application is presented. 136