Lecture 11. Phase Locked Loop (PLL): Appendix C. EE4900/EE6720 Digital Communications

Transcription

1 EE4900/EE6720: Digital Communications 1 Lecture 11 Phase Locked Loop (PLL): Appendix C

2 Block Diagrams of Communication System Digital Communication System 2 Informatio n (sound, video, text, data, ) Transducer & A/D Converter Source Encoder Channel Encoder Modulator Tx RF System Channel Output Signal D/A Converter and/or output transducer Source Decoder Channel Decoder Demodulator Rx RF System

3 PLL: Core Component for the Receiver Example: AM Radio 3 Transmitter Receiver Received Signal Mixer (Multiplier) Low Pass Filter Remove DC Demodulated Signal Local Oscillator Same Frequency As the Carrier Signal Phase Locked Loop (PLL) is used to get the precise frequency

4 PLL: Core Component for the Receiver Super Heterodyne Receiver 4 Phase Locked Loop (PLL) is used to get the precise frequency

5 PLL: Core Component for the Receiver Zero IF or Direct Conversion Receiver 5 Phase Locked Loop (PLL) is used to get the precise frequency

6 Continuous-time PLL Basics PLL a device that tracks phase and frequency of a sinusoid signal and provides the stable reference signal PLL has three main components: Phase Detector (PD), Loop Filter (LF), and Voltage Controlled Oscillator (VCO) Continuous-time PLL 6 Received Carrier Signal PD Loop Filter VCO Output of VCO=Reference Signal

7 Continuous-time PLL Basics Stable Frequency: once the VCO phase is locked or synchronized (i.e. phase difference is constant) to the received signal, its frequency is said to be locked Consider two sinusoids (points) around the unit circle If the phase difference between the two is constant, then they move around at the same rate (same frequency ω) Ref: Phase Locked Loop PLL Tutorial Unit Circle ω Time-Domain ω=2πf 7 Phase Difference

8 Continuous-time PLL Basics Stable Frequency: once the VCO phase is locked or synchronized (phase difference is constant) to the received signal, its frequency is locked Stable Phase: minimize the phase error between the received signal phase θ t and the VCO signal phase θ(t) Phase Detector (PD): finds the phase difference (phase error), θ e t = θ t θ(t) Loop Filter (LF):filters out phase error and produces control voltage v(t) Voltage Controlled Oscillator (VCO): generates the reference signal Continuous-time PLL 8 Received Carrier Signal PD Loop Filter VCO Reference Signal

9 Continuous-time PLL Basics Ideal Operation Loop adjusts the control voltage v(t) of VCO until phase error, θ t θ t ~0 1) θ t > θ t :VCO output lags the carrier signal Loop filter will generate v(t) > 0 so that θ t increases 2) θ t < θ t : VCO output leads the carrier signal Loop filter will generate v(t) < 0 so that θ t decreases 9 Phase Error Function Linear Region Phase Error

10 Continuous-time PLL Basics Phase Equivalent Representation Loop adjusts control voltage of VCO until phase error ~ 0 10 Received Signal Phase Phase Detector Loop Filter Reference Signal Phase VCO

11 Continuous-time PLL Basics Time and Frequency Domain Representation Loop adjusts control voltage of VCO until phase error ~ 0 Loop Transfer Function: H a s = Θ(s) Θ(s) = Phase Error Transfer Function: Time-Domain G a s = Θ e(s) Θ(s) = k 0k p F(s) s + k 0 k p F(s) s s + k 0 k p F(s) 11 Frequency-Domain (Laplace T.)

12 Phase Error Transfer Function Phase Error Transfer Function: G a s = Θ e(s) Θ(s) = s s + k 0 k p F(s) We need to come up with F(s) or the Loop Filter 12 Loop Filter is the key component Two cases: Phase Offset (step input) Multipath Delay Frequency Offset (ramp input) L.O. Frequency Instability

13 Loop Filter, F(s) Sections C.1.2, C.1.3, C.1.4 Phase Lock 13 Frequency Lock Proportional- Plus-Integrator The best Loop Filter is Proportional-Plus-Integrator

14 Loop Filter, F(s) Sections C.1.2, C.1.3, C Loop Filter has p poles, the PLL has p+1 poles

15 Loop Filter Characteristics 1) Acquisition Time or Locking Time: time required to make phase error=0 T LOCK = T FL + T PL ; T FL = 4 Δf2 B n 3 T FL = 1. 3 B n Frequency Offset Noise Bandwidth (or PLL Bandwidth) 15 Pull-in Range: Δf pull in = 2π 2ζ B n 2) Tracking: Q: How well can the PLL track the carrier signal? A: Phase error variance 2 σ θe Damping Factor (Ringing) = N OB n P in ; P in =Received sig. power with AWGN with noise = N o /2 Trade-off: Fast Acquisition and Good Tracking

16 Continuous-time PLL with Proportional-Plus-Integrator LF 16 Loop Transfer Function Time-Domain H a s = 2ζω ns + ω n 2 s 2 + 2ζω n s + ω n 2 Loop Constants k 0 k p k 1 = 2ζω n ; k 0 k p k 2 = ω n 2 Selection of Damping Factor ζ Frequency-Domain (Laplace T.)

17 Discrete-time PLL with Proportional-Plus-Integrator LF Loop Transfer Function Time-Domain 17 Eq. C.51 Loop Constants Eq. C.61 Direct Digital Synthesizer (DDS) Frequency-Domain (Z-Transform)

18 Discrete-time PLL Example (Fig. C.2.4) Goal: Track Complex Exponential Follow Dr. Rice s PLL Exercise Time-domain 18 Phase Phase Error Design first-order PLL and second-order PLL

19 Assignment 7 [10] Simulate 1 st order and 2 nd order discrete-time PLLs [10] 19 Submit the following: 1) Simulink Model 2) Phase error plots 3) Time-domain plots