A 6-BIT SUB-RANGING HIGH SPEED FLASH ANALOG TO DIGITAL CONVERTER WITH DIGITAL SPEED AND POWER CONTROL

Transcription

1 A 6-BIT SUB-RANGING HIGH SPEED FLASH ANALOG TO DIGITAL CONVERTER WITH DIGITAL SPEED AND POWER CONTROL A Thesis Presented in Partial Fulfillment of the Requirements for The Degree Master of Science in the Graduate School of The Ohio State University By Balasubramanian Sivakumar, B.E. * * * * * The Ohio State University 2009 Master s Examination Committee: Approved by Professor Mohammed Ismail, Advisor Professor Steven Bibyk Graduate Program in Electrical and Computer Engineering

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3 ABSTRACT As communications and data processing equipments are being pushed to higher speeds and into the digital domain, it becomes necessary that they are complemented with the fastest analog to digital converters (ADC) possible. As device sizes scale down, more transistors can be fabricated in the same area, but also this requires a higher amount of heat dissipation in a smaller area. Also a lot of emphasis is being laid on designers to design products that consume less power as a step towards green computing and prevention of global warming. A result of all these needs is the requirement for a high speed, low power, high performance ADC. This requirement can be satisfied only with innovation and new techniques being developed. In this thesis, a high speed flash sub-ranging ADC with digital speed and power control is developed. Two main innovations, current pumping and voltage pulling are developed and are applied to the components of the ADC. It is shown that these two techniques double the speed of the components. Further, it is shown how the speed and power of the components can be controlled digitally in addition to these techniques. This can be applied for the devices in case of stand-by and action modes. Further, digital control of the speed and power of the devices can be extended to be an option of the user. The ADC has been developed targeting UWB applications and for memories, it is designed to perform with 6 bits resolution, at 2.5 Gsps at a single stage and targeting 2 stage time interleaving to work at 5 Gsps with 2 speed and power settings but extend able ii

4 to N bits and N power and speed settings. Simulations are shown to support the theories developed. The whole ADC has been developed using the 0.35u CMOS technology at transistor level implementation and with a 1.8 V supply to be compatible with 0.18u CMOS technology. The chip is designed targeting cheap and widely available fabrication, it uses a single well process, 4 layers of metal and single layer of poly and relies on CMOS technology. iii

5 This work is dedicated to my parents who gifted me my soul, prosperity and life and to my friends who gave me support, shelter and warmth during difficulties. iv

6 ACKNOWLEDGEMENTS I would like to convey my heart felt thanks to my parents. None of my work would have been possible without the love and support my parents showered on me. It is because of them that I am what I am today. No other son could have had better parents than me. I would like to thank my professor and advisor Professor Mohammed Ismail for allowing me to be a part of his team and the constant support and advice he gave me. I owe him a lot for his precious time he spent with me and for being with me at all times. I would like to express my gratitude towards Professor Steven Bibyk for having agreed to be a member of my thesis examination committee despite his extremely busy schedules. I would also like to thank Professor Patrick Roblin, P.V.Ramakrishna for all their technical support. I would like to express my gratitude to my friends, my life. They provided me with support when I was falling, they gave me direction when I was lost and stood by me when I needed them. I would like to express my gratitude to some of my close friends Athreya, Harsha, Shankar and John Hu who gave me technical support; to MRK, Vijay, Prashanth, Hari for having helped me overcome times of need; to Karthikeyan, Nandakumar, Awad for their moral support. I cannot write enough to thank them and I cannot put down everyone's names who have helped me. v

7 VITA August 15, Born Chennai, India June, Bachelor of Engineering in Electronics and Communication Engineering, Anna University, Chennai, India September, 2007 June, Member, Analog VLSI Lab, The Ohio State University, Columbus, Ohio June, 2008 September, Intern, Integrates Systems Lab, Anna University, Chennai September 2008 present...member, Analog VLSI Lab, The Ohio State University, Columbus, Ohio FIELDS OF STUDY Major Field: Electrical and Computer Engineering Studies in Analog VLSI Design: Professor Mohammed Ismail vi

8 TABLE OF CONTENTS TITLE PAGE No. Abstract ii Acknowledgments... v Vita.. vi List of Figures. xiii CHAPTERS TITLE PAGE No. 1. INTRODUCTION 1.1 NEED FOR ANALOG TO DIGITAL CONVERTERS TYPES OF ANALOG TO DIGITAL CONVERTERS Low Speed, High Resolution, Low Power ADC High Speed, Low resolution, High Power ADC Low Speed High Resolution Low Power Converters Successive Approximation Register Converters Sigma Delta Converters High Speed, Low resolution, high power ADCs Thesis Organisation A THREE BIT FLASH CONVERTER EXAMPLE 2.1 FUNCTION OF FLASH CONVERTER Analog Input is sampled. 16 vii

9 2.1.2 Resistive Ladder Network Comparator and latch Thermometer to Binary Code Conversion FAT Tree Encoder Advantages and limitations of flash converter SUB-RANGED CONVERTER CONCLUSION PARAMETRICS OF ANALOG TO DIGITAL CONVERTERS 3.1 ADC TESTING STATIC PARAMETERS Over Sampling Ratio ADC Response Resolution Analog Input Range Offset Full scale Error Gain Error Differential Non-Linearity Error Integral Non-Linearity Power Dissipation Dynamic Parameters Analog Input Bandwidth Input Impedance Equivalent input referred noise 42 viii

10 3.3.4 Signal to Noise Ratio Signal to Noise and Distortion Ratio Dynamic Range ENOB Harmonic Distortion Spurious Free Dynamic Range Effective Resolution Bandwidth Conclusion THE ANALOG COMPONENTS 4.1 ANALOG COMPONENTS OF ADC Sample and Hold Resistance Ladder Comparators and Latches Current Pumps Theory of Current Pumps Application of Current Pumps to Comparators Latches A brief discussion of results Future works on current pumps Voltage Pulling Theory of Voltage Pulling Application to Sample and Hold Charge injection Cancellation Conclusion. 89 ix

11 5. FLASH DIGITAL COMPONENTS 5. 1 DIGITAL BLOCKS OF THE ADC Bubble Corrector and Thermometer to Gray code converter FAT Tree Encoder Conclusion PIPELINE COMPONENTS OF CONVERTER 6.1 MODIFIED SUB RANGING Analog multiplexer Delays Conclusion DISCUSSION OF RESULTS 7.1 COMPARATOR AND LATCHES COMPARATORS AND LATCHES QUANTISATION OF CURRENT PUMPING TECHNIQUE SWITCHING TRANSISTOR SAMPLE AND HOLD AMPLIFIER OSR ANALOG INPUT RANGE. 132 x

12 7.5 RESOLUTION OF THE CONVERTER POWER CONSUMED SIGNAL TO NOISE RATIO SFDR DNL AND INL TESTING Differential Non Linearity Integral Non Linearity Conclusion LAYOUTS 8.1 LAYOUT ISSUES Differential amplifier Extraction of parasitic capacitances Comparator and latch Sample and hold amplifier Conclusion CONCLUSION AND FUTURE DEVELOPMENTS 9.1 CONCLUSION FUTURE DEVELOPMENTS Internal reference voltage setting Sub-ranging Multiple speed settings Latency Layouts.159 xi

13 9.2.6 Time Interleaving Technology APPENDIX A..161 References.175 xii

14 LIST OF FIGURES FIGURE No. TITLE PAGE No. 1.1 Binary search path the SAR can take up The search tree of the SAR ADC showing the various paths Noise shaping taking place in a sigma-delta ADC Closer view of band of interest and noise in region An oversimplified architecture diagram of a sigma-delta Converter A conceptual Flash Converter Operation Sample and Hold operation performed on a sine wave Top level view of function of comparator and latches Conversion of thermometer code to Gray code Conversion of Gray codes to digital output Block level diagram of a Sub-ranging Flash Converter Noise power in signal band and reduction in noise by Oversampling Typical ADC response to a ramp voltage Offset error seen in the response of the converter Response of typical ADC showing gain error Response of ADC showing DNL error Response of ADC with INL errors Computations of SNR, SFDR for a ADC from [6] Conceptual diagram of analog components of an ADC...48 xiii

15 FIGURE No. TITLE PAGE No. 4.2 A simple model of a Sample and Hold Operation Reference Ladder and corresponding response of ADC Reference Ladder and corresponding ADC response Comparator and Latch Circuit Output of the comparator and latch to opposite going ramp Signals A single cycle of output of comparator and Latch An alternative view of the regenerative part of the Comparator and latch A conceptual view of the regenerative part A NMOS transistor between the output rails Arbitrary differential amplifier with parasitics at output rails Output rails with assisting current sources A circuit implementation of the current pumping technique Current pumping concept applied to the Comparator and Latch Current pumps isolated using transmission gates to reduce effects of parasitics Functioning of Current Pumped Comparator and Latch Simulation run with a closer view of the output of current pumped comparator and latch Comparison of Current Pumped and Normal Architectures Parametric sweep of size of current pumps and resulting differential nets.69 xiv

16 FIGURE No. TITLE PAGE No Parametric sweep of size of current pumps and resulting output swings Digitally controlled Current Pumps leading to digital speed and power control Output of comparator with current pumps turned ON digitally A close view of the output of current pumped architecture Comparator response when assisting current pumps are Digitally turned OFF and isolated A zoomed in view of the response of the comparator and latch with the current sources turned OFF Comparison of outputs when the assisting current sources are turned On, Off A high speed sample and hold circuit suited for high frequency applications Clock signal being fed to the PMOS pair after mirroring a. Voltage Pulled Sample and Hold Circuit b. Clock signal of voltage pulled Sample and Hold Amplifier Parametric sweep of size of input transistor and resulting clock waveforms (a). Charge injection cancellation for the SHA (b) Charge injection canceled clock signal Final clock waveforms after voltage pulling, charge Cancellation Comparison of normal architecture and voltage pulled architecture outputs 87 xv

17 FIGURE No. TITLE PAGE No Input sine wave and resulting sampled signal A sine wave of 250 MHz sampled by a 2.5 GHz clock signal The digital components of the Flash converter A single stage of a thermometer code to Gray code converter An implementation of the thermometer to Gray converter that employs lower number of transistors Thermometer to gray code converter with sparkle error correction Input given to the thermometer to binary code converter Output of the thermometer to binary code converter for input as in Fig Transistor level implementation of a 2 input NOR gate Transistor level implementation of a 3 input NOR gate Input to the 3 input NOR gate Output of the 3 input NOR gate for the input as in Fig Transistor level implementation of the NOT gate used in the converter Input (orange) and output (blue) of the NOT gate in Fig The thermometer code that is output from the string of comparator and latches for a sine wave.101 xvi

18 FIGURE No. TITLE PAGE No Output gray code for the input as in Fig Gate level implementation of FAT Tree Encoder as in [15] Modified implementation of FAT Tree Encoder with low power, delay NAND Gate implementation at transistor level for the FAT Tree Encoder Output of the FAT Tree Encoder when inputs to the Thermometer to gray code converter are as in Fig Conceptual operation of the sub-ranging operation Conceptual operation of the modified sub-ranging flash converter used in the thesis Pass gate transistor level implementation Reference selector composed of analog multiplexers Implementation of reference propagation, multiplexer A single case of the outputs of the reference selector Stair case response of reference propagator to a decreasing ramp Delay introduced by a comparator: 0.5 ns Delay introduced by the FAT Tree Encoder: 0.5ns Delay introduced by the reference generator: 0.2ns Comparison of the instantaneous and delayed samples Plot of response of the comparator showing a mismatch in common mode voltages.125 xvii

19 FIGURE No. TITLE PAGE No. 7.2 Comparison of common mode voltages when the current sources are turned on and off Plot of mismatch current in an inverter Sweep of transistor sizes of the current pumps showing lowering of sensitivity when current pumps begin to dominate due to excessive sizing Response of the string of comparators to a ramp signal Plot of the frequency spectrum of the output of the ADC Frequency spectrum of output showing the noise floor Frequency plot showing the maximum amplitude of the spur Comparison of response of ideal converter with the Implemented converter Reconstructed output of the analog to digital converter Differential Nonlinearity plot of the converter The Integral Nonlinearity plot of the ADC Trial layout of the op-amp used in the thesis Better laid op-amp (a) Optimised layout for the PMOS transistors (b) Optimised layout of differential amplifier transistor pairs DRC successful for the opamp layout LVS reports the netlists match Layout of the comparator and latch along with current pumps and pass gate Layout of the sample and hold amplifier.153 xviii

20 8.8 Layout of a 4 input NOR gate 154 xix

21 CHAPTER 1 INTRODUCTION 1.1 NEED FOR ANALOG TO DIGITAL CONVERTERS High frequency communication is desired because the higher frequency provides the potential to carry more information than communication circuits that operate at lower frequencies. It is true that light used as a carrier in communication systems has a very high frequency, but the need for optic fibers in them makes their use severely restrained. This places considerable interest is the unlicensed band centered around 2.4 GHz; since the band is unlicensed, anyone can transmit in this band provided the power is constrained to a level of a few mw. This is highly suited for transmissions such as Bluetooth, Wi-Fi etc. which rely on short range high data rate communications. The communication systems that use bandwidths greater than 500 MHz or a fractional bandwidth greater than 0.2 are called Ultra Wide Bandwidth (UWB) communication systems. Along side this, with the processing power of digital chips being pushed further and further into the giga-flops per second range, increasing complex digital algorithms are now feasible to be implemented. These algorithms can perform far better in terms of performance compared to analog counterparts, if any, such as filters. It becomes vital that fresh data is fed to these processes as fast as possible to have the system through put high. 1

22 In case of the communication circuits, it is essential that the in-coming analog signal is converted to digital data as fast as at least twice the signal rate received, which otherwise, would result in data loss. The above merge and produce the requirement for a high speed ADC. Since most of the devices that utilize this method of communication are portable and run on a battery, it becomes essential that the power consumed is very minimal. A large number of applications that use Analog to Digital Converters (ADCs) are portable devices. With a lot of markets opening up to these devices in developing countries, the reach of the technology has extended beyond the few privileged to the masses. With this comes the requirement that each firm remains competitive with new features and improves current properties of the device. An extended battery life has always been the plea of any portable device owner. Thermal heat sinking of devices is being pushed to the limits to maintain the devices in their operating range and to have them function properly; coupled with the smaller sized devices that are sought by everyone, this manifests itself as a big challenge as this requires a lot of heat to be dissipated in a small area. All these needs culminate into low power consumption, high speed of operation with good resolution and small chip size. It is also very important that the cost of the component be as low as possible since these components go into production with counts over millions, a minuscule increase in the cost of manufacturing a component would end up being magnified millions of times for the company marketing it and the reverse can be said about savings. Similar trends are true even for issues such as power consumption, where a small increase in power consumed by a device would manifest itself as a large power consumption by the population. 2

23 For UWB communication systems, this requires that the data be sampled at a frequency greater than 1GHz. It is also a constraint that the resolution is at least 4 bits [12, 19] to be of use to the systems in noise and interference constrained environments. Off late, many ADCs that are based on technologies such as InP, SiGe and photo converters [23] have been developed that can reach up to 40 Gsps[14]. Though they are high speed, they are generally not manufactured in large scales as CMOS as this requires special fabrication units which turn out to be prohibitively expensive. Plus, CMOS technology has not quite really reached its maximum performance. A lot depends on the innovation of the designers to push the limits further. This will enable the large scale manufacturing of the components and costs will be rendered lower. Further ADCs operating on very high data rates are being sought for hard disk reading. Though the digital processors are well advanced and their speeds of operations are into the giga-bits per second range, rarely is this speed realized in practice. This is essentially because the bottleneck in processing power now rests on how fast data can be retrieved from memory rather than on the speed of the processor. Multiple levels of cache memories are used to provide a seemingly faster access to data, nevertheless, data retrieval from the magnetic hard disks are crucial as cache memories have reached only a fraction of the size of hard disks in terms of memory. Thus, this thesis deals with the development of an ADC that caters to these needs. The thesis is centered around innovative developments and then an ADC is constructed around these developments and the improvements are shown. Certain new techniques have been developed and they are shown to increase the speed of the 3

24 converter to twice the original value, better than a mere increase of transistor sizes and also in terms of sensitivity. A small quantitative analysis of the techniques is also provided. Further, the technique is implemented in such a way that it can be digitally programmed as to if the user requires higher speed or lower power consumption. Such decisions are very familiar in portable devices, namely the stand by mode and plugged in modes in lap tops when they are connected to the mains and stand by modes in cell phones. Usually in portable devices to conserve precious power, the power amplifier, which is one of the most power consuming components, is switched ON only when it is needed so that the power consumption is lowest when in stand by mode. A similar concept is applied here in case of comparators, which is a high power consuming component in a ADC and it is shown that power consumed can be minimized by switching the comparators between the standby and operating modes. 4

25 1.2 TYPES OF ANALOG TO DIGITAL CONVERTERS The ADCs are of many sorts, some of the most important are: Successive Approximation, Sigma Delta (Delta Sigma), Flash, dual slope, single slope converters. But the classification of the ADCs is more prudent if based on their advantages and disadvantages rather than on the way they perform these conversions Low Speed, High Resolution, Low Power ADC This is a class of converters that function for conversion of slow varying signals but with extreme accuracy. These converters usually have resolutions greater than 8 bits and perform on very low power. These are very well suited to measuring devices. A lot of work is happening to increase the speed of these converters and at the same time retain the resolution and low power consumption. The sigma delta ADC is a good example for this class of converters. They can provide resolutions greater than 16 bits at 100 Msps [37] High Speed, Low resolution, High Power ADC These converters rely on lower accuracy and higher power consumption to attain high speed of operation. The Flash converter is the most dominant of this type of converters. The main disadvantage of this type of converters is their higher power consumption. A lot of work is happening in this domain to reduce the power consumption and to also push the performance of these converters to attain a higher speed of operation. Some of the examples are the capacitive interpolation techniques, pipelining architectures. 5

26 1.2.3 Low Speed High Resolution Low Power Converters As discussed earlier in this chapter, this category of converters is used when the input signal is not of high frequency and a good resolution of the signal is needed. A lot of work is going on this field of converters. Some good examples of this type of converters are: Successive Approximation Register Converters (SAR Converters), sigma delta converters, dual, triple slope converters. A good reference to the history and advances of converters is in [3,5]. All these converters have only one comparator in their architecture and use multiple cycles of comparison to deduce the correct digital output code for the input analog value. Since many cycles are used for one code, the power consumed per computation is also spread over a longer duration. Hence, this reduces power consumed in a cycle. There are more advantages to this processing than just power consumption as will be seen in the following sections Successive Approximation Register Converters The approach of this converter is to use the binary tree search algorithm, lately, techniques that use ternary search algorithms have also been coming up [Reference: Shankar]. These systems begin to resemble pipelined flash converters on their high level. The Analog Converter has an in built Digital to Analog Converter which is used. First the controller inside the ADC sets the MSB to 1, this is equivalent to exactly half the full scale of the converter. The DAC converts this to an analog value and feeds it to the comparator which decides if the input value is higher or lower than the digital code. If the code is lower, then the next less significant bit is set and the comparison is done again, else, the most 6

27 significant bit is zeroed while the next bit is set. This process continues till the correct code is found out. Since successively approximations are made till the right code is found out, plus a register is used to store the digital code, this converter is called the Successive Approximation Register (SAR) converter. This operation is shown in Fig 1.1 where the code is for a 4 bit SAR converter. Listed in each column of the image are the binary codes for 4 bits; the boxed codes are the binary values that the register can take in each step of approximation. Each line connecting the boxes represents a path that the SAR can take depending on the current value and the approximate input value. 7

28 Fig 1.1 Binary search path the SAR can take up For 4 bits, the SAR will take a maximum of 4 cycles of approximations; extending, for N bits resolution, the SAR will use N cycles in a radix-2 SAR converter. Each boxed value is exactly half way between the values determined in the previous step. This is due to the binary nature of the search algorithm. The same converter s radix-2 search tree path is shown in Fig 1.2 with only the possible values in each step the register may assume present in it. 8

29 Fig 1.2 The search tree of the SAR ADC showing the various paths Sigma Delta Converters The sigma delta converter is another important converter which similar to the SAR ADC uses a coarse ADC and a DAC in the feedback and multiple cycles of conversions to deduce the value of the analog input to the corresponding digital code to a great accuracy. 9

30 The name Sigma Delta comes from the fact that there is an integrator and a difference detector in the converter. Similarly Delta Sigma converters are also available. One of the great advantages of this class of converters is the noise shaping performance that they have. Fig 1.3 Noise shaping taking place in a sigma-delta ADC As shown in Fig 1.3, the noise is shaped from the value of V lsb^2 / 6 to the shaped spectrum. This shows that the quantization noise is greatly reduced in the frequency band of interest. Shown in Fig 1.4 is an enlarged version of the frequency band of interest. F b indicates the maximum frequency content of the signal, Fs is the sampling frequency. 10

31 Fig 1.4 Closer view of band of interest and noise in region This noise shaping performance is done by using a filter between the ADC and the DAC as shown in Fig

32 Fig 1.5 An oversimplified architecture diagram of a sigma-delta converter The order of the filter and the sampling frequency decide the amount of noise that lies inside the band of interest High Speed, Low Resolution, High Power ADCs This class of ADCs consume a lot of power but operate at the highest speeds that ADCs are capable of operating. They provide low to moderate resolution. This class of ADCs are dominated by the flash converters. They consume a lot of power as they have many comparators in their architecture, but this also makes them very fast as they provide the output digital value with a high throughput. The architecture consists of a sample and hold stage, this stage provides an output at each clock high level to the succeeding comparator and latch block. The comparators have one terminal obtaining the sampled value which the other terminal is attached to a resistance ladder that develops proper reference voltages that are products of the Least Significant Bit [LSB] voltage. Thus, they compare the input signal with the reference 12

33 value and decide if the input is higher or lower than this reference. This produces a set of decisions. This set of decisions is then fed to a set of digital circuits which convert them into the corresponding digital values. All these occur in a single clock cycle. These operations are shown in Fig 1.6. Fig 1.6: A conceptual Flash Converter operation As can be seen, this has very high speed of operation and hence is used for applications which require high bandwidth and high speed of operation. It is interesting however, that the energy consumed to perform a conversion in all the converters for an equal number of bits is almost the same, as each require the same number of comparisons. 1.3 Thesis Organisation The Chapter 1 provided a brief introduction of the needs for an ADC and also an overview of the different types of converters. From the discussion above, it is seen that the flash converter has the highest speed of all the converters but also suffers from power penalty. The high speed of the flash converter makes it highly suited for high speed applications, but the power it consumes makes it a great challenge when implementing it for battery operated devices. Chapter 2 discusses the flash converter to a greater detail by providing a simple flash ADC model at the block level. This model is then used to define 13

34 parameters and a direction to move in the Chapter 3 which also characterises the inputs and outputs of each block. The implementations of the ADC at the transistor level is carried on in later chapters. Chapter 4 is the core of the thesis, it deals with the innovations in the thesis and the analog components of the ADC. This is then followed by the digital components that process crude digital representations and convert them into digital data which is used universally; this is shown in Chapter 5 along with techniques to make the system robust against noise. Some optimizations of power are also shown. Chapter 6 describes the flash pipelining components and their implementations. All these are at the transistor level. Supporting simulations are shown for the techniques in the relevant chapters. Chapter 7 deals with the analysis of the results, quantization, optimizations of new techniques. Chapter 8 deals with the layouts of the components and a walk through of a layout design cycle is shown with optimizations, verifications and parasitic extractions. Chapter 9 concludes the thesis and also provides a view at the possible developments that can be done in the current work. 14

35 CHAPTER 2 A THREE BIT FLASH CONVERTER Chapter 1 explains the different types of converters and briefly explains the working of the flash converter. This chapter explains the working of flash converter to a greater detail. This helps define parameters and also provides a performance scale on which the converters developed can be compared to in later chapters. Also, to explain the processes that take place in a flash converter when there is a conversion between an analog value and the digital value, the example of a three bit flash converter is discussed in this chapter. Discussed here is a simple single stage flash converter with a 3 bit resolution. It is assumed that the analog converter is preceded by the analog anti alias filter that prevents aliasing. It is also further assumed that there are the necessary band gap circuits that produce the required supply voltages for the converter. 2.1 FUNCTION OF FLASH CONVERTER The flash converter follows the general principles of quantization and sampling. First the signal is sampled and then this is followed by quantization. Quantization how ever does not lead to the digital value directly and hence digital processing is needed to convert the quantized signal to their corresponding digital values. These processes are now explained in a more detailed form in the following sections. 15

36 2.1.1 Sampling of the Analog Input The analog input signal may vary continuously and may operate at the maximum allowed frequency provided by the anti-alias filter. In this case, it would lead to errors if the signal is fed to the succeeding stages as complete sine waves as these stages would not have enough time for them to react to the changing analog signal. By the Nyquist theorem, it is known that the signal can completely be reproduced without any error if consecutive points of the signal are known and if the consecutive points are not further apart than half of their cycle. Thus, if we merely know the signal value at certain points on the signal, we can safely discard the rest of the signal without loss of information. Thus the succeeding blocks can operate on these specific signal values alone and they do not need to process the entire signal variation. The succeeding stages thus require a stable held value that is proportional to the absolute value of the input signal at these points. Such stables values are provided by the sample and hold architecture. When the succeeding blocks are not operating on the value provided by the sample and hold, then the sample and hold block tracks the current input. When the succeeding blocks have finished their operation on the previous value and require a new input from the sample and hold, then it holds the obtained input value and provides it to the succeeding blocks. Shown below is a representation of the operation of the sample and hold processing. The duration of each phase is determined by a clock signal and its duty cycle. 16

37 This operation is shown for a sine wave in Fig 2.1 Fig 2.1 Sample and Hold operation performed on a sine wave In ADCs, the speed of the sample and hold amplifier decides the speed of the entire ADC [32]. Also, various other performance measures also depend on the performance of the sample and hold amplifier (SHA). Hence, the performance and the SHA is very critical and must be optimum. 17

38 2.1.2 Resistive Ladder Network The speed of the flash converter relies on the fact that the input value is compared with all the reference voltages at once rather than in successive clock cycles. To generate the reference values, a reference generator has to be used; the resistive ladder network and the capacitive reference generation networks are two popularly used techniques, but they consume a lot more power than later techniques. Recently, techniques have been developed such that the size of input transistors of comparators set a specific reference to which the input value can be compared with [21]. The resistive ladder network is however the simplest circuit to construct. A string of resistors of equal resistance that are held between two reference voltages. According to the resistive interpolation technique, the reference voltages are split into the reference values. The reference values can quantitatively be given by the voltage division rule. It is to be noted that the reference voltages are proportional to the ratio of the resistances above and below a particular point and not to the absolute values of the resistances. This is a very key point since in the modern fabrication process, ratio of the resistances can be obtained to an accuracy of about 99.9% and absolute resistances can vary by as much as 20-30% of their absolute value without expensive laser trimming. Thus the ratio avoids huge variations in the reference voltages and provides stable reference voltages. 18

39 2.1.3 Comparator and latch The held input voltage is to be compared with each of the reference voltages and the result of the comparison, either a high or a low, is to be given with the value being held for a clock period. The holding of the output is called as latching and is significantly different from the holding in the sample and hold circuit. These operations are performed by the circuit called as the comparator and latch circuit. If the input voltage is higher than the reference voltage, then the comparator outputs a high signal and if the input is lower than the reference voltage, the comparator outputs a low value and holds the values for a clock cycle so that the succeeding stages can work on them. The signal, is in a crude sense, has been converted to a digital code at this stage as the signal has been represented using just high and low values. The operation on the signal is shown in Fig 2.2, The sine wave has been sampled at six times its frequency and hence, each sine wave has six samples. The samples are the flat portions of the sampled sine wave. Each of these flat regions is compared by all the comparators with the voltage references generated by the resistance ladder. 19

40 Fig 2.2 Top level view of function of comparator and latches The output value of the comparator swings between the rail voltages; that is between Vdd and ground value. This is the first block that experiences such swings in the chain of blocks, however, the comparator operates on analog inputs and the output is digital. If the comparator can settle to its values faster, then the succeeding stages can like wise be optimized for higher speed. Hence the speed of the comparator is critical Thermometer to Binary Code Conversion The input signal is compared with the reference values and all the comparators settle at either a high or a low value. The comparators comparing the reference above the signal settle at a low value and the comparators comparing the signal above the reference value settle at a high value. Since the references are from low to high, the comparators form a sort of thermometer code in which all the comparators comparing references below the input signal are high and above are low. From here on, the analog input signal is not given importance. Only the high or low values are used. Thus, information is lost here. This leads to quantization error. It can intuitively be understood that when more 20

41 references and hence more comparisons are used within the supply levels, the signal can be approximated to a higher accuracy and hence the quantization error can be reduced. As noted, the row of comparators produce the thermometer code, this information is not digital in the definition used for computing processors etc. also, more information can be crammed in with the binary representation than with the thermometer representation for the same number of bits. Hence, this code has to be converted to a binary code. The conversion can be based on a simple decoder operation. Decoders are well known in digital circuitry. However, the direct conversion of the thermometer code to a binary value can cause errors called as sparkle errors, in which a flicker of a bit from its value can cause a huge error, at times of the magnitude of even the most significant bit (MSB). To prevent such errors, a more complex operation is performed with the thermometer code before it is converted to the digital code. The operation involves conversion to the gray code and then to the binary code as shown in Fig

42 Fig 2.3 Conversion of thermometer code to Gray code Gray codes are essentially used in digital circuits due to their resistance to errors [42]. It is beneficial to convert the thermometer code to Gray code due the same reason, plus the conversion takes care of sparkle errors as it checks the thermometer code for consistency first and then converts the code to Gray code FAT Tree Encoder The Gray code is then converted to digital code by a conversion block, this is usually a PLA or ROM, but can be implemented using digital circuits also. Performing the operation using sequential circuits implemented using blocks has the advantage of lower power consumption [15]. The operation is performed by a block called as the FAT Tree Encoder which is completely composed of digital gates. This operation is shown in Fig

43 Fig 2.4 Conversion of Gray codes to digital output In the example converter shown above, the values 0 and 1 actually correspond to the analog voltage levels of gnd and V dd. The high resistance of digital circuits to noise is attributed to the fact that though the signal may be influenced by noise and may swing by even a fifth of the total supply voltages, the bits can still be recognized correctly as a one and a zero. This along with the fact that parity bits, error correction codes etc can be added to digital data, which do not have counter parts in analog signals prove that conversion to digital data, is beneficial. In the example stated in this chapter, the input analog sine wave is assumed to swing between gnd and Vdd with a mid point at V dd /2. The sine wave is not considered to go below gnd potential. Thus the circuit is unipolar, meaning, negative values are not accommodated. The converter thus gives unipolar output. It is better to isolate the clock for digital signals and analog signals as this reduces the amount of jitter and fluctuations in the chip. 23

44 2.1.6 Advantages and limitations of flash converter The example discussed here contains only one phase of a clock cycle in which all the processing takes place. All the processing also take only one cycle of operation of the flash converter, such a flash converter is called as a full flash converter. The main advantage of this type of a converter is the speed and zero latency. However, the disadvantage of this type of converter is the number of comparators that the converter uses. For a 3 bit converter, the converter must check the input signal with 7 reference levels as shown in the comparator and latch section. This can be generalized as 2^N 1 comparators for an N bit full flash converter. As discussed in various literatures [17,26, 27, 29], the comparator and the resistive ladder networks are the most power hungry components of the converter. The number of comparators required by a flash converter when the resolution exceeds 8 bits is prohibitively large [17, 25, 27] in terms of the power and area penalty for the full flash converter. Reducing the number of converters or reducing the power consumed by the comparator is of tremendous interest SUB-RANGED CONVERTER Though this thesis discusses the digital control of speed and power consumption of comparators, it still remains that the number of comparators used has not been reduced because of the modifications; hence, the full flash architecture suffering from a chip area penalty is not the perfect choice. Hence, a sub-ranging or a pipelined flash is used. The sub-ranging converter is the best trade off between speed, power and latency [32]. 24

45 The sub-ranging converter deciphers the digital output in multiple stages and multiple clock cycles, but the number of comparators that the converter requires is knocked down by a large extent. For a 6 bit full flash converter, the converter would require 2^6 1 = 63 comparators, but if the same is pipelined with 2 stages and each stage pumping out 3 bits, the total number of comparators is knocked down to 2*(2^3 1) = 14 comparators, which reduces the power and the chip area is also correspondingly reduced. Consider a 6-bit sub-ranging flash converter which has 2 stages each with a 3 bit full flash converter. The conversion takes place in two stages, where the first stage takes care of a coarse conversion (3 MSBs are obtained) and then the digital code is fed to a DAC which converts the digital code into the corresponding analog value. This analog value is then subtracted from the input signal value and this gives a much smaller range which is then compared with finer reference levels by another 3 bit full flash. This ADC then puts out 3 bits which are the 3 LSBs. Fig 2.5: Block level diagram of a Sub-ranging Flash Converter 25

46 The sub-ranging flash as discussed in this chapter requires two clock cycles for the entire conversion, though a new value is put out in each cycle. The first coarse converter takes a cycle and the second converter takes another cycle. This is the minimum period for conversion, though the number of cycles can be greater. As shown in Fig 2.5. The coarse MSBs are available immediately after one clock cycle; however the LSBs take one more clock cycle as a minimum to appear. Thus, a delay is required for the MSB bits. This is easily implemented as D-Flip Flops since they are digital bits. A major disadvantage of the sub-ranging type is the latency that the converter has to deduce a correct digital code. This latency is of great significance in certain applications such as control systems where the ADC is in a feed back loop. This latency would lead to instability of the system [5]. In most other cases, the latency of the converter can be overlooked as the throughput of the converter remains equal to the full flash ADC. Since the ADC used in this thesis focuses on a high speed ADC for communications and hard disk drives, the latency can be ignored. 2.3 Conclusion Chapter 2 explains the various blocks of the analog to digital converter. It also covers the type of input and the type of output at each block. It also shows the nature of the inputs and outputs at the blocks of the system. So far, the system has been discussed from an ideal sense. However as in any system, there are imperfections in each block when they are implemented. This makes the outputs of each block deviate from the ideal response. Hence, quantizations of ideal behavior and deviation from the normal behavior is 26

47 required to compare between systems. Chapter 3 provides these necessary quantizations as measurements and parameters. These parameters are later used in the thesis for easier reference and to signify characteristics. 27

48 CHAPTER 3 PARAMETRICS OF ANALOG TO DIGITAL CONVERTERS Chapter 2 discussed the block level description of the flash converter and the characteristics of the input and output of each block. Chapter 3 discusses the quantization of the outputs and the deviation from ideal behavior. A Converter s performance is characterized by parameters such as Resolution, Power consumed, Maximum input range, frequency, Effective Number of Bits (ENOB), Differential Non Linearity among many others. These will be defined now. 3.1 ADC TESTING The history of testing ADCs begins from the 1960 s. Much has changed in the method the ADCs are tested. The parameters that specify the performance of the ADCs have not been standardized, but it has evolved through time and most companies baring a few stick to the methods and parameters that have come to be standardized. Very good sources of such parameters and measurements can be found in [6, 22]. Lot of literature have been written about testing of ADCs, some of the note worthy references are [6, 22 ] which deal with very good static testing, both back to back and simulated testing of ADCs in general. The reference [22] gives a very good overview of testing of High Speed ADCs and is well suited to Flash ADCs. 28

49 Some tests require the ADC to be connected to a DAC and then correlating the input with the output of the DAC. This test however is very time consuming and also requires the fabrication of a DAC that is at least ten times more accurate compared to the ADC [6]. Such a method is not followed in this thesis. One important condition that has to be followed while testing of the ADCs is that, the test signal must not have any harmonic frequency components at the sampling frequency of the ADC. This is so because, the harmonic components generate periodic quantization noise signal components which can indicate false missing codes and large differential non linearity (DNL) errors [6, 22]. 3.2 STATIC PARAMETERS Parameters can broadly be classified into two depending on the nature of the characteristic of the ADC they measure: static and dynamic; Static parameters are those that characterize the ADC when they are operating in a DC mode. This is similar to large signal analysis of the amplifiers. Dynamic parameters are those which refer to the ADC s response to higher frequency signals, the distortions they produce etc. Signal amplitudes can be large here too. Out of the many static parameters, the thesis concentrates on a few important parameters that are relevant to a converter that works for communication and hard disk applications. 29

50 3.2.1 Over Sampling Ratio (OSR) According to the Nyquist theory, the sampling frequency has to be at least twice that of the maximum frequency component of the signal. This is required so that the digitized data can be reconstructed without any loss of information. However, when the sampling rate is equal to or just greater than the maximum frequency component, this places a severe constraint on the preceding anti-aliasing filter. Thus, usually the signal is sampled at a much higher rate than is needed according to the Nyquist theory. This benefits in two ways, the transition region of the filter can be broader than otherwise; second, the quantization error is reduced as shown in the diagram. The quantization error is spread over a broad region and the portion that falls into the signal bandwidth is reduced. This concept is illustrated in Fig 3.1. Fig 3.1 Noise power in signal band and reduction in noise by oversampling 30

51 In Fig 3.1, the shaded region shows the amount of noise power that lies in the sampling band. It shows the noise power is reduced by over sampling as in the second case. Thus, usually, when low frequency signals are sampled, the sampling rate is held pretty high so that quantization error is reduced. However, when sampling high frequency signals, it is tough to have a very high sampling rate which is multiples of the maximum input frequency. Based on these, converters are classified as Nyquist rate and over sampling converters. The ratio between the Nyquist limit and the signal band, (f s / 2f b ) is called as the over sampling ratio (OSR) [17]. Converters with large OSR are called oversampling converters while Nyquist converters have a small OSR, typically less than 8 [17] ADC Response The Fig 3.2 shows the typical ADC response, which plots the output digital code versus the analog input voltage signal. 31

52 Fig 3.2 Typical ADC response to a ramp voltage 32

53 Resolution It is the number of bits that the ADC uses to represent the analog input it receives. The resolution along with the reference voltage determines the minimum detectable voltage or the minimum change in the output variable. This is called the quantization step. [17] Analog Input Range It is the differential or single ended peak to peak voltage that must be applied to the ADC to produce a full scale response Offset It is the constant deviation of the converter from that of the ideal characteristic of a converter. All the quantization steps are shifted by the ADC offset. The response of the converter with an offset is plotted in Fig

54 Fig 3.3 Offset error seen in the response of the converter Offset error is given by the formula [6]: Offset Error = V *V lsb (ideal) Full scale Error It is a measure of how much the last code transition is from the ideal top transition immediately below V ref + 34

55 3.2.7 Gain Error It is the error on the slope of the straight line interpolating the transfer curve. The ideal ADC has a straight line slope, with a line that starts at V lsb /2 and ends at V msb 1.5*V lsb. When the ADC transfer curve has been accommodated for the offset error, if the end point is still further away from Vmsb 1.5*V lsb, then the ADC has a gain error. The percentage gain error when the offset has been nullified is given by [6]: %Gain error = 100*[(V * V lsb )/(V fs 2*V lsb ) 1] The 1 in the equation corresponds to the slope of the ideal ADC. The gain is actually the slope. Thus when the slope varies, the gain varies and this leads to the gain error. 35

56 Fig 3.4 Response of typical ADC showing gain error In case the offset has not been nullified, the percentage gain error can be calculated using the formula [6]: % Gain error = 100*[(V V )/(V fs 2 V lsb ) 1] Differential Non-Linearity (DNL) Error DNL error is the deviation of the step size of a real data converter from the ideal width of the bins. In an equation, it is given as: DNL(k) = (del(k) del)/del, Where del is the horizontal step size of the converter whose measurement is being done. K is the k th bit for which the DNL is being measured. 36

57 Fig 3.5 Response of ADC showing DNL error The DNL is usually measured in terms of LSB but sometimes is measured in terms of voltages also. The DNL measurement can be done in many ways, one method is to use a sine wave as the input of the ADC, tracking all the digital output codes as in [22]. This method is very reliable, how ever, it is meant for industrial applications where aggressive testing of ADCs is required and where the necessary advanced softwares that record and analyse the output data from the tests are available. For academic purposes however, it is easier to obtain the DNL by using a ramp input to the ADC and then measuring the DNL as in [6]. 37

58 As stated in [6] the code transitions are measured directly instead of using the code centers in this thesis as this is more reliable. This test is however carried out using the histogram technique, wherein a saturating saw tooth voltage waveform is applied to the input. The frequency of this wave is selected so that the AC errors do not occur in the ADC and also harmonics are not related to the sampling frequency as this leads to erroneous results. The saw tooth waveform takes care of two things, first, each code has an equiprobabilistic occurrence and second, it averages out all the input referred noise generated [6]. The equi-probablity eliminates the necessity for post processing such as the ones tested with sine waves. How ever sine wave testing is considered better as it is more aggressive in its testing [22]. The DNL can also be specified in terms of the root mean square DNL. Monotonicity: The digital value of the ADC continuously increases with increasing analog input or continuously decreases with decreasing analog input. The monotonicity of the ADC is guaranteed if the DNL is less than 0.5 LSB for all bits. At times this is described by hysteresis, which is the maximum difference between the non-monotonic values. The histogram check of the ADC alone does not guarantee the monotonicity of the ADC. But how ever, generally a high amount of DNL will correspond to a loss of monotonicity. 38

59 3.2.9 Integral Non-Linearity Integral Non-Linearity(INL) is the deviation from the end point to end point to fit of the converter response. This is used to estimate the harmonic distortions. INL is the cumulative sum of the DNL for each bit. Fig 3.6 Response of ADC with INL errors It shows that the INL is merely the piecewise sum of the differential non linearity. When the INL is large, there is harmonic distortion. The INL again is measured using the direct measurement instead of using the code center measurements as this method is more reliable [6]. 39

60 Power Dissipation It is the power consumed by the device during normal operation or during stand by mode. 3.3 Dynamic Parameters The frequency response and the speed with which the analog components can function, i.e. change the values, charge up parasitic capacitances decides the speed of operation and hence the dynamic specifications of the converter. The dynamic specifications of ADCs require that the sine wave input frequency not be a sub harmonic of the sampling frequency. This has been discussed earlier in this chapter. Further, the sine wave is required to be applied to the ADC for a sufficiently long period so that the noise is averaged out and more reliable average value of the measurements can be obtained which is neither too optimistic nor pessimistic. A sufficiently long would be five complete cycles of the sine wave [6]. All the dynamics are hence made with five cycles of the sine wave. The data bits obtained from the ADC can be fed to a DAC or computer, regenerate the sine wave that created the data bits and then the best fit can be computed. Further, the variations from the original sine wave are compared and the errors are computed from it. This method is however tedious and direct results are not easily obtained. Hence, the output bits are fed to an FFT algorithm and this indirectly computes the sine wave that the data bits signify. By comparing the input and output spectra of the ADC, the parameters are specified. 40

61 Since the testing in the thesis and in general uses the FFT processing to analyze the spectrum of the output codes, the processing effects of the Fourier Transform must also be taken into account and certain errors associated with the FFT techniques must not be held against the converter, such as DFT leakage etc. A lot literature regarding the FFT analysis, the errors encountered have been analyzed and thoroughly quantized in [44] [6]. It is required that the number of cycles that is being fed to the algorithm is an integral number which otherwise would lead to noise in the spectrum due to DFT leakage. Windows are used often to modify the signal such that they do not have any abrupt terminations so that DFT leakage is minimal. If N is the number of frequency bins used in the FFT processing, then it must be maintained that the ratio of the input frequency to the sampling frequency is maintained at the ratio of number of cycles to the number of frequency bins. Also, the number of cycles must be a prime number as discussed earlier. When the ratio is not equal, then the measurement is called as a non-coherent measurement. However, in this thesis, the ratio is made equal, which is called as coherent testing, which is suitable to testing in labs. The DC value of the FFT spectrum is always discarded in the calculations Analog Input Bandwidth The bandwidth that is defined for the ADCs is different from that defined for normal amplifiers. The bandwidth is defined as the frequency at which the full scale input of an ADC leads to a reconstructed output that is 3 db below the low frequency value. This can be obtained by sweeping the input frequency of the signal and then observing 41

62 the output FFT spectrum. The frequency for which the FFT spectrum drops by 3 db is called as the Analog Input Bandwidth (From DC to this frequency) Input Impedance The input impedance at low frequencies is largely resistive. But at high frequencies, the parasitic capacitances also come to dominate the input impedance Equivalent input referred noise The components of the ADC are not noise free. Hence even when a constant DC value is provided to the converter, the output tends to vary about the central value. This is usually Gaussian distributed and the variance is dependent on the Vlsb and the noisiness of the circuit in general. This is often measured by having set the input voltage at a constant DC voltage and then measuring the variations of the output code and plotting a histogram. The voltage, if set near a transition voltage, will produce a symmetric curve with the center between two values. How ever, this is not necessary and the voltage can be set at a value that is at a mid point. 42

63 3.3.4 Signal to Noise Ratio This is the ratio between the power of the signal and the total noise produced by quantization and the noise of the circuits. This accounts for the noise in the Nyquist interval. SNR also depends on the input frequency of the signal and decreases proportional to the input amplitude. For a good response, the SNR must be constant over the entire Nyquist interval or drop by only a few decibels at high frequencies. The SNR can be obtained from the output spectrum as shown in Fig 3.7. Care must to taken about the ratio of sampling and input frequency Signal to Noise and Distortion Ratio Signal to Noise and Distortion Ratio(SNDR) is similar to the definition to the SNR except that non linear distortion terms generated by the input sine wave are also accounted for. It is the ratio between the root mean square of the signal and the root mean square value of the harmonics plus the noise. This again is dependent on the input frequency and the amplitude of the input sine wave. High linearity of components produces a good SNDR. Again, the FFT is applied to the output signal spectrum and the SNDR is calculated as in Fig 3.6, adapted from [6]. The first five harmonics are considered in the evaluation as the other components have less power in them compared to the first five samples. 43

64 Fig 3.7 Computations of SNR, SFDR for an ADC from [6] Dynamic Range It is the value of the input signal at which the SNR is 0 db. This definition is more important for sigma delta ADCs than for the flash converters ENOB To measure the Effective Number of Bits (ENOB), procedures similar to testing of ADCs in case of dynamic specifications is required. This is the Effective Number of Bits given by, ENOB = (SINAD 1.76)/

65 3.3.8 Harmonic Distortion Harmonic Distortion is defined as the ratio between the root mean square of the signal to the root mean square of the harmonic components including aliased terms. It is generally assumed that the harmonic components above the 10 th component have low amplitudes, hence only till the 10 th component are computed Spurious Free Dynamic Range The Spurious Free Dynamic Range is probably the most important definition of the ADC in terms of communication applications since it determines how much spur is to be expected in the entire bandwidth (from DC to f s /2) when the input signal can have a very large dynamic range. Since dynamic range is high and also the entire bandwidth is used, this is very well suited for communication applications that require both. It is the ratio of the root mean square of the signal amplitude to the root mean square of the highest spurious spectral component in the Nyquist range. This is measured for various input amplitudes and SFDR can be plotted against amplitude also. A lot of care must be exercised when using FFT to determine the SFDR as FFT can lead to harmonics showing up due to DFT leakage and this will terribly reduce the SFDR value though the actual SFDR may be quite high Effective Resolution Bandwidth(ERBW) It is defined as the analog input frequency at which the SINAD drops by 3 db compared to its low frequency value. This gives the maximum signal bandwidth that the converter can handle. The ERBW should be well above the Nyquist limit. 45

66 3.4 Conclusion Chapter 2 deals with the block diagram representation of the components of the ADC, using this Chapter 3 characterizes the inputs and outputs of the ADC and then defines the static and dynamic parameters and the terminologies used in the flash converters. Using this base the succeeding chapters develop techniques and concepts for the Flash ADC. 46

67 CHAPTER 4 THE ANALOG COMPONENTS In Chapter 2, the functional block diagrams of the flash converter and the subranging ADC are shown. Chapter 3 discusses the parameters that quantify the behaviour of these blocks based on the text in Chapter 2. Chapter 4 is the core of this thesis and it discusses the transistor level description of the blocks discussed so far. It also shows the new developments that have been made in this work and the supporting simulations to verify the developments. From Chapter 2, it was seen that the first analog components of the ADC are the Sample and Hold Amplifier, Comparator and Latches. This is a top level description of the blocks that are present in the converter. In this chapter, insights into the components are given and how the components have been optimized in this work has been brought out in theory and analysis. Simulations that support the proposed optimizations are also produced as necessary. 4.1 ANALOG COMPONENTS OF ADC The functional diagram of the analog parts are reproduced here for easier reference in Fig

68 Fig 4.1 Conceptual diagram of analog components of an ADC Sample and Hold The sample and hold circuit is the component of the ADC that is the bottleneck in speed. It decides how fast the converter can be clocked [32]. The Sample and Hold can be constructed by using a capacitor and switches that pass or stop the input signal from reaching the capacitor. A conceptual model is shown in Fig 4.2. Fig 4.2 A simple model of a Sample and Hold Operation 48

69 In the Fig 4.2. the capacitance is charged by the input signal when the switch is closed by the clock signal. When the signal forces the switch to the open state, the capacitor holds the value of the last sampled input signal. When clock signal goes low, the inverse clock goes high; this closes the switch and conducts the held signal onto the following circuits. This model is the basis for all sample and hold circuits. But, in reality, a lot of problems arise in this process. A simple implementation is also shown in the Fig 4.2. When the switches are implemented with MOS transistors, it leads to charge offsets that are non-linear, improper resistances of MOS devices etc. Volumes of literature have been written about these issues [5,7,8,9,17,24,32,38] Resistance Ladder The resistance ladder relies on the resistance interpolation or the voltage division rule to split the supply voltage into finer reference levels that are required by the comparator to compare the input voltage with the reference levels. The resistance ladder network is well suited to generating the references as the references form a ratio of the resistances rather than being proportional to the absolute values of the resistances. This is important as these resistances can vary by as much as 30% but the ratios of parameters can be tightly controlled to within 0.1% of the required value without any special laser trimming. The resistance network is shown in Fig 4.3. This network is used for the converters that have a response as shown in Fig 4.3. But for converters that have a response as shown in Fig 4.4, the last resistance and the first resistance values are changed as shown in Fig 4.4. The responses are different by half of the least significant 49

70 bit. The design choice is that of the engineer. The response as shown in Fig 4.3 is suited for bipolar converters as well. Fig 4.3 Reference Ladder and corresponding response of ADC 50

71 Fig 4.4 Reference Ladder and corresponding ADC response Each triangle shown in Fig 4.3, 4.4 is a comparator and latch. Not shown in the diagram are the clock signals that each comparator and latch is fed. The comparators compare the input Vin (which is the output from the Sample and Hold Amplifier) with the reference voltage generated at each node of the resistance and the output of the comparator is set according to the difference in potential between the reference and the input voltage. This happens during the compare phase of the clock; during the reset phase of the clock, the output of the comparators settles down at a common voltage which is half way between the supply rails. This is required so that the comparator output voltage is ready to swing either way when the next comparison phase arrives. The operation of 51

72 the comparator and latches are described in detail in the following sections of this chapter Comparators and Latches Fig 4.5 shows a very common comparator and latch circuit that is used in many ADCs [9]. The comparator consists of a preamplifier and a regenerative latch. The preamplifier in the circuit amplifies the difference in the signal to produce a good difference in voltages that is fed to the latch part; this can also be viewed as a difference in the currents in the output arms of the latch. Since the preamplifier is made of a differential input stage, it provides high CMRR which is essential in high speed circuits. Fig 4.5 Comparator and Latch Circuit 52

73 In terms of analog techniques, the latch part consists of two back to back connected gate drain pair. This is a familiar circuit in case of analog circuits; this displays a negative resistance of -1/gm when looking from the output toward either rail. These pairs are often used to produce extremely high gains and low rise and fall time constants and are hence well suited for the comparator application. Single pair of such a back connected device can also be used [18], but this was found to have a lower sensitivity than the one used in the thesis. Fig 4.6 Output of the comparator and latch to opposite going ramp signals 53

74 Fig 4.6 shows how the comparator and latch reacts to the input voltages applied to the two input terminals. The relatively slowly rising(dark blue) and slowly falling(light blue) ramp signals are applied the to preamplifier inputs of the comparator and latch. The square waves(orange and red) are the voltages at the output rails of the comparator and latch. The comparator decides on the difference and provides an output when the clock is in the compare phase (say as in 5ns to 6ns). When the next phase of the clock arrives, the outputs settle at a common voltage and are ready to settle to the next output value (6ns to 7ns). Initially, the input voltages have a positive difference and at 10ns, the difference in their voltages begins to go positive. To this, the comparator output reverses the direction in which the rails charge up. The net difference in the potentials are reversed. Fig 4.7 A single cycle of output of comparator and latch 54

75 Fig 4.7 shows another simulation with the clock period equal to 1ns and each phase of the clock equal to 500ps. A single cycle has been zoomed into and the characteristics of the output are clearly seen. The common mode voltage is not correctly set and there is a finite voltage difference between the outputs. The charging and discharging of the parasitic capacitances causes the RC time constant and the charging and discharging of the rails takes a finite amount of time. This dictates the minimum required time for the comparators to settle to the final value and hence the maximum clocking frequency. This comparator requires at least 300p to settle to the final value and hence the maximum clocking frequency would be 1.66 GHz. If a ping-pong architecture is used for the ADC, then the speed can be doubled to 3.33 GHz. For a better understanding of the latch part, Fig 4.8 reproduces the regenerative latch part of the comparator and latch without the preamplifier. The connections are the same, but are oriented so that they resemble the commonly seen CMOS inverter pairs. 55

76 Fig 4.8 An alternative view of the regenerative part of the comparator and latch For a conceptual view, the circuit can be visualized as digital components, excluding the bottom current source transistor. This is shown in Fig 4.9 which in essence is a regenerative circuit. The output of one inverter aids the input of the other inverter and hence the feed back is positive. This in digital circuits is called the S-R flip flop. The S-R flip flops operate solely on digital inputs, but the analog comparator and latch is modified to operate on the input analog voltages by using the pre-amplifier, which converts the input voltages to currents. This has two advantages; first, the circuit becomes very 56

77 sensitive, it can detect very small differences that normal opamps struggle to do; second, the rise time is faster as the input of the inverters are forced to go high by each other as well. Fig 4.9 A conceptual view of the regenerative part During the compare phase, the comparator and latch circuit operates as the S-R Flip Flop and just as any flip flop, it holds the value till the end of the clock period; it latches onto the output and hence the name latch. But during the other period of the clock, the bottom current source transistor is turned off and the flip flop is disabled. If left as such, the circuit output voltages are arbitrary and hence, the voltages may set in a wrong way and also this would interfere in the next decision phase of the comparator and latch. To avoid this phenomenon, an NMOS transistor is added between the output rails and is switched on during flip flop disable of the inverter pairs as shown in Fig

78 Fig 4.10 A NMOS transistor between the output rails The NMOS conducts a zero voltage well, hence, this essentially functions as a short between the output rails, this regenerative circuit is then forced into the voltage that is mid range between the supplies by itself. This is held till the next decision cycle of the circuit, errors in this phase of the circuit leads to errors called as the meta-stability errors which leads to sparkles in the output thermometer code. Sparkles by themselves are not too problematic in most applications; also methods to correct sparkle errors are well documented [17,32] and have been proven in practice. Few applications like the ones for high sensitivity digital scopes require very low sparkle errors. Since the work does not 58

79 focus on this category, emphasis is not laid on this topic, but wonderful works are present in this area [17,32]. In very high speed circuits with many blocks, the speed of the whole circuit relies on how fast the parasitic capacitances and other loads of the blocks can be charged and discharged. A large current charges the parasitic capacitances faster than a smaller current. One technique that is very prevalent is to increase the size of the previous stage (input) so that it provides a lot more current to the current stage [38]. This however loads the stage ahead of it and hence a proper sizing ratio is necessary. Local regeneration is possible; however, if the signal needs to pass through more than two transistors, then the delay it experiences is too much to be acceptable for better usage and, the direction of the current flow is critical and establishing this direction during circuit operation is a challenge. Thus, any regeneration circuit must first provide the correct polarity of current or voltage and also must comprise, generally, not more than two transistor passes of the signal. Such a technique and a corollary are discussed in this chapter, which are then applied to the Flash ADC. 4.2 CURRENT PUMPING Theory of Current Pumps This is a new theory that the thesis tries to develop, bring out and apply to analog components on a large scale. The theory has been explained and its application to the Analog to Digital converter's comparator and latch is shown. Large currents produce lower charging times and when extra currents are sourced or sunk from these parasitic 59

80 capacitances, speed of the block can be increased. The speed with which this charging and discharging action takes place is governed by how much current the transistors in the rail path can pump in or out. To increase the current, the size of these transistors can be increased, this in turn increases the capacitance of the rail and the time for the swing remains a constant. Another method as discussed in [38] is to increase the size of the input stage and form a chain of stages with sizes in the ratio of e or e+1. Instead, if the signal can be locally regenerated and an additional current be used to assist the charging and discharging of the parasitic capacitances with the proper polarity, the speed of operation could be increased. Thus we pump in current either into or out of the parasitic capacitances, hence the name current pumping. The concept is similar to that of charge pumps in phase locked loops but different in the sense of these applications. The technique is well suited for the differential circuits more than single ended design. Consider an arbitrary output rail of a differential amplifier as shown in Fig Suppose the rails swing between the supply voltage and the ground potential according to a clock signal. When the rail charges toward the supply, the parasitic capacitances associated with it are also charged towards the supply. During the next clock cycle when the rail voltage goes towards ground potential, the parasitic capacitances are discharged. 60

81 Fig 4.11 Arbitrary differential amplifier with parasitics at output rails Let C represent the total parasitic capacitance of all the transistors. The top pair of NMOS transistors is present to increase the gain of the circuit and is biased as constant current sources and is only optional for use. C can be charged or discharged faster if an additional current source is used with the proper direction. Shown in Fig are two hypothetical current sources that can vary their current direction based on Vctrl, their control voltages. 61

82 Fig 4.12 Output rails with assisting current sources Though a single current source providing both polarities of current is an option, it is easy to implement two voltage controlled current sources of opposing polarity and add their currents to produce a current in the right direction. Thus, one current source would source current into the node and the other would sink current, but to varying extents depending on the control voltage, resulting in a net current flowing either in or out of the node. 62

83 Fig 4.13 A circuit implementation of the current pumping technique The current source in this case can be a PMOS transistor and the current sink can be an NMOS transistor. This concept is shown in Fig 4.13, where the current sources are replaced by the transistors; they resemble CMOS inverters. Selection of the control voltages depends on the input voltages to the differential amplifiers. If the input voltage to the differential amplifier is always going to vary about a common mode voltage, then the input themselves can be used as the control voltages. This reduces the delay between the input and the current source turning on. 63

84 Suppose the input V inm is going low, then V outp would go high, to assist this, the current sources must source current into the node. Since V inm is going low, the PMOS transistor conducts more heavily and the NMOS conducts very little current. Thus the combination produces a current that flows into the node and charges up the capacitance. The inverse takes place at the other rail. Thus the voltages settle down faster Application of Current Pumps to Comparators and Latches Section discusses the development of current pumps to increase speed of devices and section discusses the application of the current pumps to comparators and latches. It also discusses the digital control of speed and power that can also be applied to current pumped architectures in general. The set of operations discussed in section is true in the case of input common mode voltage being close to the midpoint between supply and ground potentials. Suppose the inputs are operating well below or well above the common mode, as in the case of comparators in the flash ADCs, then the small signal variation would not be enough to provide the correct polarity of the current. However, the output voltages of the comparator rails are still enough to provide the correct control voltage. The outputs are always differential and the swings are always in opposite directions in a correctly designed comparator. The control voltages are obtained from the opposite rails as shown in Fig

85 Fig 4.14 Current pumping concept applied to the Comparator and Latch In fact, a transmission gate could also be inserted between the conventional latch of this comparator and the current sourcing/sinking transistors as in Fig When this transmission gate is properly switched only when the current pumping is required, the pre-amplifier would avoid charging the very small parasitic capacitances associated with the drain nodes of these current pumping transistors and their gates. The circuit is shown in Fig

86 Fig 4.15 Current pumps isolated using transmission gates to reduce effects of parasitics Fig 4.16 Functioning of Current Pumped Comparator and Latch 66

87 Fig 4.16 shows the output (red, green) of the comparator to the input signals that opposite going ramps (blue lines). The comparator works at a clock period of 500ps, with the decision cycle taking up 250ps. This allows for a speed of operation of 4 Gsps when used in a ping-pong architecture. This can however be reduced to 400 ps which produces a speed of 5 Gsps. Fig 4.17 Simulation run with a closer view of the output of current pumped comparator and latch 67

88 Fig 4.17 shows another simulation run and the output having been zoomed in for a better view. The simulation shows how the rise time is now only about 200ps. This allows for the operation at 5 Gsps in time interleaved architectures. Fig 4.18 Comparison of Current Pumped and Normal Architectures Fig 4.18 shows the comparison of the normal architecture and the current pumped architecture. The simulation clearly shows that the current pumped architecture has only about half the charge up time as the normal architecture. The normal architecture had the sizes of the rail transistors increased to equal the size of the current pumped architecture. The lowest voltage that the output rail can take is now ground potential, as compared to 68

89 the V dsat of the tail transistor in the normal architecture. This is because, there is no tail transistor for the assisting current pumps. This is an advantage. Fig 4.19 Parametric sweep of size of current pumps and resulting differential nets Fig 4.19 shows a parametric sweep of the sizes of the current pumping transistors and the differential net output voltages of the rails that are generated. The simulation shows that higher the transistor size, faster the rise and fall times. However, this also leads to higher power consumption. Hence, a trade off is to be achieved between the size, power and speed of operation. 69

90 Fig 4.20 Parametric sweep of size of current pumps and resulting output swings Fig shows the swings of the rails for the parametric sweep and it is evident as to how current pumping improves the speed of operation. This type of a circuit modification provides one more advantage. This breaks down the circuit into two combinations, being, the component that decides the voltage swing directions, which is in essence slow and consumes little power and the component that assists the voltage swing, pumps the current in the right direction and which consumes a lot of power. In the circuit, the core of the comparator with the cross coupled MOS pairs decide the voltage swing directions and the current pumps assist them. 70

91 This split up of the circuits leads to another advantage: control of the components separately, which in turn produces the control of power and speed. When the assisting current sources are switched off, the comparator consumes very little power but is also slow as current pumping does not assist the comparator. But, when it is turned ON, the comparator consumes more power but also operates faster. This switching ON and OFF of the comparator current pump blocks can be done digitally by introducing a third PMOS transistor into the inverter configuration. When the gate voltage of this PMOS is made to go low, it perfectly conducts the supply voltage to the inverter pair and it functions as a current pump, when a high signal is fed to the PMOS gate, then the current pump is turned off. Thus, the speed and power can be controlled digitally for the comparator. This circuit setup is shown in Fig The circuit has been reproduced without the transmission gates for simplicity though they exist in the actual implementation. 71

92 Fig 4.21 Digitally controlled Current Pumps leading to digital speed and power control 72

93 Fig 4.22 Output of comparator with current pumps turned ON digitally Fig 4.22 shows the output of the comparator when the current pumps are turned ON digitally. Fig 4.23 shows the same simulation run with the output value zoomed into. Fig 4.23 A close view of the output of current pumped architecture 73

94 Fig 4.24 Comparator response when assisting current pumps are digitally turned OFF and isolated Fig 4.24 shows the same comparator output to the same input but with the current pumping digitally turned off. As can be seen, the rise is much slower and the rise is not complete when the clock period has elapsed. Clearly current pumping has improved the speed of the comparator. Fig 4.25 shows a zoomed in version of the same simulation run. 74

95 Fig 4.25 A zoomed in view of the response of the comparator and latch with the current sources turned OFF Fig 4.26 Comparison of outputs when the assisting current sources are turned On, Off 75

96 Fig 4.26 shows a comparison of the digitally turned on and turned off configurations of the current pump assisted comparators. It is intuitive that the response of the comparator when the assisting current sources are turned off is almost the same as that without the current sources at all A Brief discussion of results for current pumped architecture An increase of about 40% in the power consumed was noticed when the current sources were turned ON. This can also be viewed as a 28.75% reduction in power consumed when the comparator is switched from high speed mode to low speed mode. The circuit discussed in the previous section has been implemented for a comparator and the output is plotted and compared to the circuit without assisting current sources. The circuit outperforms the normal architectures for all input voltage combinations. There are two more advantages in this configuration; first, the low rail can be pushed down to a complete ground potential compared to the very small V dsat associated with the tail transistor of a conventional latch. This allows that the V dsat of the tail transistor remain nearly 0.3 V, which is similar to the LNA design, so that the transistor does not suffer from voltage saturation and end up generating noise. Second, the sensitivity of the comparator is increased tremendously because of the reduction in the parasitic capacitors seen by the pre-amplifier due to the addition of two extra transmission gates on either side. This is discussed earlier. Both these advantages were not obtained even when the rail and input transistors of the original circuit were increased in terms of sizes equivalent to this configuration. This indicates that this is not equivalent to having parallel amplifiers or mere increase in the size of the 76

97 transistors. In the original configuration, though transistor sizes are increased, it can still only sample the same minute difference in the input voltages, however in the case when the outputs are being fed to the current sources which now forms an inverting configuration, the voltage difference they detect is much higher and they strengthen this by giving a manifold increase in sensitivity. A disadvantage of this method is that it consumes a little more power than necessary to provide the current; the power consumed is about one and half times more than the original circuit. A method to minimize this would be to switch the current sources also and to obtain a single current source that was discussed earlier. In other words, the efficiency of the current pumps can be improved to further reduce the power consumed for high speed setting Future Works on Current Pumps The sections 4.2.1,2,3 discuss the current pumps and their applications to the comparator and latches. However, it is possible to develop the concept in a broader sense and this would the aim in future works. However certain aspects of the current pumps themselves can be improved, this is discussed in this section. The concept of digital control of current pumps can be extended to a multi rate comparator with multi power consumption modes by using multiple stages of current pumps and each controlled individually. Further, the amounts of currents each stage pumps in can be ratioed as powers of 2, so that truly digital multi bit settings can be obtained. 77

98 One disadvantage of this method is that, when the number of gates attaching to the output rails is increased, the capacitance attached to the output rail node is also increased. This increased capacitance tends to slow down the charging of the rail when the current sources are not pumping in current. This problem can be overcome by using a switch that disconnects the current pump s input from the output rails when the current pumps are not being used. 4.3 VOLTAGE PULLING Theory of Voltage Pulling A corollary to the current pumping theory is the voltage pulling theory or vice versa. Though in essence both operations are very nearly the same, there are subtle differences and the operations are easier to understand according to the application of the concept. In the case of voltage pulling, the circuits where voltages need to be pulled to the supply voltages are targeted. Here, the emphasis is that node voltages do not reach the supply voltages even if a very long settling time is provided to them and this effect is not because of the parasitics but because of general transistor operation and biasing conditions. The solution is based on the fact that PMOS transistors are strong conductors of a positive voltage and NMOS transistors are strong conductors of a 0. Thus providing these transistors with a suitable control voltage would pull the voltages to either ground or supply voltage. This extends the concept of current pumping beyond merely satisfying parasitic capacitances to making circuits more robust. This concept can be clearly 78

99 understood by studying its application to the Sample and Hold circuit from [4,8]. The circuit is optimized for speed Application to Sample and Hold Section discusses the theory of voltage pulling, this section discusses the application of voltage pulling to the sample and hold circuit. Fig.4.27 shows a high speed sample and hold circuit tailored for differential input signals. It is an altered circuit from the one in [34]. This sample and hold circuit is in the form of a differential amplifier whose tail currents and the gate voltages of the top PMOS pairs are determined by the current mirrors that is active only during the positive level of the clock. During this phase, the sampling of the input is done and in the negative level of the clock, the current mirrors are disabled saving power and the last signal value is held in the hold capacitors, these hold capacitors can also be the capacitances of succeeding stages. The clock signal being provided to the top PMOS pairs, obtained after mirroring also disables the sampling differential amplifier circuit. 79

100 Fig 4.27 A high speed sample and hold circuit suited for high frequency applications Mirroring is performed so that the clock voltage only has to swing between just above moderate inversion and supply voltage making the circuit faster by minimizing the effect of the slew rates of the transistors. This also reduces the effects of clock jitter on sampling. In principle, this differential amplifier circuit would tend to continue operating in the active region because of the voltages stored on the parasitic capacitances in the gates of the tail transistors during the positive level of the clock. Also the negative level of the clock does not reach deep near the supply level, causing the top PMOS pairs to remain ON for a finite duration, which may well reach nearly 40% of the hold period at very high speed clocking. This leads to high voltage offsets and the offsets being dependent on the input amplitude since during the transition, the arrangement acts like an 80

101 amplifier and amplifies the input and puts it into the capacitor. The clock signal in this case is shown in Fig Fig 4.28 Clock signal being fed to the PMOS pair after mirroring To remove this effect, two additional transistors are added which pull the voltage up to the supply voltage. This is shown in Fig 4.29 a. and the resulting clock signal is shown in Fig 4.29 b.. The extra PMOS transistor on the top of the sample and hold circuit provides the supply voltage (1.8 V) to the gate of the active load in the differential amplifier turning it completely off. Similarly, an extra NMOS transistor on the bottom of 81

102 the sample and hold circuit shorts the gate of the tail transistor in the differential amplifier circuit to ground. Fig 4.29 a. Voltage Pulled Sample and Hold Circuit Fig 4.29 b. Clock signal of voltage pulled Sample and Hold Amplifier 82

103 This enables the tail transistor of the differential amplifier to turn completely off. This addition of two extra transistors enables the perfect holding of the sampled signal. Also, the rise of the signals is much faster thus minimizing the effect of offsets to a much greater extent. Fig 4.30 Parametric sweep of size of input transistor and resulting clock waveforms Fig 4.30 shows the different clock signals for different values of the PMOS mirror transistor W/L on a parametric sweep. As can be seen, as the size of the input transistor increases, the range within which the clock signal swings reduces. A smaller swing 83

104 provided it is in the proper regions of operation ensures that the system can be clocked faster with higher reliability. 4.4 Charge injection Cancellation The MOS transistor can be viewed as a large capacitor when viewed from the gate to the bulk, the charges need to move between the drain and the source. This charge requires a finite time to transit from the drain to the source. This time is very negligible when the frequency of operation is low; however, when the transistor acts at high speed, especially when the transistor is switched between the supply voltages, a phenomenon called as charge injection occurs onto the connected devices. The charge that is present when the transistor switches between the supply voltage and the ground potential needs to discharge. But since the transition is very fast, the charge does not escape into the supplies, but has enough time only to get through to other devices before they turn off themselves. This leads to signal swings that are not expected and are undesirable. To avoid this phenomenon, each of the transistors is attached with its complementary pair. The complementary transistor injects the opposite charge carrier into the system compared to the transistor of reference. This neutralizes the charge injections and improves system performance. This can also help speed up the performance of the system if the signals are tracked correctly. The circuit is shown in Fig 4.31 a. 84

105 The charge injection canceled clock signal is shown in Fig 4.31 b. The rise still takes the same amount of time, but it starts and ends smoothly and hence there is no undesirable swing in the signal. Fig 4.31 (a). Charge injection cancellation for the SHA 85

106 Fig 4.31 (b) Charge injection cancelled clock signal Fig 4.32 shows the final clock signals that are obtained after voltage pulling and after the charge cancellations have been performed to the circuit. The swings are not between supply and ground but only just over moderate inversion to turn off. As discussed, this enables faster clocking of the SHA and eases the bottleneck. 86

107 Fig 4.32 Final clock waveforms after voltage pulling, charge cancellation Fig 4.33 Comparison of normal architecture and voltage pulled architecture outputs 87

108 Fig 4.33 shows a comparison of the voltage pulled and normal architecture outputs. The yellow line is the normal architecture output and the violet line is the output of the voltage pulled architecture. Fig 4.34 Input sine wave and resulting sampled signal Fig 4.34 shows an input sine wave and the resulting sampled signal in a differential net. The sine wave is of a frequency of 100 MHz and sampling frequency is at 2 GHz. The signal swing is from gnd to V dd. 88

109 Fig 4.35 A sine wave of 250 MHz sampled by a 2.5 GHz clock signal Fig 4.35 shows a 250 MHz signal sampled by the SHA with the clock period of 400ps and a clock width of 200ps. This provides an oversampling ratio of 5. Similar to the charge injection cancellation present in the sample and hold, charge cancellation can be done in comparators also. The results are similar to that obtained with the SHA. 89

110 4.5 Conclusion The analog components of the ADC are discussed in Chapter 4. It also presents the advances that have been made in this thesis with regard to the analog components namely the current pumping and voltage pulling theory and how it benefits the ADC with higher performance. The techniques are the core of the thesis and the ADC has been built around these concepts to demonstrate their functionality. The chapter also provides a brief discussion of the results relating to the performance of the blocks of the converter. The chapter deals with the analog components of the ADC, chapter 5 deals with the digital components that have been implemented in this thesis. The analog components pass on the thermometer code to these digital components. 90

111 CHAPTER 5 FLASH DIGITAL COMPONENTS Chapter 4 developed the theories explaining the analog components in the ADC. As seen from Chapter 2, these analog components convert the analog signals and provide the thermometer code, one code for each clock cycle. This thermometer code is then converted to the digital output by the ADC. Chapter 5 discusses the processing of the digital signals. The gate level, transistor level implementations and block level implementations are shown. Transistors are just four terminal devices that process voltages and currents depending on their terminal potentials. The classification of these signals into digital and analog has no effect on them. But, circuits that process only digital signals can be optimized in such a way that the power they consume is very little. This is the basis for the CMOS, the Complementary MOS in which either the current or the voltage is very low, hence their product, the power consumed by the component is very low. Analog how ever suffers from the fact that, the circuits are made to operate in between both these points; hence the power is always higher for analog. 91

112 5. 1 DIGITAL BLOCKS OF THE ADC The digital circuits that are used in the converter are reproduced from chapter 2 here for easy reference. Fig 5.1 The digital components of the Flash converter As discussed in Chapter 2, the sampled and held signal is fed to the comparator and latch network and the comparators decide if the held signal is higher or lower than the reference voltages generated by the resistance network. Till this point in the flow of signals, the signals can predominantly be classified as analog signals. The new digital signal is then fed to the bubble corrector that corrects sparkles and provides the position of the bit transitions, this is done by the thermometer to gray code converter. This coded sequence of bits is fed to the decoder (FAT Tree Encoder) which converts the sequence to the correct digital output. These processes are shown for six different clock cycles in Fig 5.1. These processes are explained in greater detail in the following sections. 92

113 5.1.1 Bubble Corrector and thermometer to gray code converter As discussed in chapter 2, the thermometer codes generated from the comparator and latch circuits are susceptible to sparkle errors due to noise, low sensitivity. To reduce the effects of sparkles to a great extent, the bubble corrector circuit is employed. The bubble corrector circuit is a digital logic circuit which detects where the transition from all zeros to all ones occurs in the thermometer code. The bubble corrector may be thought of as a differentiator. This however is also similar to the gray code which is defined as one out of N. The gray code is essentially resistant to errors and any error resulting would only be of magnitude equal to the LSB voltage level and hence not too ominous [42]. The objective of a bubble corrector is therefore two fold; correcting sparkles (at most one bit) and converting the thermometer into a gray code. A normal conversion of thermometer code is achieved by checking if the corresponding bit is 1 and the next bit is a 0 (t n.not(t n+1 )). A single such corrector is shown in Fig 5.2. Fig 5.2 A single stage of a thermometer code to Gray code converter This is implemented using a 2-input NOR gate with the complement of the corresponding bit and the actual value of the next bit as the input as this is more efficient in terms of transistors and power consumed. The implementation is shown in Fig

114 Fig 5.3 An implementation of the thermometer to Gray converter that employs lower number of transistors This will only convert the thermometer code into gray code, but does not take care of sparkles. So instead of checking only if the current bit is 1 and the next bit is 0, in a bubble corrector, it is checked if the current bit is 1 and the next 2 bits are 0. This is implemented using a 3-input NOR gate and two inputs same as the previous case the 3 rd input as the actual value of the 2 nd bit as shown in Fig 5.4. Fig 5.4 Thermometer to gray code converter with sparkle error correction This circuit has one inherent slow path and two fast paths and hence care is taken so that the circuit value is read only when the slow path has settled. A buffering stage can 94

115 also be used in case timing the signals is tough. Buffering would require a differential amplifier and the output being obtained from the non-inverting end. Fig 5.5 shows an input sequence of thermometer code that is provided to the thermometer to gray code converter that is generated by controlled voltage sources. The inputs are such that they are the outputs generated from the comparator and latch string for an increasing ramp signal given as the ADC input. Fig 5.6 shows the output of the thermometer to binary code converter. Each color in the output corresponds to an output. The output simulation shows how the code converter works correctly. Only one input is high at any given time and also that bit corresponds to the highest level comparator that is turned high by the input. Fig 5.5 Input given to the thermometer to binary code converter 95

116 Fig 5.6 Output of the thermometer to binary code converter for input as in Fig 5.5 The NOR gate used in the thermometer to binary converter is implemented using transistors as shown in Fig 5.7. The 3 input NOR gate is implemented using transistors as shown in Fig 5.8. Fig 5.7 Transistor level implementation of a 2 input NOR gate 96

117 Fig 5.8 Transistor level implementation of a 3 input NOR gate Fig 5.9 shows a test simulation run setup having the inputs shown. Fig 5.9 Input to the 3 input NOR gate 97

118 Fig 5.10 Output of the 3 input NOR gate for the input as in Fig 5.9 The NOT gate implementation in transistor level is shown in Fig V out being the complement of V in. This is used in the thermometer to binary code converter. The response of the inverter is shown in Fig Fig 5.11 Transistor level implementation of the NOT gate used in the converter 98

119 Fig 5.12 Input (orange) and output (blue) of the NOT gate in Fig 5.11 The simulated results for the bubble corrector are shown in Fig The input to the code converter is as in Fig These are simulation results that are obtained when a sine wave that is not a harmonic of sampling frequency is applied to the ADC. Each color in each figure represents a different output. 99

120 Fig 5.13 The thermometer code that is output from the string of comparator and latches for a sine wave 100

121 Fig 5.14 Output gray code for the input as in Fig 5.13 The outputs of the gray code converters are such that no two outputs are high at the same time and the high output corresponds to the comparator output that is high. This verifies the working of the code converters. 101

122 5.1.2 FAT Tree Encoder The duty of the FAT Tree Encoder is to convert the gray code in to the corresponding digital code. The block diagram representation in Fig 5.1 shows the operation of the FAT Tree Encoder. It is also the last stage of the ADC in this thesis. However, more digital circuits such as the digital signal processing units that collect the digital data and synchronize them correctly can also be found in converters. The operation of converting the gray code to binary data can be performed by using ROMs or PLAs. However, the same function can be modeled and implemented using the digital gates when the number of bits is small [15]. This implementation is called as the FAT Tree Encoder. The FAT Tree Encoder provides faster and efficient conversion with lower power consumption [15]. The FAT Tree Encoder for a 3 bit Flash ADC is extracted from [15]. The gate level implementation is shown in Fig

123 Fig 5.15 Gate level implementation of FAT Tree Encoder as in [15] The delay from the input to the output for all the bits is the same since the signals pass through the same number of gates from input to the output. This is important as this prevents any meta-stability errors from occurring. Though the method shows that the digital components can be used to produce the desired result, it does not take into account the number of transistors that the implementation requires. The same circuit can be modified to work with NOR gates and NAND gates. The implementation resides on the DeMorgan s Law that: 103

124 This reduction is beneficiary as this has a lower number of transistors in the implementation and additional inverters are not required. This saves power and model still works efficiently with a good enough fan out. The system has a lower latency in this implementation as there are fewer gates the signal has to pass through. This is also essential in case of sub-ranging flash converters. Thus the FAT Tree Encoder is modified as in Fig Since this implementation using the DeMorgan s Law avoids an inverter at each stage, this avoids the usage of 2 transistors per gate and hence reduces the total number of transistors from 48 transistors to 32 transistors and this would result in lower power consumption and chip area. Also, since the number of gates the signal passes through is reduced, the propagation is faster, hence latency can be reduced. 104

125 Fig 5.16 Modified implementation of FAT Tree Encoder with low power, delay The NAND gate implementation at the transistor level is given in Fig The simulated waveforms for the FAT Tree Encoder are shown in Fig This output is generated when the inputs are as in Fig 5.5 for the thermometer to gray code converter. 105

126 Fig 5.17 NAND Gate implementation at transistor level for the FAT Tree Encoder Fig 5.18 Output of the FAT Tree Encoder when inputs to the Thermometer to gray code converter are as in Fig

127 The functioning of the digital components is the same for both stages of the sub ranging ADC since they operate on the same voltage levels as they are digital components. Hence, the same set of components can be used for the second fine stage of the data converter. The signal has to pass through 4 gates while propagating from the latch output to the FAT Tree Encoder output. The total delay experienced is 1.2ns. 5.2 Conclusion Chapter 4 deals with the analog components of the ADC, it shows how the analog value is converted to crude digital representations. Chapter 5 discusses how this crude digital representation is then converted to actual digital code used universally. It also discusses the design techniques that are used to make the system robust against errors and implementations of digital components that are power efficient and have low latency. These however take place in two sections in a sub-ranging converter, namely the LSB and MSB processing sections. Chapter 6 discusses how the interface between the two sections of the converter is done. 107

128 CHAPTER 6 PIPELINE COMPONENTS OF CONVERTER Chapters 4 and 5 discussed the analog components and the digital components of the flash converter that convert the analog data into the corresponding digital data. The conversion takes place in two steps, first the coarse data is converted into the most significant bits, these bits are fed to a digital to analog converter and the resulting analog value is removed from the analog input data and then the resulting value is then fed to the finer ADC and the least significant bits are obtained. This is shown in Fig 6.1. This kind of operation is known as sub-ranging. Chapter 6 discusses the sub-ranging components. Fig 6.1 Conceptual operation of the subranging operation 108

129 6.1 Modified Sub-ranging Usually, the DAC is followed by a subtractor and then the finer analog value is amplified by an amplifier so that the conversion is better and easier. In this work however, instead of having a subtraction followed by amplification, the reference voltages between which the analog value lies is found out and then split into finer divisions using the resistive interpolation technique. This method saves power spent on amplification. However, the comparators need to be sensitive enough to detect the small variations in the signals. As discussed in Chapter 5, the current pumping technique improves the sensitivity of the comparator for it to be used in this method. The conceptual operation of the pipeline components is shown in Fig 6.2 Fig 6.2 Conceptual operation of the modified sub-ranging flash converter used in the thesis The initial reference is generated using the resistance ladder network that works on the principle of the resistive interpolation technique. This reference is then selected and the correct reference level is propagated to the second level. This is similar to the 109

130 Kelvin DAC[32] but modified to prevent loading issues as discussed in the following sections Analog multiplexer Since the voltage level that needs to be propagated to the second stage is an analog value, an analog multiplexer is needed. Such multiplexers can be developed using differential amplifiers with a unity gain in them[34]. However such systems require careful design and also they require more power than the systems that use the principle of pass transistors. The transmission gate or the pass transistor is a set of NMOS and PMOS connected in parallel to each other as shown in Fig 6.3. The transistor by itself is a switch and connects the output to the input by using a select signal. However, the NMOS conducts low voltages very well but poorly conducts high voltages (close to V dd ) and vice versa for the PMOS transistor. Hence using both transistors in parallel ensures that all voltages are conducted well. Fig 6.3 Pass gate transistor level implementation The arrangement is non-restoring, meaning that the stage does not force any external signal onto the signal that is being passed, but only passes it or stops it based on 110

131 the select signal. This property is disadvantageous for digital circuits, but, is very essential in case of the analog multiplexers and is utilized in this work. The transmission gates can be connected in such a fashion that they pass the input value based on a select signal. This arrangement is based on the principle of the Shannon theorem, but extended to the fact that it can also be applied to analog signals to pass on the values needed. However, the node would be left floating rather than being driven to high or low as in digital circuits. Hence care is taken while using them for analog multiplexers. The passgate is a symmetric device, the output takes the value of the input and vice versa depending on the strongest driver. Since the reference in propagated to the gate of a comparator, the strongest driver becomes the resistive interpolation network. However, when multiple outputs are connected together and only one of the passgates is conducting, a voltage is still propagated from other transistors, which are very small, but still enough to cause offsets of the voltage reference. Hence, the outputs are shorted in two halves, the upper half and the lower half as shown in Fig

132 Fig 6.4 Reference selector composed of analog multiplexers 112

133 The correct half is selected using a select signal. This operation is similar to the operation of a multiplexer. The circuit that is used for the multiplexing operation is shown in Fig 6.5. The bits that are obtained from the thermometer to binary code converter is used, the higher half of the bits are ORed together and are given as the select signal to the multiplexer. Since if the signal does not lie in the upper half of levels, it has to lie in the lower half, the lower half need not be considered and just checking the upper half of signals is enough. The multiplexer requires a select signal and the inverse of the select signal to properly pass the correct signal to the output. Thus this requires an OR gate and the inversion of the OR output. Instead, the number of transistors can be reduced by connecting a NOR gate and an inverter. This saves two transistors in implementation. More than the number of transistors, the latency is reduced. 113

134 Fig 6.5: Implementation of reference propagator, multiplexer A second set of a reference propagator is used with the reference voltages one step less than the other. This selects the level below the level of the reference selected by the other reference generator. Again, the same select signal is used for the multiplexer to select the correct half from which the reference voltage has to be propagated from. Supporting simulation images are shown in Appendix A. Figs 6.6,7 show such outputs for easy reference. 114

135 Fig 6.6: A case of output of the analog multiplexer Fig 6.7 A single case of the outputs of the reference selector 115

136 An interesting test condition for the reference generation is the ramp signal. When the ramp signal is provided to the ADC, the response of the reference generator must be two stair case signals that closely follow the ramp signal and the ramps being V lsb apart. The system is tested with a decreasing ramp and the output is shown in Fig 6.8. Fig 6.8 Stair case response of reference propagator to a decreasing ramp Fig 6.8 shows the generation of the reference voltages and how the sampled signal lies in between the references generated by the reference propagator. It is intuitive that when a ramp signal is applied to the ADC, the reference propagator generates a step response which is characteristic of DACs, justifying the proper operation of the reference propagation and the theory. 116

137 6.1.2 Delays Operating at 2.5 GHz and 250 MHz input frequency range, the system is extremely sensitive to delays. At 2.5GHz, a clock phase is only 200 ps broad and at 250 MHz, the sine wave cycle is 4 ns broad. Since the system employs pipeline architecture, the LSB parts of the system receives the correct values for operation later than the MSB processing parts. Hence, for a finite amount of time, the LSB sections would operate on erroneous signals if suitable delay compensation is not introduced. Further more, since the constraint of meeting a 250 ps rise time requires extremely low capacitances and resistances at the output nodes of circuits, the number of input gates or transistors that the output is attaching to must be as close as possible or be compensated using capacitances. Since the system is sensitive to delays that are experienced by the signal in the MSB processing parts and up to the reference propagation stage, it is important to exactly know the delay that the signal experiences and compensate it accordingly. To find the worst case delays, the various systems discussed so far are tested for the worst case rise time and the simulation results are shown. Fig 6.9 shows the delay that the delay a comparator introduces. Fig 6.10 shows the delay the FAT Tree encoder introduces. Fig 6.11 shows the delay the reference generator introduces. Delay totals to 1.2 ns. 117

138 Fig 6.9 Delay introduced by a comparator: 0.5 ns Fig 6.10 Delay introduced by the FAT Tree Encoder: 0.5ns 118

139 Fig 6.11 Delay introduced by the reference generator: 0.2ns The sum of the individual delays gives a handle on the total delay but the total delay can be seen accurately by matching the sample and hold output and the reference propagation output by simulations as shown in Fig 6.8. The total delay hence measured is 1.2ns. This represents latency in the system. This problem can be overcome by providing the input to the second stage of the converter but with a delay equal to that needed to have the correct references coming out of the reference generator. The introduction of the proper delay for the second stage is done by introducing a delay in the input and performing the same operation of sampling 119

140 again on the delayed signal again to obtain the exact signal but with a delay in it. Though better methods exist, this method is quick to implement and the systems are well matched which greatly lowers the time to design and implement. The delay on the input signal can be done using delay interpolation stages as described in [34]. This method of interpolation is well suited for the sine waves which are used in this work. The delay depends on the RC time constant at each output stage of the delay interpolator. In this work, it is assumed that the delayed signal is available for operation. In this work, the second stage performs the sampling operation again to produce the sampled signals for the second stage. Fig 6.12 shows the first and second sampling operations of the signal. Fig 6.12 Comparison of the instantaneous and delayed samples 120

141 Fig 6.12 shows that there are no variations in the output of the sampling operation after delay. This is predictable as the system developed in the thesis is a time-invariant system and the sampling output does not change when the input provided to the system is delayed in time. This property is essential for the system developed which otherwise would result in the system being erroneous with the latency that exists in the system. The latency of the system is predicted very well with these estimates. Such an estimate is required so that when the input given is a periodic input such as the sine wave, then the delay need not accommodate for the repetitions of the wave and the cycle for which the output is being drawn can be correctly computed. With this in hand, the exact delay of the stages can be computed using simulations. 121

142 6.2. Conclusion Chapters 4 through to 6 developed the components of the ADC at the transistor level and produced supporting simulations to prove the theories developed and to characterize the components. Further analysis is provided in chapter 7 along with some attempts at quantising the developments and also analyses of the responses of the systems in different cases are analysed. 122

143 CHAPTER 7 DISCUSSION OF RESULTS Innovative concepts pertaining to the theories of voltage pulling and current pumping have been developed in this thesis and their applications to the sample and hold amplifier and the comparator and latches respectively in Chapter 4. This has been the core focus of the thesis. Later on, small improvements to the FAT Tree encoder, reference propagation have also been developed in Chapter 5. All these developments have been applied to build a complete ADC and the system has been shown to work well enough using the supporting circuits from Chapter 6. This chapter pertains to the developments that have been made in this thesis and an elaborate analysis of the behaviour of circuits and the reasons to their behaviour. Though the analysis cannot be complete and very accurate, it is still a good first step to quantisation of the phenomena. 123

144 7.1 COMPARATOR AND LATCHES COMPARATORS AND LATCHES Quite an amount of results have already been presented in Chapter 4 and some have been repeated here for ease and relevance. The introduction of the current pumps to the comparator provided a three fold advantage, first the speed was doubled using them, second the sensitivity was increased using them and third, it provided the ability to switch them on and off which in turn led to the ability of digitally switching between low power and high speed modes using the same design. As already discussed in chapter 4, the current pumps also have gates and there are wiring capacitances that are associated with them that load the output rails of the comparator. This loading effect however is compensated by the current pumping action of the inverter configuration. However, when the current pumps are not pumping any current as when during the non-comparison phase of the clock signal, the pass gate that is connected between the output rails sees the capacitance of the inverter and the capacitance of the current pumps. Plus, the inverter configurations do not settle at the same potential during this phase. This causes a larger difference between the output rails. There is a small potential difference between the common mode potentials of the output rails of the comparator. This is seen in Fig

145 Fig 7.1 Plot of response of the comparator showing a mismatch in common mode voltages This difference in potential can be neutralised by using larger sized transistors in the pass gate. This is true even when the size of the comparator transistors is increased; it requires a larger pass gate transistor sizing. This in turn loads the output of the comparator and this reduces the speed of the comparator. The effect is also seen when the current pumps are not isolated by using the pass gates and the current pumps are digitally turned on as shown in Fig 7.2. The green lines represent the response when the current pumps are turned off and red lines represent the response when the current pumps are turned on. 125

146 Fig 7.2 Comparison of common mode voltages when the current sources are turned on and off Quantisation of current pumping technology The current pumps rely on the fact that the mismatch of the currents flowing in the output rail is fed to the output rails of the comparator and latch of the comparator. Thus for the correct amount of the current to flow according to the control voltages, the transistors must be sized properly according to the conductivities of the technologies. The current flow according to the control voltage is shown in Fig 7.3. The current must be exactly matched when the control voltage is exactly midway between the supply voltages. This is required because, when the control voltage is exactly between the supply voltages, the output rails of the transistors are exactly at the midpoint of the supply 126

147 voltages which happens during the non comparison phase of the clock. In this case, the current pumps do not pump any current to imbalance the setup. This control voltage is hence used to compute the exact ratio of sizing of the transistors by equating the mismatch current to be equal to zero. The ratio of Bp/Bn is found as 2.61 for the TSMC 0.18u used in the thesis, however, the equation is only a handle on judging initial sizes of transistors but simulations are required to measure the ratio exactly. This is because the equation does not incorporate the secondary effects such as channel length modulation or the mismatch due to the different threshold voltages. Further the switching PMOS transistor in the current pump raises the V th of the PMOS causing a higher mismatch between the threshold voltages. The plot of the mismatch current and the control voltage is plotted in Fig 7.3.The absolute value of the current has been plotted. This follows the square law and the zero point is found around 0.6 V. x-axis is the voltage. 127

148 Fig 7.3 Plot of mismatch current in an inverter Equation also suggests that as the size of the current pump transistors increase, more current flows to the output rails. Hence, this suggests that the speed would be increased correspondingly. However, this has two disadvantages; the first being the obvious increase in capacitance which requires enlarging the transistor sizes on the rails. The second is the loss of sensitivity. The inverter pairs begin to dominate if their sizes become larger than the output rail transistors. This must be compensated by using larger transistors for pulling to the common mode voltage. The sweep of the ratio of the transistors is shown in Fig 7.4, where the result shows the higher number of cycles the comparator takes to produce the right polarity as the size increases. 128

149 Fig 7.4 Sweep of transistor sizes of the current pumps showing lowering of sensitivity when current pumps begin to dominate due to excessive sizing Switching Transistor The CMOS inverter pair forms the current pumps to the comparator. The switching of the current sources digitally is performed by the PMOS transistor at the top of this pair. This PMOS pair remains in the triode region always. The current from the transistor when it remains in the triode region is governed by the equation: Hence the current is dependent upon V ds. In case the output stabilises, the current is nearly zero because the V ds across this PMOS is zero and this saves power. However when the output is charging towards a rail, the inverter output is mid way between the 129

150 supply rails, in this case, the Vds of the top PMOS is non-zero and it conducts current and this current ends up pumping the parasitic capacitances. Thus, the PMOS switch acts to save power when the current pumps are not needed and also provide the digital switching function. The response of the inverter when a resistance exists at the output is almost a slope and not the normal drastic change between the two values, hence, as long as a different control voltage exists, the inverter output will not have a drastic change as and this causes a finite Vds to exist across the switch transistor. This allows for conduction of current by the transistor; once the value has settled down to the supply voltages, the current reached zero and conserves power. The converter that has been constructed has a constant offset of 10 mv. This arises from the offset that is present in the comparator. 130

151 Fig 7.5 Response of the string of comparators to a ramp signal Fig 7.5 shows a string of comparators in a reference ladder with each reference 225 mv higher than the previous one. However, the comparators do not recognize the voltage difference when the difference is within 10 mv of each other. This leads to offsets that are not desirable. Often these offsets are corrected or accounted for later in the digital processing circuits. The main criterion in that case is that the offset remains constant. 7.2 SAMPLE AND HOLD AMPLIFIER The sample and hold amplifier for the circuit has been adapted from [34] where the circuit performs as a phase detector. The circuit has been modified to perform the 131

152 sample and hold operation and the speed of the amplifier has been increased by using the voltage pulling technique and results have already been portrayed in Chapter 4. The circuit performs very well when the inputs are not of too low a frequency, since the inputs are being provided to the gates of the transistors. Problems are encountered when the input is not a signal with frequency content. To overcome this effect, a separate SHA with a switch capacitor circuit was implemented as in Chapter 2 to obtain the common mode voltage after low pass filtering and then added to the sampled signal to produce correct values when DC values are used. However, the circuit has been shown to outperform other circuits when sampling high frequency signals. 7.3 OVER SAMPLING RATIO OF CONVERTER In the current work, the maximum input frequency is 250 MHz and the sampling rate is 2.5 GHz, hence the OSR is 5. This allows the anti-alias filter a transition band of 895 MHz with the 3 db cut off at 250 MHz. This is not too stringent for the filter. 7.4 ANALOG INPUT RANGE The ADC that is used in this case is a differential converter, with an input range of 1.4 V. This is advantageous in the sense that this increases the dynamic range of the converter and provides a good power supply rejection ratio (PSRR) since the peak values are dependent on the supply voltages that the converter is receiving. However the error can be minimized by proper buffering of the supply voltages before they are supplied to the converter. 132

153 7.5 RESOLUTION OF THE CONVERTER The converter developed has a resolution of 6 bits. Along with a voltage supply of 1.8V, this translates to 1.8 / (2^6) which is mv, which is the quantization step. 7.6 POWER CONSUMED The power consumed is measured in the two settings, namely the low power and high speed mode. Fig 7.6 shows the current consumed by the ADC in the high speed mode. The voltage supply is at 1.8 V. The average current consumed by the converter is approximately 15mA including the spikes in the current which are caused due to the swings in the comparator and current pumps. This leads to a power consumption of 27mW. In the low power mode, the current is about 10mA, the main reduction is in the spike levels of the current as this is where the current pumps are acting. This gives a power of about 19mW which translates to about 30% reduction in the power consumed. 7.7 SIGNAL TO NOISE RATIO The frequency plot of the converter output has been shown in Figs. 7.6 and 7.7. The waveform has been manually converted to bits and the FFT algorithm has been run using Matlab and the output has been obtained. According to theoretical calculations, the SNR of an ADC is given by: SNR = N + 10log(OSR) Where N is the number of bits of the converter and OSR is the oversampling ratio. Thus for the converter developed, the SNR can be estimated as: SNR = *6 + 10log(5) = 44 dbc 133

154 Fig 7.6 Plot of the frequency spectrum of the output of the ADC Fig 7.7 Frequency spectrum of output showing the noise floor 134

155 The SNR of the ADC is thus: = 39 dbc 7.8 SFDR The spurious free dynamic range (SFDR) is calculated using Fig 7.6 and Fig 7.8. SFDR = = 47 dbfs Fig 7.8 Frequency plot showing the maximum amplitude of the spur 7.9 DNL AND INL TESTING As discussed in Chapter 3, the ADC is tested for the static parameters by giving it a ramp input and observing the output bits. Here the results that are obtained for the three bit ADC has been produced. 135

156 Fig 7.9 shows the response of the ADC to the ramp input. The blue stick graph represents the output. The black line connects the midpoints of the LSB and the MSB. The red line shows the connection between the midpoints of the consecutive output bits. This line represents the deviation of the response of the converter from the ideal response. Fig 7.9 Comparison of response of ideal converter with the implemented converter 136

157 7.9.1 Differential Non Linearity As discussed in Chapter 3, the DNL is measured by using a ramp input and the response of the ADC after reconstruction of signal is shown in Fig The DNL plot of the converter is shown in Fig Fig 7.10 Reconstructed output of the analog to digital converter 137

158 Fig 7.11 Differential Nonlinearity plot of the converter Integral Non Linearity As discussed in Chapter 3, the INL is computed from the DNL using the summation function. The INL is shown in Fig

159 Fig 7.12 The Integral Nonlinearity plot of the ADC. The INL is not more than 1 bit and the DNL is always less than 0.5 LSB, this ensures that the ADC is monotonous always. 139

160 7.10 Conclusion The chapters so far have dealt with the transistor level implementations of the ADC and also the developments and analyses. Chapter 8 deals with the layout level implementation of the components of the ADC. This level of implementation of the ADC components is required to extract the parasitics to get a better estimate of the responses of the chip. 140

161 CHAPTER 8 LAYOUTS The chapters so far have discussed the ADC starting from the block diagram description through to gate level, transistor level descriptions. Various simulations to support the theories have been reported. This chapter deals with the layout level description of the various components of the ADC. The building components of the ADC are the sample and hold amplifier, comparator and latches, opamps, nor gates, not gates and pass gates. 8.1 LAYOUT ISSUES The design cycle for the layout is to first generate the layouts of the transistors from the schematics, place them as close as possible while leaving enough space for the metal wires, contacts and also follow the design rules. Design rules can be found in most transistor level design literatures. Some good references are [38]. 141

162 8.1.1 Differential amplifier It is important that the transistors that form parts of the differential amplifiers are as close as possible, have a significant number of fingers and have as large an area as possible that is suited for the W/L ratio. These small measures ensure that the transistors are rightly matched and do not generate any errors. This is essential to have a good symmetry between the rails of the differential amplifiers or comparators. A good amount of symmetry is required as this ensures that the Common Mode Rejection Ratio (CMRR) is held high which is essential for high speed circuits that are susceptible to noise [8]. A disadvantage of high speed circuits is that the circuit metal lines are close to the quarter wavelength of the clocking signals or such high frequency signals. Hence, they begin to radiate this signal and nearby metal wires in the chip pick up these signals. These act as noise and at times these may also act as correlated noise and may cause a lot of problem. But having signals processed as differential signals greatly reduces the effect of these noises due to their high CMRR [8]. A problem with the chips in which the analog and digital signals share the same chip is the digital noise that is picked up by the analog components. In these cases, proper layout with differential circuits of high CMRR helps lower the effects of these noises. Proper layout with the transistors as close as possible to each other is hence essential. Further, any metal wire comparable to the wavelength of the signals can be modeled as a distributed transmission line which has inductive and capacitive components. These components lead to slower responses of the circuits are called 142

163 parasitic capacitances. As for any distributed transmission line, longer the length of the transmission line, larger the parasitic elements and slower the response. If this parasitic capacitance then connects to a high resistance node, it leads to a RC product that is large. This in turn causes the 1/RC component to go low which results in a dominant pole at low frequency which causes the circuits to behave a low pass filter. Hence, it is essential that the components are as close as possible and metal wires are used sparingly. Fig 8.1 shows the layout of an op-amp that has been used in this thesis. Fig 8.1 Trial layout of the op-amp used in the thesis 143

164 The layout of this opamp is not the most efficient due to the following reasons. First, the transistors are placed far apart for their areas. This causes the variations of the parameters of the circuit to be very large and this looses reliability and lower CMRR. Second, since the transistors have been placed far apart, the wiring metals have to be long and this causes them to pick up a lot of interference noise. This also increases the parasitic capacitance at the nodes of the opamp. A better layout for the same op-amp is shown in Fig 8.2. Fig 8.2 Better laid op-amp 144

165 All the transistor sizes are the same, but since the layout is in a smaller area, the zoom level has been increased and the transistors appear larger. This layout is better compared to the first layout since the transistors are closer together and this gives a better matching of the components and produces higher CMRR. The metal wires are also very small and hence they pick up a lot less interference and have very low parasitics associated with them. Fig 8.3 (a) Optimised layout for the PMOS transistors 145

166 Fig 8.3 ( b) Optimised layout of differential amplifier transistor pairs Figs 8.3a, 8.3b show two optimized layouts for transistors that share the same source terminal, the drains do not have a contact as no outputs are drawn from them as in the case of the NOR gate in Fig 8.3a, just one drain contact suffices. In Fig 8.3b, the transistors are interlaid and this is considered the best way to lay differential amplifier transistors. The parameter variations are the minimum in this case. Once the layout has been obtained, a design rule is performed. This is performed using the Calibre interface kit. The errors that are reported by the Calibre DRC kit are 146

167 rectified until they do not report any layout errors. One error that can be ignored is the density error. Any chip must contain a minimum amount of metal in it. If the layout does not cater to this, then the layout engineer can ask the fabrication industry to fill some extra metal so that the required amount of metal is obtained. Fig 8.4 shows the DRC results. It reports only density errors that can be ignored. The Calibre interface kit can also be made to not show the density errors and show only the other results. Fig 8.4 DRC successful for the opamp layout 147

168 The DRC access a file from the Calibre library for the specific technology and then the rules such as minimum widths of components, minimum distance between wells, contact spacing etc of the layout are verified against the rules in this file. If no rule is violated, then the DRC returns a successful run. However, the DRC does not check for unintended short circuits or unintended open circuits. The checks for the connectivity are performed using the Layout Verification Schematic (LVS). First, a netlist for the layout is generated using the LVS toolbox. Then this netlist is fed as an input file for the LVS check. The netlist file is indicated by opening the layout from the schematic window and running the LVS from this layout window. The LVS toolkit then compares this netlist with the netlist that already exists for the schematic. If the netlists match, then the LVS returns a netlist match comment and a green smiley. Fig 8.5 shows the LVS netlists match for the opamp schematic and the layout. 148

169 Fig 8.5 LVS reports the netlists match Extraction of parasitic capacitances The parasitic capacitances can be extracted from the layout. The input capacitances of the gates of the transistors are automatically calculated from W/L and bias points in the schematic, but the parasitics depend on how the layout is done and hence the parasitics are calculated only after the layouts have been performed. This is called as parasitics extraction. These parasitics are then placed into the schematic and then the simulations are performed to make sure the results do not vary too much. If the 149

170 results are not satisfactory, then either alternate design techniques have to be selected or the layout has to be optimized and the process is to be repeated. The design process is hence an iteration of various optimizations. The layouts for the other components were also performed and the DRCs and LVSs were performed for each one of them, errors were rectified and checks were rerun until no errors were reported. 150

171 8.1.3 Comparator and latch Fig 8.6 shows the layout for the comparator and latch along with the current pumps, charge cancellation transistors and digital switch. Fig 8.6 Layout of the comparator and latch along with current pumps and pass gate For short lengths, poly, the material used to form the gates of the transistors, can be used as a conductor. This has been used to short the gates in transistors. An exception to this is when connecting the gate of the output rails of the comparator to the current pumps. A metal line must be used as this line has to conduct the mismatch current. 151

172 The layouts did not use any special technology and were aimed at the most commonly available technologies so that the design can be fed to any fabrication industry and is not dependent on a single expensive process. To cater to this need, the layouts are all single well processes. This translates to the fact that all the bulks of the NMOS transistors are connected to the ground and all the bulks of the PMOS transistors are connected to Vdd. In the layout process, 4 layers of metal and 1 layer of poly were used which is also quite standard. Up to 6 layers of metal are very common in literature Sample and hold amplifier Fig 8.7 shows the layout for the sample and hold amplifier. 3 layers of metal and 1 layer of poly was used in this layout. 152

173 Fig 8.7 Layout of the sample and hold amplifier Fig 8.8 shows the layout of the layout of the 4 input NOR gate. 153

174 Fig 8.8 Layout of a 4 input NOR gate Layouts can further be optimized by interlaying the transistors close together and also by interlaying them as shown in Fig 8.3. But these have to be laid out manually as they are not supported by layout synthesis tools. These optimizations along with other optimizations such as double ring guards which are used to protect against noises are left for future developments. 154

175 8.2 Conclusion The chapter discusses the layouts of the components of the ADC and the processes in the verification of the layout and design rule checks are shown. Further the extraction of the parasitic capacitances are shown. The post layout simulations are performed and the simulation results that have been shown in the previous chapters are shown. Chapter 9 discusses the work that can be extended and optimisation ideas that can be implemeted. 155

176 CHAPTER 9 CONCLUSION AND FUTURE DEVELOPMENTS The chapters so far of the thesis have been about the implemented work of this thesis. However due to constraints of time and resources, certain achievable or explorable concepts have been left out for future developments. These possible developments have been discussed in this chapter. 9.1 CONCLUSION The current work has two main theories developed namely current pumping and voltage pulling and were applied to the comparator and latch and sample and hold amplifier respectively and it is shown how the speed can be doubled by using these techniques. It was also shown how the speed and power of the comparator and latch and hence the ADC can be controlled digitally. A model ADC has been built with the comparators and latches and the sample and hold amplifiers. Since the power consumed by the comparator is the highest in a flash converter, the power reduction shows up as a 30 % reduction in the power consumed by the ADC. A detailed analysis of the comparator and latches with current pumping is provided and steps of analysis have been provided and supporting simulations have also been provided. 156

177 In the digital blocks, certain advancements have been made such as reference propagation and the power consumed and transistor count of the FAT Tree encoder and DACs have been reduced by considering the transistor level implementations of each of these blocks and optimizing them. The sub-ranging concept has been shown with these systems and supporting simulations have been shown. Measurements of interest have been made on the ADC that has been constructed and the system has been shown to perform satisfactorily. Corner simulations were performed on the ADC and the effects on the system are reported. Layouts have been laid for the converter and Design Rule Checks and Layout Verification Schematics have been performed with positive results. Simulations have been performed with parasitic capacitances and results have been shown. But no work will come to an end and hence in this work also there are some developments that could be carried over in future. Future advancements have been listed and certain ideas have also been portrayed for development in the next section 157

178 9.2 FUTURE DEVELOPMENTS Internal reference voltage setting The thesis uses the simple resistance ladder to derive the required voltage reference levels for comparison of the voltages. However, techniques have been developed such that the ratio of the sizes of the transistors can be different from being equal so that the comparator does not require an external reference at all and the reference voltages are developed internally by the comparators. This also has the advantage that the circuit would be differential completely and hence would have a very high CMRR which is very beneficial for high speed circuits. Also, these comparators save a lot of power by avoiding the resistance ladder Subranging The ADC in this thesis works on the sub-ranging principle. The second stage of the converter is fed the analog signal after the coarse bits have been converted to the corresponding analog value and has been removed from the analog signal. The remaining signal is then amplified and the value is converted to the corresponding finer bits. In this thesis however, amplification is not performed to conserve power, but the sensitivity of the comparators is increased. In future developments, it would be better if both amplification and increased sensitivity are present along with lower power consumption. This would result in a better SNR than currently available Multiple speed settings 158

179 The comparator and latch developed in this thesis along with the current pumps are available with two speed settings and two corresponding power settings. However, this can be extended to multiple speed settings and corresponding power setting by using multiple stages of current pumps and properly sizing them so that they correspond to exact binary values. The mismatch currents must be powers of 2 so that they are exactly as digital data. 159

180 9.2.4 Latency In the current work, the reference propagation works on the result of the gray code converter. This adds extra delay. Instead, if the reference propagation can be based on the outputs of the comparators, the latency would be greatly reduced Layouts Layouts have already been optimised from an area stand point and parasitic reductions, but are not tightly matched. Layouts can be improved such that the transistors are placed together for better matching and are inter laid. Double ring guards can be used to reduce clock propagation into other circuits Time Interleaving The converter has been developed with time interleaving and UWB applications as targets. The system works well for UWB systems with input bandwidth of 250 MHz and 6 bits of resolution. For time interleaving however, the multiplexers have not been developed, future works could incorporate this to provide a 5 Gsps 6 bit sub-ranging low power flash converter with multiple speed and power settings, which would be a good goal of future works Technology The current system has been developed with the 0.35um TSMC process with a 1.8V supply voltage. The aim was to develop the system in a 0.18um technology but problems were faced when this is referenced in Cadence, hence the supply voltages were kept at 1.8V but the system was developed using the 0.35um. If the 0.18um technology becomes available, the speed of the system has the potential to be increased 4 times. 160

181 APPENDIX A Output bits for the sine wave used for testing arranged from most significant to least significant bits: 161

182 162

183 163

184 Outputs of the ADC with the same sine wave tested for worst case slow-slowslow corner arranged from MSB to LSB: 164

185 165

186 166

187 Outputs of the ADC tested with the same sine wave but with fast-fast-fast corner: 167

188 168

189 169