An HCI-Healing 60GHz CMOS Transceiver

Transcription

1 An HCI-Healing 60GHz CMOS Transceiver Rui Wu, Seitaro Kawai, Yuuki Seo, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of Technology, Japan 0 of 30

2 Outline Motivation Hot-Carrier-Injection Issues, Prior Arts and Proposed Solution Proposed HCI-Healing 60GHz TRX Detailed circuit implementation Measurement and Comparison Conclusion 1 of 30

3 Wireless Standards 60GHz-Band Capability PDC LTE WiMAX UMTS 9-GHz band GSM WLAN DVB-T ISDB-T GPS Bluetooth UWB Frequency (GHz) 2.16 GHz 1.76 GHz 7.04Gbps/ch in 16QAM Channels of IEEE ad standard Freq (GHz) 2 of 30

4 Hot-Carrier-Injection Issue in CMOS (1/2) CMOS power amplifier Drain efficiency: η=p out /P DC V ds V ds,peak =2V DD V ds V ds,peak =1.5V DD V DD V DD Class-A η=50% t Class-A η=12.5% t Large V ds,peak HCI damage Small V ds,peak Low efficiency 3 of 30

5 I D (ma) Hot-Carrier-Injection Issue in CMOS (2/2) 80 V D =1.2 V HCI damage Stress cond. V D =2.4V V G =0.8V 1 hour V G (V) Lifetime: the time when I DS = saturation 4 of 30

6 Hot-Carrier-Injection Mechanism V S Gate oxide V G Generated defects: Trapped charges & Interface states I D V D I G n+ n+ [*Y. Leblebici et al., JSSC 1993] High field P-Substrate I sub Impact ionization Degrade V t, m n, g m, I D, and lifetime 5 of 30

7 HCI Issue in Advanced CMOS HCI aging E lateral V ds /L eff HCI issues more severe 6 V ds,peak for same V ds,peak /L eff HCI limited V ds,peak =1.35V* 4 2 Voltage (V) Nominal V DD ** Process node (nm) 0 10 [**ITRS2013] [*D. Stephens et al., RFIC 2009] 6 of 30

8 HCI Issues for 60-GHz Applications 2.4-GHz power amplifier 2.5 V 60-GHz power amplifier 1.0 V Thick oxide L=250 nm (I/O Tr.) f max =40 GHz Standard L=65 nm (core Tr.) f max =220 GHz 7 of 30

9 Summary of Prior HCI V ds V DD =0.7V V DD =1.2V P 1dB =10dBm Low V DD or Stack Tr. t Better lifetime Degraded output power, linearity and efficiency V DD =1.2V P 1dB =6dBm P 1dB =5dBm Low V DD * Stack Transistor** [*M. Tanomura et al., ISSCC 2008] [**A. Siligaris et al., JSSC 2010] 8 of 30

10 Power Combining Techniques P in,n PA1 I n PAn P out,n Power combining Output (combiner, antenna array, etc.) [*J. Chen et al., ISSCC 2011] PAE = P out,n P in,n PAE = n (P out,n P in,n ) Individual: Combined: I n V DD n I n V DD Compensate output power and linearity Deteriorated efficiency can not be improved 9 of 30

11 I D (ma) Proposed HCI-Healing Technique V D =1.2 V HCI damage HCI healing How? V G (V) Ultimate solution: Physically heal HCI damage 10 of 30

12 Proposed HCI Healing Mechanism (1/2) Damaged gate oxide V G V S V D V B n+ n+ p+ P-Substrate Damage mechanism: trapped electrons [Y. Leblebici et al., JSSC 1993] 11 of 30

13 Proposed HCI Healing Mechanism (2/2) V G 0V 2.2V V S V D V B n+ n+ p+ P-Substrate Possible solution: charge ejection 12 of 30

14 I D (ma) Measured HCI-Healing I D -V G Curves First HCI healing demonstration V D =1.2 V Fresh Damaged Healed Accelerated Meas V G (V) Stress cond. V D =2.4V V G =0.8V 1 hour Heal cond. V B =2.2V V G =V D =0V 1 second 13 of 30

15 HCI-Healing Function in Transistor First HCI healing transistor Floating source* & low drain bias** assisting ejection (memory cells) V G High voltage V H V G V S High Z Deep n-well V H High voltage V B High Z p+ V S E BG n+ n+ p+ n+ Ejection of the trapped n+ electrons E BD Deep n-well V D V B R [*T. Endoh et al., IEDM 1989] [**K. Miyaji et al., JJAP 2012] 14 of 30

16 HCI-Healing Transistor Module MIM TL V DD TL Equivalent circuit for 60-GHz operation V G 1.2 V V D V H V G V D V B V H Deep n-well Deep n-well Deep n-well V GT Equivalent circuit for HCI healing 15 of 30 V G V S High Z V H High voltage

17 HCI-Healing Power Amplifier (1/3) V DD Proposed HCI healing block V PA S 6 M p S 6c M n RF in V G6 V D6 RF out V H MIM TL TL 16 of 30 V GT

18 HCI-Healing Power Amplifier (2/3) Deep n-well V DD V G V S High Z V H High voltage HCI healing status V PA V G6 V D6 V DD M p V DD M n RF out RF in V H MIM TL TL GND 17 of 30

19 HCI-Healing Power Amplifier (3/3) V G 1.2 V V D od V H 60GHz operation status V PA GND V DD M p GND Deep n-well RF in V G6 V D6 M n RF out V H MIM TL TL 18 of 30 V DD

20 TX output RX input HCI-Healing TRX Block Diagram Direct Conversion 20GHz PLL+ 60GHz QILO Integrated HCI-healing function V H LNA Logic Gain control Power mgmt. HCI healing HCI-healing block PA RF Amp. RF Amp. 60GHz QILO 60GHz QILO RF Amp. RF Amp. I Mixer I Mixer Q Mixer Q Mixer BB Amp. BB Amp. 20GHz PLL Control signals 19 of 30 I+ I- Q+ Q- Ref. 40MHz Q- Q+ I- I+

21 Die Micrograph 2 mm TX out RX in LNA HCI PA RF Amp. & I Mixer RF Amp. & Q Mixer RF Amp. & Q Mixer QILO QILO PLL Logic 2 mm Standard 65 nm CMOS Block Area (mm 2 ) TX 0.79 RX 1.01 PLL 0.27 Logic 0.21 RF Amp. & I Mixer 20 of 30

22 Transistor TEG Measurements DC stress lifetime AC stress lifetime Stand-alone PA TEG P in -P out with healing AC stress lifetime with healing TRX Board EVM versus P out with healing 21 of 30

23 Lifetime t (s) 65 nm NMOSFET DC Stress Lifetime 1E E E Lifetime = 63 V DS =1.2V Stress condition V GS V DS E+04 V V DS E E+00 τ = K e b V DS * /V DS (1/V) V GS = 0.8 V [*E. Takeda et al., EDL 1983] 22 of 30 t

24 I DSat (%) 65 nm NMOSFET RF Stress Lifetime 100 Lifetime = 2 hours Freq.=100 MHz P out =11 dbm Stress condition V ds 10 V gs V ds V gs 1.2 V I DSat = A t n * 0.8 V 1 1E E E E Time (s) [*L. Negre et al., JSSC 2012] 23 of 30 t

25 P out (dbm) Measured P in -P out of the PA 12 9 DC Stress-AC Meas. Freq.=60 GHz V G6 =0.7 V 6 3 Symbols: P 1dB Fresh Damaged Healed Accelerated Meas P in (dbm) 24 of 30

26 I D6 (%) Measured Lifetime of the PA 1E E E AC Stress-DC Meas. Lifetime@10% 1.2 year Fresh Tr. Stress P out =7dBm Lifetime@10% 81.2 years 1E Healed Tr. Stress P out =7dBm 1E E+31E+41E+51E+61E+71E+81E+91E Time (s) 25 of 30

27 TX EVM (db) Measured TX EVM versus P out IEEE802.11ad MCS12(16QAM) specification 7Gb/s Fresh 9dBm Stress cond. 12.5dBm with V DD =1.5V (40hr) -24 Damaged 5dBm -27 Fresh Damaged Healed Healing cond. V B =2.2V 1sec Averaged TX Output Power (dbm) Healed 8dBm 26 of 30

28 60GHz TRX Performance Comparison Ref. CMOS Process Data rate (Modulation) P out /each PA (dbm) TX efficiency P out /P DC (%) HCI healing Core area (mm 2 ) Power Consumption Tokyo Tech [1] 65nm 10.56Gb/s (64QAM) 28.16Gb/s (16QAM) EVM = -21dB 2.8 NO 3.9 TX: 251mW RX: 220mW NEC [2] Panasonic [3] Broadcom [4] This work 90nm 90nm 40nm 65nm *Estimated from literature 2.6Gb/s (QPSK) 2.5Gb/s (QPSK) 4.6Gb/s (16QAM) 7Gb/s (16QAM) Chip area w/o PLL EVM = -19.6dB EVM = -23dB EVM = -21dB NO NO 5.7 TX: 133mW RX: 206mW w/o PLL TX: 361mW RX: 260mW TX: 1190mW 0.5 NO 26.3 RX: 960mW 16x16 array 3.9 YES 2.3 TX: 218mW RX: 188mW 27 of 30

29 60-GHz CMOS transceiver with HCI damage healing function by using charge ejection technique. 81-year lifetime without sacrificing the output power and efficiency The transceiver demonstrates an EVM of -27.9dB and can transmit 7Gb/s in 16QAM within 2.16GHz bandwidth. Conclusions 28 of 30

30 Acknowledgement This work is partially supported by MIC, SCOPE, MEXT, STARC, STAR, and VDEC in collaboration with Cadence Design Systems, Inc., Mentor Graphics, Inc., Synopsys Inc., and Agilent Technologies Japan, Ltd. 29 of 30

31 References [1] K. Okada, et al., A 64-QAM 60GHz CMOS transceiver with 4-channel bonding, IEEE ISSCC, pp , [2] M. Tanomura, et al., TX and RX front-ends for 60 GHz band in 90 nm standard bulk CMOS, IEEE ISSCC, pp , [3] T. Tsukizawa, et al., A PVT-variation tolerant fully integrated 60 GHz transceiver for IEEE ad, IEEE VLSI Circuits, pp , [4] M. Boers, et al., A 16TX/16RX 60GHz ad chipset with single coaxial interface and polarization diversity, IEEE ISSCC, pp , [5] Y. Leblebici, et al., Modeling and Simulation of Hot-Carrier-Induced Device Degradation in MOS Circuits, IEEE JSSC, pp , Vol.28, No.5, May [6] E. Takeda, et al., An empirical model for device degradation due to hot-carrier injection, IEEE Electron Device Letters, Vol.EDL-4, No.4, pp , Apr [7] L. Negre, et al., Reliability characterization and modeling solution to predict aging of 40-nm MOSFET DC and RF performances induced by RF stress, IEEE JSSC, Vol.47, No.5, pp , May of 30

32 References [8] A. Siligaris, et al., A 60 GHz power amplifier with 14.5 dbm saturation power and 25% peak PAE in CMOS 65 nm SOI, IEEE JSSC, Vol.45, No.7, pp , Jul [9] J. Chen, et al., A compact 1V 18.6 dbm 60 GHz power amplifier in 65 nm CMOS, IEEE ISSCC, pp , [10] K. Miyaji, et al., Zero additional process, local charge trap, embedded flash memory with drain-side assisted erase scheme using minimum channel length/width standard CMOS single transistor cell, Japanese J. Appl. Phys., Vol.51, pp.04dd DD02-7, Apr [11] D. Stephens, et al., RF reliability of short channel NMOS devices, IEEE RFIC, pp , [12] T. Endoh, et al., New design technology for EEPROM memory cells with 10 million write/erase cycling endurance, IEEE IEDM, pp , of 30