High Data Rate 60 GHz CMOS Transceiver Design

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1 High Data Rate 60 GHz CMOS Transceiver Design Akira Matsuzawa Tokyo Institute of Technology

2 Contents 1 Background and Motivation Development of High Data Rate 60 GHz CMOS Transceivers High Data Rate Circuits Design Basic Design Method for 60GHz CMOS RF Circuits High Speed and Low Power ADC Future Prospect of High Data Rate Wireless Systems Summary

3 2 Background and Motivation

4 Progress of data rate in 60 GHz band 3 Our lab. is developing high data rate wireless transceivers. 28 Gbps has been attained. Data rate [Gb/s] Univ. of Toronto NEC UCB SiBeam, CEA-LETI Panasonic Toshiba Year Tokyo Tech IMEC UCB Broadcom

5 60GHz bandwidth allocation on IEEE 802.ad 4 Totally 9 GHz can be used. The use of high # of bit can attain ultra-high data rate com. BPSK QPSK 16QAM 64QAM 1ch ch ch ch

6 Time for big data contents download 5/ GHz MM wave can transfer the DVD data within several seconds Estimated time for download 単行本 Boo k コンテンツダウンロード推定所要時間 LTE WiMAX A 社 FTTH B 社 FTTH 雑誌漫画 Magazine Comic 新聞 News Paper Audio 音楽 CD CD Visual 映像 DVD DVD Measured average effective data rate as of Jan WiMAX LTE FTTH (A) FTTH (B) 12Mbps 4Mbps 40Mbps 120Mbps Microwave, マイクロ UHF UHF MM-wave ミリ波モバイ Mobile ル Contents コンテンツサイズ size [MB] 2014

7 WiGig Usage Models 6 WiGig White Paper, Defining the Future of Multi-Gigabit Wireless Communications July 2010

8 7 Development of High Data Rate 60 GHz CMOS Transceivers

9 The 1st 60GHz transceiver on ISSCC 2011 Rx input LNA Direct conversion IMixer QMixer I+ I- 60GHz QILO Q+ Q- K. Okada, et al., ISSCC 2011 Two 60GHz QILOs with 20GHz PLL 20GHz PLL 8 Tx output PA IMixer QMixer I+ I- 60GHz QILO Q+ Q- PLL 36MHz REFCLK TX: 186mW RX: 106mW PLL: 66mW

The 1st 60GHz transceiver on ISSCC 2011 9 I MIXER LO BUFFER

10 The 1st 60GHz transceiver on ISSCC I MIXER LO BUFFER 11Gb/s (16QAM) 8Gb/s (QPSK) LNA Q MIXER Q. OSC. 4.2mm I MIXER LO BUFFER LO BUFFER Buf. VCO LPF PA Q MIXER 4.2mm QUADRATURE OSCILLATOR LO BUFFER 20GHz PLL 65nm CMOS Rx:3.8mm 2 Tx:3.5mm 2 PLL:1.2mm 2

11 The 2 nd 60GHz Transceiver on ISSCC 2012 RF and baseband chips have been developed RF front-end Analog/Digital BB 10 60GHz Rx 60GHz I 60GHz Q 20GHz VGA LPF VGA LPF ADC ADC Digital BB 6.3Gb/s 20GHz PLL BB PLL 60GHz 60GHz I LPF DAC Tx 20GHz Digital BB 6.3Gb/s 60GHz Q LPF DAC K. Okada, et al., ISSCC 2012

12 4.2mm The 2 nd 60GHz Transceiver on ISSCC 2012 Full transceiver has been developed. LNA I MIXER Q MIXER I MIXER PA 65nm CMOS (RF) PLL Q MIXER LO BUF. LO BUF. LO BUF. LO BUF. LO BUF. Q.OSC. Q.OSC. Logic 10Gb/s (16QAM) TX: 319mW RX: 223mW K. Okada, et al., ISSCC nm CMOS (BB) ADC(Ich) VGA VGA PLL ADC(Qch) RAM DCTR LDPC Digital BB DAC(Qch) DAC(Ich) LVDS(11ch) LVDS (11ch) 11 3mm Tokyo Tech SONY

13 The 3 rd 60 GHz Transceiver on ISSCC Direct conversion method is used for wider bandwidth and low power I *K. Okada, A. Matsuzawa., ISSCC 2014 Q RF amp. Control Logic TX Output PA Psat=10.3dBm RX Input LNA NF=4.2dB RF amp. I Mixer I Mixer I Q Mixer Q Mixer Q LO buf. 60GHz QILO LO buf. BB amp. (FVF-FVF-SF) 20GHz PLL 60GHz QILO

The 3 rd 60 GHz Transceiver on ISSCC 2014 13 Chip was fabricated in 65 nm CMOS technology 4.2mm TX BB in I MIXER LO BUF. TX out RX in PA LNA Q MIXER I MIXER & RF amp LO BUF.

14 The 3 rd 60 GHz Transceiver on ISSCC Chip was fabricated in 65 nm CMOS technology 4.2mm TX BB in I MIXER LO BUF. TX out RX in PA LNA Q MIXER I MIXER & RF amp LO BUF. LO BUF. Q.OSC. Q.OSC. Logic PLL RX BB out QMIXER & RF amp CMOS 65nm, 1Al+11Cu TX: 186mW RX: 155mW PLL: 64mW LO BUF. Area TX 1.03mm 2 RX 1.25mm 2 PLL 0.90mm 2 Logic 0.67mm 2

15 Chip with antenna in package 14 The 60GHz RF chip are mounted on the antenna in package

16 Chip measurement setup 15 Chip was measured with high speed measurement system Power supply Power supply Arbitrary Waveform Generator Oscilloscope RF board (TX mode) RF board (RX mode) 25-GS/s AWG 100-GS/s oscilloscope (33GHz BW) 14-dBi horn antennas

17 Channel ch GHz Measured result ch GHz ch GHz ch GHz ch.1-ch.4 bond Modula- 64QAM 16QAM tion Data rate 10.56Gb/s 10.56Gb/s 10.56Gb/s 10.56Gb/s 28.16Gb/s Constellation Spectrum The world s first 64 QAM has been realized The world s fastest 28 Gbps has been attained TX EVM -27.1dB -27.5dB -28.0dB -28.8dB -20.0dB TX-to-RX EVM -24.6dB -23.9dB -24.4dB -26.3dB -17.2dB

18 Performance comparison 17 Highest data rate with low EVM and power dissipation Data rate / Modulation TX-to- RX EVM Integration Power consumption SiBeam [3] 7.14Gb/s(16QAM) -19dB 65nm, 32x32-array heterodyne, TX, RX, LO TX: 1,820mW RX: 1,250mW Tokyo Tech [4, 5] 16Gb/s(16QAM) 20Gb/s(16QAM)[5] -21dB 65nm, direct-conversion, TX, RX, LO, antenna, analog & digital BB TX: 319mW RX: 223mW IMEC [6] 7Gb/s(16QAM) -18dB Toshiba [7] 2.62Gb/s(QPSK) N/A IMEC [8] 7Gb/s(16QAM) -15dB 40nm, direct-conversion, TX, RX, w/o PLL 65nm, heterodyne, TX, RX, LO, antenna, analog & digital BB 40nm, 4-array direct-conversion, TX, RX, LO, antenna TX: 167mW RX: 112mW TX: 160mW RX: 233mW TX: 330mW RX: 284mW for 1 stream Panasonic [9] 2.5Gb/s(QPSK) -22dB 90nm, direct-conversion, TX, RX, LO, antenna, analog & digital BB TX: 347mW RX: 274mW Broadcom [10] 4.6Gb/s(16QAM) -20dB 40nm, 16-array heterodyne, TX, RX, LO, antenna, analog/digital BB TX: 960mW RX: 1190mW This work 10.56Gb/s(64QAM) 28.16Gb/s(16QAM) -26dB 65nm, direct-conversion, TX, RX, LO TX: 251mW RX: 220mW

19 18 High Data Rate Circuits Design

20 Data rate in communication 19 Wider bandwidth and higher SNR are required to attain higher data rate Shannon s theory D rate BW log 2 1 S N Wider bandwidth Higher SNR Multi-cascaded amplifier Passive mixer circuit Injection locked I/Q oscillator 7 bit ADC

21 Effect of the gain flatness 20 Poor gain flatness makes ISI (Inter Symbol Interference) due to different gain for plus frequency and minus frequency.

22 Multi-cascaded RF amplifiers 21 Multi-cascaded RF amplifier can increase the gain flatness due to the distributed resonant frequencies. 4-stage PA MIM TL TL MIM TL to antenna 4-stage CS-CS LNA ESD protection from antenna W=1m x40 1m x40 2m x20 2m x20

23 Mixer circuit in TX 22 Passive mixer with resistive feedback RF amplifier can realize Widely flat impedance, rather than LC impedance matching method. Z ) 200// R 8 in( SW 2 Re Z RF LO Rf LO+ RSW 50 To PA Matching network ZRF LO- RSW RSW 200 Zin BB input Rf ZRF LO+ RSW 200 Zin

24 Measured gain of TX circuit 23 The gain flatness of 2 db is attained for the band width of 4 GHz. Gain [db] Frequency [GHz]

25 Required phase noise of IQ-VCO for 16QAM24 A phase noise of LT. -90dBc/Hz@1MHz is required for 16QAM systems A reported phase noise of 60GHz IQ VCO is at most Required CNR [db] K. Scheir, et al., ISSCC, pp ,Feb QAM 8PSK AM-AM of PA QPSK Phase noise 1MHz offset

26 Q of inductors and capacitor 25 Q of capacitor is rapidly degraded with frequency. Q of Less than 10 at 60 GHz at most. Low phase noise 60 GHz VCO is hard to be realized. Q switched capacitor 2nH inductor 8nH inductor Qc < 60GHz 0.2nH inductor Frequency [GHz]

27 Frequency Multiplier 26 (1) IF 4x RF for hetero-dyne TRX reasonable for PN and FTR (2) 12GHz 30GHz 20GHz 2x 48GHz (20GHz x 3, 15GHz x4 are OK.) (3) 90 o 0 o hybrid 90 o 60GHz 60GHz 0 o, 180 o 90 o, 270 o *S. Emami, et al., ISSCC GHz is too high for PN and FTR I/Q phase calibration is required. **C. Marcu, et al., ISSCC GHz QILO*** good for PN and FTR ***W. Chan, et al., ISSCC 2008

28 Injection locked 60GHz I/Q VCO 27 We have developed the injection locked 60 GHz I/Q VCO The 60 GHz quadrature VCO is injected by 20 GHz PLL In 60 GHz out Qn 20 GHz in VDD 20GHz matching block INJn INJp Ip 60 GHz out Qp A. Musa, K. Okada, A. Matsuzawa., in A-SSCC Dig. Tech. Papers, pp , Nov

29 60GHz Quadrature LO Design 28 36/40MHz ref. 20GHz PLL 2 PFD CP LPF *K. Okada, et al., ISSCC GHz QILO* (54,55,56,57 58,59,60) GHz PLL: 64mW 60GHz QILO: 18mW(TX)&15mW(RX) QILO frequency range: 58-66GHz Phase noise improvement by injection locking* 1MHz at 61.56GHz GHz 59.40GHz 60.48GHz 61.56GHz 62.64GHz 63.72GHz 64.80GHz

30 Injection locking technique 29 Injection locking technique is a very important circuit technique for high frequency signal generation and frequency divider. Phase noise of the oscillator is mandated by the injection signal. INJ P INJ N Output t Injection signal t parallel injection Phase noise PN ILO Locking frequency range PN f L INJ f o 2 Q 20 log( N I inj I OSC ) N: Multiple number N=3

Low phase noise can be realized 30 Quadrature injection locked 60GHz oscillator with 20GHz PLL Low phase noise of -96dBc/Hz @1MHz.

31 Low phase noise can be realized 30 Quadrature injection locked 60GHz oscillator with 20GHz PLL Low phase noise of Previous one is Best phase noise is achieved GHz, -96dBc/Hz-1MHz offset A. Musa, K. Okada, A. Matsuzawa., in A-SSCC Dig. Tech. Papers, pp , Nov

32 31 Basic Design Method for 60GHz CMOS RF Circuits

33 Gain and Noise; f max and f T 32 Gain and noise are mainly determined by f max and f T of Transistor Lower gain semi-log scale MAG is inversely proportional to the logarithm of the operating frequency f c. Higher noise log-log scale NF min is proportional to the operating frequency f c. 65nm NMOS W f =2.5μm, N f =32, V gs =0.8V and V ds =0.8V. G max f max f c NF min f f c T g m R g R s

34 f max Basic RF performances f max and f T of MOS transistor will increase continuously. Gain and NF will be improved by using future CMOS technology. G GaAs max f c CMOS InP f f c max NF min gm R g Rs Bulk CMOS Ultra-Thin-Body Fully-Depleted (UTB FD) SOI Multi-Gate MOSFETs f T f T CMOS GaAs InP ITRS RFAMS 2011.

35 Cross coupled feedback capacitors 34 Differential circuit Ccc Ccc Capacitance is cancelled C gd -Ccc Cross coupled feedback capacitors in a differential circuit can reduce the effective capacitance to increase the gain of 6dB at 60GHz. f f Max Gain[dB] max R g g m C gd /( C gs C This term is reduced T gd ) ( R w/ocross-coupledcap. w/ cross-coupled cap. 6dB up g r ch R s ) g ds C gd -Ccc Frequency[GHz] Y. Natsukari, et al., VLSI Circuits, Dig. Tech. Papers, pp , June W. L. Chan, et al., ISSCC. Tech. Dig., pp , Feb

36 Feedback signal and stability 35 Feedback signal is suppressed by the cross coupled capacitors and this increase the stability of amplifier. -10 Feedback signal 40 Stability factor S(1,2) [db] w/o cross-coupled cap. w/ cros-coupled cap Frequency [GHz] Stability factor w/o cross-coupled cap. w/ cros-coupled cap Frequency [GHz]

37 Development history of 60GHz circuits 36 Device modeling Trial & Error First 16QAM TRx ISSCC 2011 RF+BB ISSCC 2012

38 In-house PDK 37 PVT C MIM TL TL with L/T NMOS PMOS R RF PAD DC probe for ADS Varactor MIM MOS cap Each component is implemented as an in-house PDK for Agilent ADS.

39 Key technology: low loss TR line Optimized parameter and manually-placed dummy metal 2.5 realize low loss transmission line. 0.8dB/mm Manually-placed dummy metal GND signal(10m) gap(15m) GND dummy GND M1&M2 shield GND [db/mm] Z0 [ohm] manual auto ` Frequency [GHz] manual auto Frequency [GHz]

40 Basic amplifier design Amplifier design; accurate sizing, biasing, impedance matching and decoupling. 39 Z 0 =3 50, 0.8dB/mm 1st, 2nd stage 3rd, 4th satge MIM TL for dec. A several GHz oscillation will occur, if the feedback passes are made. Feedback pass Gain max Z out * Z out Loss min * Z in Z in Gain max Matching network Amp. 1 Amp. 2

Decoupling capacitor 40 A decoupling capacitor has been developed using MIM capacitor with distributed structure to prevent a resonance, Which occurs, if used a

41 Decoupling capacitor 40 A decoupling capacitor has been developed using MIM capacitor with distributed structure to prevent a resonance, Which occurs, if used a conventional capacitor structure. A very low impedance of 3 ohm is realized. Z0 [] Measurement Proposed Model Frequency [GHz]

42 Tile-based layout method Each component is previously measured and modeled. The same layout is utilized to maintain modeling accuracy. 5mm pitch 41 T-Junction Tr TL C L-Bend MIM TL RF PAD GND-Tile

43 In-house PDK 42 We have developed in-house PDK for 60-GHz circuit design for Virtuoso

44 Design Example 43 High design accuracy at around 60GHz has been attained TL MOM Cap. Tr. T-Junc. IN OUT Bend 10 8 S21[dB] Frequency[GHz] S11 (RED:meas BLUE:sim) S22

45 44 High Speed and Low Power ADC

46 7bit 2.2GSps ADC for 60GHz ABB 45 7bit ADC for the 16QAM modulation Convert the voltage difference to the timing difference Folding and interpolation are realized by logic gates M. Miyahara, A. Matsuzawa, ISSCC 2014 Ref ladder Resistive Averaging Coarse SR Latch Time-based Folder x 4 Fine Interpolated SR Latch Encoder D-FF x mm 0.25mm

47 V to T conversion in dynamic amplifier 46 Voltage difference can be converted to time difference in a dynamic amplifier. ΔV in V in1 V in2 T V V eff in T 0 V eff V GS V T V DD CLK V DD V oa V in1 I D1 g m I D2 g m C L C L V ob Voltage V oa V ob V DD /2 Logic threshold V in2 CLK T Dynamic amplifier Time T 0

48 Conversion from the voltage to the timing 47 The signal generation of larger voltage difference is faster in the dynamic amplifier. early signal V INP3 D P3 V INN3 V-T D N3 V INP2 D P2 V INN2 V-T D N2 V INP1 D P1 V INN1 V-T D N1 late signal L Dynamic Amps.

49 Signal folding in time-domain 48 Signal folding in time-domain can be realized easily by simple logic gates. AND: Select late pulse OR: Select early pulse D 1_1 =D N0 OR D P2 D 1_2 =D N4 OR D P6 (Mountain fold:select early) Delay Time D 2_1 =D 1_1 AND D 1_2 (Valley fold:select late)

50 Performance comparison 49 Highest SNDR of 37.4 db is attained in flash ADCs No calibration circuits are required. This ADC will contribute increase of data rate of 60 GHz transceivers. P d is large so far, however can be reduced by the optimization. ISSCC 2008 [3] VLSI 2012 [8] VLSI 2013 [9] This work Technology 90nm 40nm 32nm SOI 40nm LP Resolution [bit] Power Supply [V] Sampling Frequency [GS/s] Power Consumption [mw] [db] FoMw [fj/conv.-step] FoMs [db] Core area [mm 2 ] Calibration Off chip Foreground Off chip No need

51 50 Future Prospect of High Data Rate Wireless Systems

52 Link budget example of wireless system 51 Transmitted RF power is lowered so much at the receiver 6dBm(P out )-4dB(back-off)=2dBm Tx Signal Antenna gain:6dbi 60 GHz, 1.5 m for QPSK system -71.5dB(1.5m loss)+6dbi(tx)+6dbi(rx) Noise -3dB(loss) +6dB(NF) Rx Required CNR: 9.8dB -60.5dBm Signal CNR +14.0dB -74.6dBm Noise -80.6dBm=-174dBm(kT)+93.4dB(2.2GHz-BW)

53 Calculations 52 Calculate the data rate as function of career frequency and Tx power Shannon s theory D rate BW log 2 1 D rate BW S N log 10 SNR 0.3 BW SNR( db) 3 Received signal P RX ( db) P TX B OFF G AT G AR I L S LOSS Spatial loss Noise S LOSS P n c 4 20log 20log 20log df 4d 4dfc c ( dbm) log BW d: distance f c : career frequency NF c

54 Estimated data rate 53 There is an optimum frequency for the maximum data rate. Higher Tx power is required to increase the data rate. 16 QAM looks the best to attain the maximum data rate. Data rate (Gbps) Solid line: consider the SNR Dashed line: neglect the SNR Pt=20dBm Pt=10dBm 64QAM 16QAM QPSK BPSK Distance:1m Antenna gain:6dbi NF: 6dB Back off: 4dB Power loss: 3dB Pt=0dBm Carrier frequency (GHz)

55 Future direction 54 Future direction should be chosen by the usage model High frequency and high power Best but very difficult!! High gain antenna Sharp beam High frequency but low power Fixed point only! Medium frequency but high power Low gain antenna Short distance only! Reasonable high data rate Reasonable long distance

56 Our roadmap for 300Gbps data transfer 55 Data Rate [Gbps] Wider BW larger N MIMO 56Gbps 42Gbps 28Gbps 328Gbps 7Gbps 10.5Gbps 16QAM 64QAM

57 Summary High data rate wireless communication is demanded 28 Gb/s has been realized Wider bandwidth and higher SNR are the keys Multi-cascaded amplifier Passive mixer with resistive feedback Injection locked I/Q oscillator 7 bit ADC with time domain processing Accurate RF modeling and measurement up to 100 GHz is fundamentally important Optimum frequency for the maximum data rate. - Higher frequency does not guarantee the higher data rate - Higher Tx power is required to increase the data rate. Future direction should be chosen by the usage model Long distance with reasonable data rate Short distance with high data rate D rate BW log 2 1 S N 56

58 Acknowledgement 57 I would like to thank Prof. K. Okada and this work was partially supported by MIC, SCOPE, MEXT, STARC, Huawei, Canon Foundation, STAR, and VDEC in collaboration with Cadence Design Systems, Inc., Synopsys, Inc., and Mentor Graphics, Inc., and Agilent Technologies Japan, Ltd. And also,

59 Acknowledgement Thanks lot to students Murakami(ILO) Musa(PLL) Yamaguchi(ILO) Okada Bu(LNA) South Bldg. 9, 5F cleanroom 58 Sato(VCO) Asada(PA) Han(modeling) Minami(TRx) Bunsen(Rx) Matsushita(Tx) +W. Chaivipas, N. Li, N.Takayama, S.Ito, Y.Nomiyama

Technology Trend of Ultra-High Data Rate Wireless CMOS Transceivers

2017.07.03 Technology Trend of Ultra-High Data Rate Wireless CMOS Transceivers Akira Matsuzawa and Kenichi Okada Tokyo Institute of Technology Contents 1 Demand for high speed data transfer Developed high