Future Directions in. December 12, 2008 Boris Murmann Murmann

Transcription

1 Future Directions in Mixed-Signal IC Design December 12, 2008 Boris d Murmann Mixed-Signal Group

2 Growth ~2050 Source: European Nanotechnology Roadmap 2

3 Business as Usual? ~100x Source: European Nanotechnology Roadmap 3

4 Murmann Mixed-Signal Group 4

5 Research Overview (1) Digitally Assisted Data Converters MEMS/Sensor Interface Electronics 5

6 Research Overview (2) Bio-molecule detection Neural signal acquisition 6

7 Research Overview (3) [Subramanian] 7

8 Specific Examples Minimalistic pipeline pp ADC Using a previously unknown amplification mechanism Digitally corrected track-and-hold circuit Analog-digital co-design Offset-calibrated Osetca ated accelerometer e ete Electro-mechanical co-design Analog circuit design using organic thin film transistors Designing analog circuits using lousy technology 8

9 Pipeline ADC V in S/H STAGE 1 STAGE N-1 STAGE N R bits (e.g. R=1) V in 2 R V res A/D D/A V res D D=0 D=1 V in 9

10 Stage of a Conventional Pipeline ADC V in φ1 k V res φ1' φ2 Flash ADC k φ1' φ1 φ2 V refp,n thermometer to binary D Power goes here 10

11 Inefficiency of Class-A Amplifiers I bias V DD I load Time V SS 11

12 The World s Most Efficient SC Amplifier (?) [Hu, Dolev & Murmann, VLSI Symposium 2008] 12

13 Settling in Amplify Phase V DD Amplify - V gs + V g Gate Floating V out C load 13

14 Amplification Principle gs in DD gs t out gd gs gb gd gs gb load bias Incremental Gain C + C + gs C' gd gd C gb 14

15 Basic Amplifier Modifications Sample Add C gs,ext in parallel l to C gs for gain control C gs,ext V bias V DD Amplify Add I bleed during amplify phase C gs,ext V out C load Gate Floating I bleed 15

16 Impact of I bleed (Simulation) Bleed current small, about 5μA 16

17 Pseudo-Differential Stage 17

18 Stage Schematic DD,ref ref,accum ,2 gs,ext dac,pos dac,neg in,pos out,pos load bleed V in,neg to gate of negative e half circuit 2e 1 dac,neg dac,pos 18

19 Testchip Architecture Target 8-9 bits of resolution STAGE 1 STAGE 2 STAGE 13 STAGE 14 parator ut CM Com Ou 1-bit per stage Reduced radix (G=1.7) for offset tolerance Digital gain calibration [Karanicolas, 1993] 14 stages, no scaling Calibrated output encoded to 10 bits 19

20 Prototype ADC UMC 90-nm CMOS process 0.123mm 2 (excluding off-chip reference generators) 9.4 bits (685 levels), f s = 50MHz 20

21 SNDR vs Input Frequency f s = 50 MHz At low f in SNDR = 49.4 db ENOB = 7.9 bits SNDR degrades by 1.7 db at high f in 21

22 INL and DNL 9.4 bit resolution (685 levels), f s = 50 MHz DNL = +0.4/-0.4 LSB INL = +1.3/-0.9 LSB 22

23 Power 1.44 mw at f s = 50 MHz 0.49 mw amplifiers and biasing 0.95 mw comparators and clocks At f s = 50 MHz, only 9% of power is static 23

24 Comparison and Outlook Work in Progress 24

25 Driver Application [TI] Medical ultrasound Want to implement 64+ high speed ADCs on a single chip Approach Minimalistic, digitally assisted pipeline ADC Exploit specific signal and system properties! 25

26 Received Signals Are Highly Correlated Phantom Image of Kidney Received Signal Traces Time (s) x

27 Typical Heterodyne Receiver LPF ADC I BPF LO1 BPF +90 LO2 LPF ADC Q Analog Digital 27

28 IF Subsampling Receiver LPF I BPF LO1 BPF ADC +90 LO2 LPF Q Analog Digital Need ADC with high linearity at IF input frequencies 28

29 SFDR of Typical CMOS ADC National ADC14155: 14bit, 155 MS/s, 1.1 GHz Bandwidth A/D converter 29

30 Achieving High SFDR (1) BiCMOS front-end $$$ BJTs used as buffer for linear signal tracking and sampling Can achieve SFDR>90dB up to 4th Nyquist zone at 125MS/s A.M.A. Ali et al. A 14 bit 125 Ms/s IF/RF Sampling Pipelined A/D Converter, IEEE CICC, Sep

31 Achieving High SFDR (2) Compensate nonlinearities by applying inverse nonlinear function to the digital output Roy Batruni, Issue: complexity, power Linearizer SFDR Power 1 W Power 1.5 W SFDR ~20 db Frequency (MHz) 31

32 Judicious Modeling During tracking mode, the track-and-hold can be modeled as an RC circuit with an input dependent resistance V V R th = V R R + in C ( + 1 2) 1 = R 1 ( V in ) = μ C n ox dv C dt w ( V l gs 1 out V th ( V in, V ( Vin, Vtop ) = Vth0 + γ ( ϕ0 + ( Vin, Vtop) ϕ0 ) top )) Flip-around track-and-hold circuit V in ( k) = V out At the sampling instant 2 out ( k) + ( a0 + a1v ( k) + a2v ( k) +...) out dvout ( k) dt nonlinearity memory Nikaeen & Murmann CICC

33 Digital Processor Diagram D out, ADC ADC CLK Bandpass Filter Coefficients bp1 bp2 Interpolation bp3 bp4 bp101 bp102 bp103 bp104 Vout(n-4 t 0 /T s ) Vout(n-3 t 0 /T s ) Vout(n-2 t 0 /T s ) Vout(n- t 0 /T s ) Vout(n-1) Vout(n) bp4001 h 6 h 2 h 1 bp4002 bp4003 bp4004 Upsampling factor =100, t 0 =Ts/100 h 12 h 8 h 7 h 18 h 14 h 13 h 0 Nonlinearity correction Distortion model coefficients: h 0,h 1,,h 18 D out, corrected 33

34 Hardware Requirements The algorithm was implemented in Verilog and synthesized using standard CMOS cells in 90nm Technology 90-nm CMOS Clock speed 155 MHz Latency 33 clock cycles Number of logic cells 61,339 Area 0.54mm 2 Power ADC power (ADC14155) 52 mw 967 mw 34

35 Measured Results th Nyquist zone without digital enhancement with digital enhancement 85 SFDR (db) input frequency (MHz)

36 SFDR Comparison SF FDR (db) state of the art CMOS ADCs 50 BiCMOS ADCs This work f (MHz) in 36

37 MEMS Accelerometer CMOS Capacitance change ~10 ff/g Desired resolution ~10 mg for airbags and ESP Must resolve capacitance changes of ~100 af Problem: Drift in parasitic bondwire capacitance 37

38 Sigma-Delta Interface Mechanical a IN F m mech 2 1 x ms + bs + k C x C V VOut VDig A C V M. Lemkin and B. E. Boser, A three-axis micromachined accelerometer with a CMOS position-sense interface and digital offset-trim electronics, IEEE J. Solid-State Circuits, vol. 34, pp , April

39 Offset Offset due to bond wire deformation C Offset a IN m F mech 1 x C x 2 x ms + bs + k C V A Lead C V S/H Compensator Force- Balancing Drifts over time Indistinguishable from DC acceleration 39

40 Linear Feedback System with Two Inputs y 1 x1 + x2 f f 1 a 40

41 Spring Constant Modulation The output due to C off can be modulated to higher frequencies by modulating k V Out F mech 1 FB + C Off k + k ~ C FB x C Off a IN m F mech 1 ~ k + k x C x x C V A Lead C V S/H Compensator Decimator V Out FB 41

42 Spring softening effect No electrostatic force F Mech F Elec F Elec With electrostatic force Larger displacement than expected F Mech Q 2Q 2Q Q Can be used to modulate spring constant 42

43 Time-Multiplexed Feedback Phase 1 Phase 2 Spring constant modulation Sigma-delta force-balancing MOD Force-Balancing MOD Force-Balancing T T 43

44 Simulated Output Spectrum 0 Power/frequenc cy (db/hz) db -46 db -89 db DC Acceleration 91m/s^ m/s^2 9.1 m/s^2 Offset Capacitance 0fF 10 ff 50 ff Frequency (MHz) Currently working on IC prototype 44

45 The Future? 45

46 Organic Semiconductors Pentacene [Klauk] Mechanically flexible Suitable for solution processing Cheap to cover large areas Make disposable devices 46

47 Organic Transistors [Klauk] 47

48 Displays (1) Sony's 1,000,000:1 contrast ratio 27-inch OLED HDTV 48

49 Displays (2) 49

50 Sensor Applications Atifi Artificial i skin T. Someya, JSSC 2005 Chemical sensor V. Subramanian, ISSCC

51 Jelly Fish Autonomous Node 51

52 Organic Circuit Design Challenges Poor mobility 1.00E-07 Vds = -10V Age degradation Bias stress effects Device-to-device variations -Ids (A) 1.00E E E E sec Dielectric leakage 1.00E Vgs (V) To date, very little work on analog circuits using organic transistors 52

53 Work in Progress: ADC using OTFTs VIN Sample & Hold Comp SAR Logic VREF Clock VDAC Clock 30 mm DAC n-bit output Leverage experience from Si-CMOS to create a robust OTFTdesign 53

54 Summary Mixed-signal IC design is no longer business as usual Expect less return from pure scaling of decade-old circuits Time to become creative Many opportunities for innovation fall into the cracks between traditional boundaries of analog & digital, circuit & algorithm, mechanical & electrical partitioning Trend toward More than Moore will likely bring diversification of device technologies MEMS/NEMS, large area device technologies, novel sensor devices, 54

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