Digitizing the Analog World: Challenges and Opportunities

Transcription

1 Digitizing the Analog World: Challenges and Opportunities April 5, 2010 Boris Murmann Murmann Mixed-Signal Group

2 Murmann Mixed-Signal Group 2

3 Research Overview Biomolecule detection MEMS Sensor interfaces Digital enhancement algorithms Spin-Valve Transducers, Antennas, Cables,... Signal Conditioning Signal Conditioning A/D D/A Signal Processing Neural prosthetics Medical ultrasound High-performance and lowpower A/D and D/A converters 3

4 Research Examples High-performance A/D converters Neural prosthetics MEMS accelerometers Large area electronics 4

5 Digitally Assisted A/D Converters Additional digital processing for performance enhancement Signal Conditioning A/D Analog Media and Transducers Signal Conditioning CLK D/A Signal Processing Analog Digital 5

6 ADC for a Digital Serial Link No analog error accumulation and better scalability Need efficient high-speed ADC, typically > 10GS/s 6

7 Time-Interleaving Popular way to increase ADC throuhgput 1 text ADC 1 2 ADC 2 X(t) Y[n] N ADC N 7

8 Imperfections Mismatches result in signal distortion Gain Offset Timing Skew V off_1 text 1 G 1 ADC 1 V off_2 2 G 2 ADC 2 X(t) Y[n] V off_n N G N ADC N 8

9 Our Focus: Timing Skew (2-channel example) 1 2 9

10 Skew Calibration Using Extra ADC Statistics-based skew measurement in digital backend Correction through analog adjustments 1 2 ADC 1 X(t) ADC 2 Y[n] 1 2 N ADC N Digital Backend Clock Cal ADC Cal Digitally adjustable delay cells 10

11 Timing of Auxiliary ADC Phase 1 2 N Cal ADC 1 X(t) 2 ADC 2 N N ADC N Y[n] Digital Backend 1 2 Clock N Cal ADC Cal Cal 11

12 Calibration Scheme For each channel, adjust delay cells until correlation between calibration ADC output and each slice are maximized ADC Cal can be 1-bit and slow R( ) 1 ADC 1 2 X(t) ADC 2 Y[n] 1 2 N ADC N Max Clock Cal ADC Cal 12

13 Removed pre-publication slides on experimental results 13

14 MEMS Accelerometer Capacitance change ~10 ff/g Desired resolution ~10 mg for airbags and ESP CMOS Must resolve capacitance changes of ~100 af Problem: Drift in parasitic bondwire capacitance 14

15 Sigma-Delta Interface Mechanical a IN m F mech ms 2 1 x bs k C x C V A Lead C V S/H Compensator V Out Decimator V Dig Force- Balancing M. Lemkin and B. E. Boser, A three-axis micromachined accelerometer with a CMOS position-sense interface and digital offset-trim electronics, IEEE J. Solid-State Circuits, vol. 34, pp , April

16 Offset Offset due to bond wire deformation C Offset a IN m F mech ms 2 1 x bs k C x C V A Lead C V S/H Compensator Force- Balancing 16

17 Linear Feedback System with Two Inputs x 2 x 1 + _ a + b y f 1 1 y x1 x2 f af 17

18 Spring Constant Modulation The output due to C off can be modulated to higher frequencies by modulating the spring constant k 1 k k VOut Fmech COff FB C FB x C Offset a IN m F mech ms 2 1 x bs k C x C V A Lead C V S/H Compensator Force- Balancing 18

19 Spring softening effect Acceleration Spring Acceleration Spring Electrostatic Can be used to modulate spring constant (k) 19

20 Modulation through Multiplexed Feedback a IN m F mech ms 2 1 x bs k C x C AC V V S/H Int Com Decimator V Out k m x PULSE f k Time-Multiplexed Electrostatic Force MOD Force-Balancing MOD Force-Balancing T T 20

21 Power/frequency (db/hz) Output Spectrum with 1-Tone Modulation db -46 db -89 db DC Acceleration 9.1 m/s^2 9.1 m/s^2 9.1 m/s^2 Offset Capacitance 0 ff 10 ff 50 ff Frequency (MHz) 21

22 Output Spectrum [db] Pseudo-Random Modulation -20 Modulating spring-constant with a pseudo-random sequence Frequency [Hz] 22

23 Feedback signal [x10-15 ] Parameter Convergence 1.2 Closed-loop system - Feeding back capacitance Coff=0fF Coff=0.01fF Coff=0.1fF Coff=1fF Time [Sec] 23

24 Chip Design in Progress D Out FPGA Correlator Decimator MEMS CMOS C to V Integrator Compensator Quantizer V Out State- Machine Clk Electrostatic Feedback k-modulation V Ref Gnd Scan In/Out 24

25 Neural Prosthetics Cortical motor prosthetics Neurons in the motor cortical areas of the brain encode information about intended movement Courtesy K.V. Shenoy Courtesy L.R. Hochberg Nature Magazine June 06 25

26 Neural Signal Acquisition Electrode signals consist of multiple sources DC Offset, about 15mV from electrode/tissue interface Local field potential (LFP), 3mV peak, 10Hz to 100Hz Spikes from nearby neurons, 35μV 1mV peak, 500Hz to 5kHz Courtesy M. Sahani Courtesy C.L. Klaver 26

27 Specs Separate the fast and slow signal acquisition for DR Custom front end design for each path Spikes Local Field Potential Gain 600 V/V 200 V/V Lower Cutoff 300Hz 1Hz Upper Cutoff 10kHz 1kHz Input Referred Noise (total from sampling node) 2.0µVrms 1.0µVrms in Hz Total Power (96x Array) 3mW 100µW 27

28 Spike Path Front-End SAR ADC Input Cap Input Stage Output Buffers SC Bandpass Filter 28

29 Sampling Phase Integrate signal current on C B and sample High-pass for DC block using C ac and R big (offresistance) A 1 contains a pole that helps minimize noise folding 29

30 A1 Implementation Details I TAIL I<< I TAIL M 1a M 1b V outp V outm V B2 V B1 Flicker noise reduction Anti-alias for thermal noise from M 1a,b 30

31 Static Power 31

32 Two-Channel Interface Pixel SAR ADC Frontend 32

33 Die Photo (96 channels, 5mm x 5mm) 33

34 The Future? 34

35 Organic Semiconductors Mechanically flexible Suitable for solution processing Cover large areas at low cost Make disposable devices 35

36 Jellyfish Autonomous Node 36

37 Jellyfish Bell Prototype (Virginia Tech) A bio-inspired shape memory alloy composite (BISMAC) actuator A.A.Villanueva, et al., 2010 Smart Mater. Struct (17pp) 37

38 Want to Make Plastic ADCs! 38

39 6-bit A/D Converter Prototype Substrate Glass Interconnect Ti/Au evaporation, litho, wet etch Gate electrodes Al evaporation, shadow masking Source/Drain Au Evaporation, shadow masking Dielectric 5.7nm AlO x /SAM PFET DNTT, ~0.5 cm 2 /Vs NFET F 16 CuPc, ~0.02 cm 2 /Vs Area 28mm x 22mm Component count 74 W. Xiong, U. Zschieschang, H. Klauk, and B. Murmann, A 3V, 6b Successive Approximation ADC using Complementary Organic Thin-Film Transistors on Glass, ISSCC

40 ADC Schematic Calibration enables 6-bit precision despite poorly matched capacitors Output To DAC SAR Logic (off-chip) Calibration DAC V REFN V V REFP MID C-2C structure possible due small stray caps (glass) DAC with Sampler C/32 C/32 C/32 Comparator... Bit 0 Bit 1 Bit 2, 3, 4 Bit 5 C C 2C C 2C C Input V REFN V REFP V REFN V REFP V REFN V REFP V REFN V MID... Main DAC 40

41 Comparator Auto-zeroing cancels threshold voltage drift CLK CLK CLK CLK CLK CLK CLK CLK C S1 C C S2 C S3 C S4 F1 C F2 C F3 C F4 + - Input Output Anti-parallel PFET/NFET layout minimizes variations if C F due to misalignment Wp = 500um Wn = 500um Lp = Ln = 20um C S1 = 1.1nF A 0 = -7.8 = 3.0ms Transmission Gates: Wp = Wn = 100um Lp = Ln = 20um Wp = 400um Wn = 400um Lp = Ln = 20um C S2 = 1.1nF A 0 = -9.8 = 4.0ms C gdp Wp = 400um Wn = 400um Lp = Ln = 20um C S3 = 1.1nF A 0 = -9.8 = 4.0ms Wp = 100um Wn = 300um Lp C= gdn Ln = 20um C S4 = 1.1nF A 0 = = 16.4ms 41

42 INL (LSB) DNL (LSB) Measured DNL/INL 4 Before calibration, 100 Hz clock rate Code Code 42

43 INL (LSB) DNL (LSB) Measured DNL/INL 1 After calibration, 100 Hz clock rate Code Code 43

44 Organic ADC Summary Process Minimum feature size Chip area Resolution Full-scale range Max DNL / INL Clock rate / Update rate Power consumption 3 metal complementary organic thin-film 20 mm 28 mm x 22 mm 6 bits 2 V -0.6 LSB / 0.6 LSB 100 Hz / 16.7 Hz V 44

45 Conclusions Mixed-signal IC design remains a vibrant area of research Changing boundary conditions Ever-increasing need for higher performance, lower power New applications New device technologies A recurring theme in our research Looking for new ways to overcome analog imperfections using DSP and calibration 45