Next Mask Set Reticle Design

Transcription

1 Next Mask Set Reticle Design 4.9mm 1.6mm 4.9mm Will have three Chip sizes. Slices go through completely the re;cle. 1 1mm x 1mm die per reticle 8 1mm x 4.9mm die per reticle mm x 4.9mm die per reticle 1.6mm

2 RASP 2.9 IC family RASP 2.9a: Generic FPAA Block (expanded RASP 2.8a) RASP 2.9b: Generic FPAA Block with reduced routing blocks RASP 2.9c: Bio FPAA (expanded RASP 2.8b) RASP 2.9d: Sensor FPAA (expanded RASP 2.8c) RASP 2.9e: Selective Programming FPAA RASP 2.9f: Adaptive FPAA RASP 2.9j: Adaptive FPAA #2 RASP 2.9g: Neuron FPAA RASP 2.9h: FPAA + Filterbank RASP 2.9i: Clean FPAA

3 RASP 2.9 IC family RASP Chip Name 2.9a 2.9b 2.9c 2.9d 2.9e Iden1fica1on Generic FPAA Block (expanded RASP 2.8a) Generic FPAA Block with reduced routing blocks Bio FPAA (expanded RASP 2.8b) Sensor FPAA (expanded RASP 2.8c) Selective Programming of Regions FPAA Project Lead Degs + Basu Csaba, Basu, Craig 2.9f, 2.9j Adaptive FPAA Stephen, Basu 2.9g Neuron FPAA Shubha, Richie 2.9h FPAA + Filterbank D. Graham 2.9i Industrial Strength FPAA Keep chips as pin compatible as possible (base on RASP) Want an updated FPGA if possible

4 RASP 2.9a Generic FPAA block expanded RASP 2.8a to 4.9mm x 4.9mm ~ 100 CABs CAB design similar to 2.8a (no specialized blocks) Small fixes to programming / interface circuits (e.g. on-chip counter, SPI interface)

5 RASP 2.9b Simplified Routing Generic FPAA CAB Block with reduced routing blocks. All local routing + bridge switches between routing. Routing infrastructure is easier. Speed comparison for different problems. Do we have more delay from switches ( O(n 2 ) ) versus longer capacitance lines (O(n) ) Is this architecture better for using switches as computation elements, particularly in arrays Questions: Need confidence that bridge elements are working well

6 RASP 2.9c BioChannel FPAA Modification of RASP 2.8b. Routing architecture like RASP 2.9a. Questions: More data on RASP 2.8b helps

7 RASP 2.9d Sensor FPAA Modified RASP 2.8c chip Some thought needed to protection of the input pins

8 RASP 2.9e Simultanious Run + Prog Want to selectively program one FPAA region(s) while rest of the chip is operating. - Used for dynamic changing of an FPAA algorithm while running - opens up possibilities for self-test in the chip compilation Requires simultanious run mode and program mode; need prog mode by chip regions Need HiV swiching for tunneling in each block

9 RASP 2.9f: Adaptive FPAA pfet protection switches. - Set of switches with separate Vdd and guard rings, well at 3.3V. - all routed signals out of CAB in supply line. - no signals above signal Vdd throughout routing main routing fabric. Need High voltage transistors to connect internal (to CAB) signals and Inj Vdd - nfet switches (tunneling turns on) - Does not inject with high source voltages (Richie, Degs?) connect Vtun line through amplifier - analog output control - need amp for all tun lines grouped together in CAB - Need override so can tunnel whole chip FG devices in CABs should have multiple transistors - adaptive filter applications - neural synapse applications RASP 2.9j: Similar, but with modified CAB topology and no protection switches or HV transistors

10 RASP 2.9g: Neuron FPAA Digital Axon Inputs Soma Digital FPGA routing Digital Axon Inputs Dendritic routing (analog routing fabric) Digital Axon Inputs Neuron Block Digital Axon Inputs FPAA blocks in FPGA routing. FPAA routing is dendritic line. Analog programmable space. Perimeter fabric are synapses Soma includes digital conversion, potential circuitry for learning, and nearest neighbor coupling (WTA style)

11 RASP 2.9g: Neuron FPAA Neuron communication is mostly local (95% inputs from local connections) Digital FPGA routing Local connections through FPGA fabric - embeds memory with selection - speed is not high (like 5-10kHz range) (so simple routing) - have dedicated lines to connect to nearby chips (still local, maybe buffered) left, right, up and down Neuron Block Global AER Addressed for longer connections (AER). - A few dynamic routing lines for inputs (typically <100k events / second, 1000 neuron chip; simple 1-switch routing) - lines can route to long distance outputs - short axon pulse width Uncertain whether to include adaptive support

12 RASP 2.9h: FPAA + Filterbank Modified RASP 2.9a IC with a filterbank specialized block at the input Chip looks like a modified RASP 3.0 architecture (roughly x n CABs) Filterbank elements put on one 4.9mm x 1.4mm test die as well.

13 RASP 2.9i Clean FPAA IC What is needed for a clean FPAA chip: Improved IC interface - interface with mostly digital control for programming - Minimize # of pins for control - interface to easily put multiple chips on a board ESD Protection for the Pads (possibility of modifying VIS standard pad set) On-Chip High Voltage Selection High Voltage Generation (potential Charge Pump Devices) -reduces ESD issues as well (no HV ESD concerns)

14 RASP 2.9j: Modified Adap;ve FPAA RASP 2.9f approach: - modified CAB structure - simplier routing infrastructure - important to see comparisons

15 Remaining options for FPAA chips Build a modified FPGA chip Build an FPAA with more WTA support elements for separable transforms (requires support on time integration) Build an FPAA with GMM support Build CABs with multiple input addition (FG or non-fg). Gives support for MITEs with routing elements. Build a test cell bank (maybe integrate into an FPAA) having short-term analog memory blocks. Build an FPAA with on-chip DACs / ADCs - Could be programmable DACs, (8-bit ok, 10 bit is better) - Do we need full DAC, or just digital infrastructure and use routing elements (digital registers)?

16 Timeline of things Week of 10/5: Architecture discussions Week of 10/12: Initial IC layout, particularly RASP 2.9a Week of 10/19: Further layout, revising architecture discussions Week of 10/26: FPAA workshop at GT week (might have circuit level design review that week) Tapeout in November (should avoid golden week in Tawain in Jan)

17 Dynamic Analog Two-Port Memory Output Vector Signal Input (could be block scanned) Digital Control Shift Register Ck Input Clock 1 Ck Memory for modifying video format for computation (also good for comm apps) Shift Register Output Digital Control could be random access, etc.

18 Dynamic Analog Two-Port Memory Key is developing the memory cell (large # of elements) - size must be minimized (# of transistors, cap sizes, same well) - power minimized - non-destructive read (good two port operation) - minimize charge feedthrough, if possible Input speed set by input R of the two switches (~ 40kOhm) 100fF load cap time constant is 4ns 50MHz sampling VT mismatch of read transistor and input charge feedthrough are main errors Vdd Vdd Column Drain Output 2 Column Drain Output Column Select1 Row Select1 Column Source Row Select 2 Bias GND GND (could be diffusion capacitor) Column Source Output 2