An Smart Transducer Readout Circuit for Multi-parameter Sensor System

Transcription

1 An Smart Transducer Readout Circuit for Multi-parameter System Te-Hsuen Tzeng, Yu-Ying Chou, Yu-Jie Huang, Yu-Hao Chen and Shey-Shi Lu, Senior Member, IEEE Abstract A smart transducer readout circuitry, which comprises a reconfigurable sensor interface and a low-power 10-bit SAR ADC, is reported as a linkage between a variety of sensors and a microsystem controller. The reconfigurable sensor interface circuitry supports high-resolution and diverse signal acquisition from capacitive, resistive, voltage and current type sensors with programmable control of gain and offset. Noise cancellation and nonlinearity compensation techniques are also employed to improve the signal quality. A low power 10-bit Successive approximation analog-to-digital convertor (SAR ADC) is also included in this readout to facilitate signal processing and data transferring. To achieve low power consumption, all the amplifiers used here operate in sub-threshold region for better current efficiency. This CMOS chip with die area of 1.6 mm x 0.9 mm was fabricated in standard TSMC 0.18um technology and dissipates only 16μW at 1V. to have higher efficiency, in this work, we propose an reconfigurable multi-sensor interface architecture, which can adapt to various types of sensor input signals and convert all kinds of input signals into voltage signals. It has the advantages of low cost, low power consumption, and high adaptability compared with the prior arts. Also, since the signals generated from most of MEMS sensors are voltage type, resistance type [], capacitance type [3-4], and current type [5], this interface is designed to process these four types of signals specifically. A low power 10-bit SAR ADC is also included in this work to facilitate following signal processing and data transferring. Index Terms Node, reconfigurable, readout, multi-sensor interface, SAR ADC. R I. INTRODUCTION ecently, in response to the aging society problems and the shortage of manpower on health caring, home health care becomes an important research topic. A miniature mobile device with biosensors, which can monitor physiological signal at anytime and anywhere, may bring us an effective and practical solution. In virtue of intra-body communication (IBC) platforms and current internet communication system, it is convenient for physicians to remotely monitor and analyze the physiological data recorded from a large number of patients. A promising physiological sensor must be low cost and easy to carry around. However, the output specifications of the sensor components in the market are not uniform, and even the output signals are in various types, such as ECG voltage signals, optical current signals, and capacitance signals of the humidity sensors. In order to make our sensor nodes could be compatible with most of the commercial sensors, the front-end sensing interface should be capable of coping with various types of sensing signals. Generally, multi-parameter sensing interfaces [1] are made by a combination of several single-type sensing interface circuits with a multiplex (MUX). However, it is accompanied with the increase of the hardware cost the and power dissipation. To enable our sensor system Manuscript received August 1, 01. This work was partially supported by the National Science Council, Taiwan (contract number: NSC E MY3). T.-H. Tzeng, Y.-Y. Chou, Y.-J. Huang, Y.-H. Chen and S.-S. Lu are with the Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan. ( tehsuen@gmail.com; j54967@gmail.com; molimo84@gmail.com; yuhaochen@ntu.edu.tw; sslu@ntu.edu.tw ). Fig. 1 Block diagram of the proposed transducer readout. II. SYSTEM ARCHITECTURE In this work, a smart transducer readout circuit for multi-parameter sensor system is realized in TSMC 0.18μm standard CMOS process. Cadence Circuit Design Software was used for related simulation. The whole system architecture is shown in Fig. 1. It is composed of a reconfigurable sensor interface circuit and a 10-bit successive approximation register (SAR) ADC, supporting high-resolution signal acquisition from voltage, resistive, current, capacitive type sensors. For an portable system, people always concern about battery life time and device size. Therefore, to realize features of reconfigurability, low power, and small die area, capacitive feedback technique are basically adopted in our readout circuit. In addition, the readout circuit must be considerably low-noise so as to cope with weak sensing signals. All these needs can be satisfied by using a switched-capacitor (SC) amplifier circuit with correlated double sampling (CDS) technique. Since the signals from human body are at very low frequency, SAR ADC is chosen to digitize our sensing signals for its low power consumption. Consequently, the digital sensing data can be processed and analyzed easily by the following digital circuits such as an digital processor.

2 A. The reconfigurable sensor interface circuit The reconfigurable sensor interface circuit is shown in Fig.. The first stage is implemented based on a differential-to-single-ended SC amplifiers with CDS technique. It also acts as an analog multiplexer for converting different types of inputs (C/R/I/V) into voltage output. The second stage is a 7-bit programmable gain amplifier, which has 17 different gains from 0 db to 40 db with proper digital gain selection. Rex Rex Iin + Vin - s Input Model Vin : Temperature Cex : Glucose Iin : ph Rex : Protein Reconfigurable Interface Cex C'1 C' C3 C'3 Programmable Gain Amplifier 7-bits Cap Array Δt Non-overlap Clock Fig. The schematic of the reconfigurable sensors readout. Several noise cancellation techniques have been reported. However, CDS can not only remove low-frequency noise but also some operation amplifier imperfects. After considering all tradeoffs ( performance, power, area, and etc.) into account, we choose the SC Amplifier with gain and offset-compensating CDS configurations to be our first stage, namely reconfigurable interface, which is shown in Fig. 3. C3 at the input terminals have no effect on the gain as long as they are matched. The input parasitic capacitors are quiet large because of the large input devices of the transconductance amplifier (OTA), which operates in sub-threshold region. The circuit operates as follows. During, the charges stored on C 1 are transferred onto C, whereas C 3 holds value of output (V out ). When is available, C 1 samples the voltage difference between the input and the negative input of the OTA (V n ), while is charged to the instantaneous voltage value at V n. C 3 is the feedback capacitor that keeps the output voltage of the OTA close to the value stored during the previous phase. The other sampling branch at positive input of the OTA is used for giving a reference voltage at V n through virtual short circuit and improving the symmetry of the circuit by mimicking the operations of the negative path. Its transfer function can be expressed by /. (1) V 1 (1 C C ) / A in 1 o In this work, the open loop gain of OTA is 110 db. According to the transfer function, the gain error effect of the front-end is nearly 0 db. It makes the output voltage extremely close to the ratio of C 1 /C. It is worth to mention that the gain ratio (C 1 /C ) in the reconfigurable interface is set to be unity. This is because that, in some sensing mode (C mode & I mode), the inputs have been magnified during the signal conversion. The sampling clock is set around 00 Hz owing to the system planning. The application scenario is that four types of sensors cyclically deliver their signals within 1 second, which means it takes 50 ms for single measurement. The second stage is a programmable gain amplifier (PGA) with a binary-weighted capacitor array, as depicted in Fig. 4. It is mainly used to improve the dynamic input range of this readout. We put the capacitor array at C 1 position to achieve programmable gain, which is directly proportional to capacitance value. The gain can be digitally selected from 0 db to 40 db with 17 different settings. C 3 64C 3C φ Fig. 3 The schematic of the reconfigurable interface circuit. Considering the frequency of the bio-signals is usually close to dc frequency, there is no requirement for the readout circuit to deal with high frequency signals by using broad bandwidth techniques. Even so, we learned that a broadband CDS needs additional capacitors on predict path for speed compensating. On the other hand, CDS technique supports differential inputs design which improves the symmetry of the circuitry. It is very useful feature for giving the circuit a better CMRR, which eliminates the non-ideal effect of CMOS switches, such as charge injection, clock feed-through. Also, parasitic capacitances V in φ 16C 8C 4C C C Fig. 4 The schematic of the OTA in the reconfigurable interface. The reconfigurable readout is able to handle all kinds of electrical entries thanks to the mechanism of the SC amplifier. Such signal conversion would be successful because the SC amplifier has two-phase operations. In sampling phase, different sorts of electrical signals would be converted into charge signals by using the front C φ V out

3 capacitor (C 1 ), and they would be transformed into voltage value through the capacitance (C ) in the next phase. It is clear that we convert signals twice through two separated phases. For this reason, this reconfigurable interface can adapt to all kinds of electrical signals. Fig. 5 exhibits the equivalent circuit in current mode operation. In current mode configuration, the current induced by the sensor starts to charge the front capacitor (C 1 ) until the SC amplifier goes to the next phase. The amount of charges transformed from the input current can be easily calculated by Q= i f in CLK. By setting the gain ratio (C 1 /C ) to be A L, we can get output voltage converted by the SC amplifier in next amplification phase, as the following equation. iin AL V () C f CLK Iin Fig. 5 The principle of the current mode operation. In capacitive mode, as shown in Fig. 6, the front capacitor (C 1 ) will be replaced by the capacitive sensor, and 3-bit resolution capacitors array will help the circuit to calibrate the output voltage at common mode voltage. The capacitance variation of the sensor can be figured out by judging the charge variance stored in the sensor. In fact, the output voltage is proportional to the capacitance difference between the capacitive sensor (C IN ) and the reference capacitance (C ref ). The output voltage generated by capacitance change of the sensor can be expressed as the following equation. CIN Cref V V. (3) C where ΔV = V DD -V. The equation (3) also suggests that the output voltage is linearly related to the capacitance variation of the sensor. φ 3-bit calibration array C C ref C Fig. 6 The principle of the capacitive mode operation. The equivalent circuit in resistive mode is shown in Fig. 7. To achieve the flexibility of reading out all resistive sensor configurations, a Wheatstone bridge interface has been developed. The Wheatstone bridge could produce an output voltage which is linearly related to the ratio of resistance value rather than the absolute resistance values, and it is also good for common-mode noise rejection. In this case, we formed the resistive sensors to be a configuration of Wheatstone bridge, and it will automatically convert the resistive variation to a voltage value. Its transfer function can be expressed by VDD R AL V R (5), where ΔR represents the resistance variation of resistive sensors, R is the reference resistor, and A L is the closed loop gain defined by C 1 /C. Fig. 7 The principle of the resistive mode operation. In the voltage mode, the circuitry is formed as a typical differential-to-single SC amplifier structure. The output voltage can be easily derived by V A V V (6) out L IN, where A L is the closed loop gain defined by C 1 /C. B. 10-bit successive approximation register(sar) ADC A successive approximation analog-to-digital convertor (SAR ADC) is used in this platform. Advantages of this architecture are low power consumption and small chip area. Fig. 8 shows the schematic of our 10-bit SAR ADC. This circuit consists a comparator, a logic controller, a set of registers, and capacitor array. The logic controller and registers form the logic control unit of SAR, while the capacitor array is used as a digital analog converter (DAC) to convert digital signals into analog voltage signals. The signal φ φ

4 will then be sent into the comparator for comparison. In addition, by using capacitor bridge technique, the die area of the capacitor array can be minimized. Fig. 8 The schematic of the SAR ADC DAC is the most important part in SAR ADC. A basic DAC can be built by resistor array structure or capacitor array structure. However, the resistor array structure uses larger area, spends more power and generates more noise. Therefore, we use capacitor array structure to design this low power DAC. III. MEASUREMENTS A. The reconfigurable interface circuit Fig. 9 shows the gain switching of the 7-bit PGA. As it can be seen, it is very linear, and the R is close to 1. Magnitude (mv) PGA Equation Gain V/V y = a + b Adj. R-Squa Value Standard Err B Intercept B Slope Fig. 10 (a) the measured result of capacitive mode. (b) the measured result of current mode. (c) the measured result of resistive mode. B. 10-bit successive approximation register(sar) ADC Fig. 11 shows the static performance measurement. As 100Hz sine wave was applied to the input, the maximum DNL is 0.54/-0.6 LSB, and INL is 0.87/-1 LSB. Fig. 9 The gain switching for PGA. The C/I/R mode testing is shown in Fig. 10 (a) to (c), respectively. For capacitance mode, we use the 3-bit calibration array as a test signal to examine its function. As shown in Fig. 10, the conversion gain in capacitance mode is about 180 mv/pf while the conversion gain in the current mode is 155 mv/na. Finally, in the resistance mode, the conversion gain is 38.8 mv/kω. In fact, it is actually defined by the bridge resistors we used. Each resistor of the bridge is about 0k ohm. All the results are close to the simulation and meet the requirements. Fig. 11 Static performance measurement

5 For the dynamic performance measurement, fast Fourier transform (FFT) test were performed based on 819 ( 13 ) captured data points. The conversion rate is 00 KSPS, and the analog input signals are applied to the device under test (DUT). Figure 1 shows the dynamic performance FFT results. Fig. 14 The proposed (a)reconfigurable interface circuit (b)sar ADC die photo. Fig. 1 Dynamic performance measure- ment result Figure 13 represents SNDR and ENOB measurement results versus input signal frequency. Fig. 13 measured dynamic parameters The system parameters and design arrangements are shown in table I. The die photo of the proposed reconfigurable interface circuit and SAR ADC are shown in Fig. 14. TABLE I Reconfigurable interface circuit 10-bit SAR ADC Technology TSMC 0.18μm TSMC 0.18μm Supply voltage 1V 1V OPA performance PGA Gain Range Gain Output range Bandwidth Phase margin 7bits 0.78~100 V/V 87dB 800mV 1.56 MHz 45 deg Sampling frequency Data rate SNDR Assorted Input I, R, V, C ENOB Power Consumption 16μW 00kHz 100kHz 4.5uW IV. CONCLUSION This paper proposed a low-power reconfigurable front-end circuit and a 10-bit SAR ADC by using TSMC 0.18um CMOS process. The die area of them are 1.6 mm x 0.9 mm and 1. mm x 0.9 mm, respectively. The average power consumption are 16μW and 4.5μW, respectively. Both of them operate at 1V supply voltage. The reconfigurable interface circuit can apply to capacitance, resistance, current and voltage type sensors. The ENOB (effective number of bits) of ADC is 7.93bit. The digitized signals can be further processed by the back-end digital processor for wireless communications use. The proposed sensor readout is highly adaptive and can be used in diverse applications in the world. ACKNOWLEDGMENT This work was supported in part by the National Science Council, Taiwan, R.O.C. (Contract No: NSC E MY3). REFERENCES [1] Jichun Zhang, Junwei Zhou, and Andrew Mason, Highly Adaptive Transducer Interface Circuit for Multiparameter Microsystems, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: regular papers, VOL. 54, NO. 1, JANUARY 007. [] Oysted, K. Wisland, D.T., Piezoresistive CMOS-MEMS pressure sensor with ring oscillator readout including Δ-Σ analog-to-digital converter on-chip, Custom Integrated Circuits Conference, 005.Proceedings of the IEEE 005. [3] P. Cong, N. Chaimanonart,W. H. Ko, and D. J. Young, A Wireless and Batteryless 130 milligram 300μW 10-bit Implantable Blood Pressure Sensing Microsystem for Real-time Genetically Engineered Mice Monitoring, ISSCC, 009, pp [4] J. Laconte, V. Wilmart, D. Flandre, J.-P. Raskin, High-Sensitivity Capacitive Humidity Using 3-Layer Patterned Polyimide Sensing Film, s. Proceedings of IEEE, 003. [5] Meinrad Schienle, Christian Paulus, Alexander Frey, Franz Hofmann, Birgit Holzapfl, Petra Schindler-Bauer, and Roland Thewes, A Fully Electronic DNA With 18 Positions and In-Pixel A/D Conversion, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, DECEMBER 004. Chip Area (PAD included) 1.6 mm x 0.9 mm 1. mm x 0.9 mm